View LT8710_9050691.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

1 for more information www.linear.com/LT8710 typical a pplica t ion fea t ures descrip t ion synchronous sepic/ inverting/ boost contr oller with output current control the lt ? 8710 is a synchronous pwm dc/dc controller with a rail-to-rail output current monitor and control. the LT8710 is ideal for many types of power supply topologies and can be easily configured for boost, sepic, inverting, or flyback configurations. the LT8710 s rail- to- rail output current monitor and control allows the part to be configured in current limited applica - tions such as battery charging. the flag pin can be used as a power good indication or c/10 indication allowing for accurate bulk and float battery voltages. the LT8710s switching frequency range can be set be - tween 100 khz and 750 khz using an external resistor or synchronized to an external clock. the LT8710 also features innovative en/fbin pin cir - cuitry that allows for slowly varying input signals and an adjustable undervoltage lockout function. the pin is also used for input voltage regulation to avoid collapsing a high impedance input supply. additional features such as frequency foldback and soft-start are integrated. the LT8710 is available in a 20-lead tssop package. 300khz inverter generates C5v from a 4.5v to 25v input a pplica t ions l, lt , lt c , lt m , linear technology and the linear logo are registered trademarks of linear technology corporation. all other trademarks are the property of their respective owners. protected by u.s. patents, including 7579816. n wide input range: 4.5v to 80v n rail-to-rail output current monitor and control n input v oltage regulation for high impedance inputs n c/10 or power good indication pin n mode pin for forced ccm or pulse-skipping operation n switching frequency up to 750khz n easily configurable as a boost, sepic, inverting or flyback converter with single feedback pin n can be synchronized to external clock n high gain en/fbin pin accepts slowly varying input signals n 20-lead tssop package n high power local power supply n wide input voltage range sepic/inverting n lead acid battery charger n automotive engine control unit (ecu) power n solar panel power converter efficiency and power loss imon ss gnd csp tg csn bg LT8710 8710 ta01a mode intv cc rt sync v in en/fbin bias intv ee fbx flag v c isn isp v out ?5v 7a v in 4.5v to 25v 13.3k 2.2h 120f 2.2f 100f 2 10k 10f 4 118k 1.5m 4m 2.2h ? ? 10f 2 60.4k 11.5k 2.2f intv cc 330f + 47nf 220nf 3.3nf 100pf + 499 0.47f load current (a) 0 efficiency (%) power loss (w) 100 80 90 70 65 50 40 30 20 8 6 7 5 4 3 2 1 0 1 4 5 6 8710 ta01b 7 2 3 v in = 5v v in = 12v lt 8710 8710f
2 for more information www.linear.com/LT8710 p in c on f igura t ion a bsolu t e maxi m u m r a t ings (note 1) fe package 20-lead plastic tssop 1 2 3 4 5 6 7 8 9 10 top view 20 19 18 17 16 15 14 13 12 11 fbx v c ss flag imon isn isp bias intv ee tg gnd sync rt mode en/fbin csp csn v in intv cc bg 21 gnd t jmax = 125c, ja = 38c/w, jc = 10c/w exposed pad ( pin 21) is gnd, must be soldered to pcb o r d er i n f or m a t ion lead free finish tape and reel part marking* package description temperature range LT8710efe#pbf LT8710efe#trpbf LT8710fe 20-lead plastic tssop C40c to 125c LT8710ife#pbf LT8710ife#trpbf LT8710fe 20-lead plastic tssop C40c to 125c consult lt c marketing for parts specified with wider operating temperature ranges. *the temperature grade is identified by a label on the shipping container. for more information on lead free part marking, go to: http://www.linear.com/leadfree/ for more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/ v in voltage ................................................ C 0.3 v to 80 v bias voltage .............................................. C 0.3 v to 80 v en / fbin voltage ......................................... C 0.3 v to 80 v bg voltage ............................................................ no te 5 tg voltage ............................................................ no te 5 rt voltage ................................................... C 0.3 v to 5v ss voltage ................................................... C 0.3 v to 3v fbx voltage ................................................................. 5 v fbx current ............................................................ C1 ma v c voltage .................................................... C 0.3 v to 2v sync voltage ............................................ C 0.3 v to 5.5 v flag voltage ............................................... C 0.3 v to 7v flag current ......................................................... 1 ma mode voltage ............................................ C 0.3 v to 40 v intv cc voltage ............................................ C 0.3 v to 7v intv ee voltage ...................................................... note 5 csp voltage ................................................. C0. 3 v to 2v csn voltage ................................................. C 0.3 v to 2v isp voltage ................................. i sn C 0.4 v to isn + 2v isn voltage ................................................ C0. 3 v to 80 v imon voltage ............................................ C 0.3 v to 2.5 v operating junction temperature range lt 87 10 e ............................................. C 40 c to 125 c lt 87 10 i .............................................. C40 c to 12 5 c storage temperature range .................. C 65 c to 150 c lead temperature ( soldering , 10 sec ) ................... 30 0 c lt 8710 8710f
3 for more information www.linear.com/LT8710 e lec t rical c harac t eris t ics parameter conditions min typ max units minimum operating input voltage v in or v bias v in if v bias 4.5v l 0 4.25 4.5 v v quiescent current, i vin v bias = v isn = 7.5v, not switching v bias = 6.3v , v intvee = v isn = 0v , not switching 4 5.5 5.5 7.5 ma ma quiescent current in shutdown v en/fbin = 0v 0 1 a en/fbin active mode en/fbin rising l 1.64 1.7 1.76 v en/fbin chip enable en/fbin rising en/fbin falling l l 1.22 1.18 1.3 1.26 1.38 1.34 v v en /fbin chip enable hysteresis 44 mv en/fbin input v oltage low shutdown mode l 0.3 v en/fbin pin bias current v en/fbin = 3v v en/fbin = 1.7v v en/fbin = 1.6v v en/fbin = 0v 14 13 44 19.5 17.5 0 60 25 22.5 0.1 a a a a ss charge current v ss = 0v, current flows out of ss pin l 7 10.1 13.8 a ss low detection voltage part exiting undervoltage lockout l 18 50 82 mv ss hi detection voltage ss rising ss falling 1.5 1.3 1.8 1.7 2.1 2.05 v v ss hi detection hysteresis 100 mv low dropout regulators, int v cc and intv ee intv cc voltage i intvcc = 10ma l 6.2 6.3 6.4 v intv cc undervoltage lockout intv cc rising intv cc falling l l 3.88 3.5 4 3.73 4.12 3.95 v v int v cc undervoltage lockout hysteresis 270 mv intv cc dropout voltage v in C intv cc , v in = 6v, v bias = 0v, i intvcc = 10ma v bias C v intvcc , v in = 0v, v bias = 6v, i intvcc = 10ma 255 280 mv mv intv cc load regulation v in = 12v, v bias = 0v, i intvcc = 0ma to 80ma v in = 0v, v bias = 12v, i intvcc = 0ma to 40ma C0.44 C0.34 C2 C2 % % intv cc line regulation 10v v in 80v, v bias = 0v, i intvcc = 10ma 10v v bias 80v, v in = 0v, i intvcc = 10ma C0.003 C0.006 C0.03 C0.03 %/v %/v intv cc maximum external load current 5 ma intv ee voltage, v bias C v intvee i intvee = 10ma l 6.03 6.18 6.33 v intv ee undervoltage lockout, v bias C v intvee v bias C v intvee rising v bias C v intvee falling l l 3.24 2.94 3.42 3.22 3.6 3.48 v v int v ee undervoltage lockout hysteresis, v bias C v intvee 200 mv intv ee dropout voltage, v intvee v bias = 6v, i intvee = 10ma 0.75 v control loops (refer to block diagram to locate amplifiers) current limit voltage, v csp C v csn v fbx = 1.1v, minimum duty cycle v fbx = 1.1v, maximum duty cycle l l 46 23 50 31 54 38 mv mv v fbx = 1.4v, mode = 0v, minimum duty cycle v fbx = 1.4v, mode = 0v, maximum duty cycle l l C23 C38 C32 C51 C41 C65 mv mv fbx positive output regulation v oltage, ea1 l 1.191 1.213 1.237 v fbx negative output regulation voltage, ea2 l C2 9.6 21 mv the l denotes the specifications which apply over the full operating temperature range, otherwise specifications for each channel are at t a = 25c. v in = 12v, v en/fbin = 12v, v bias = 12v, unless otherwise noted (note 2). lt 8710 8710f
4 for more information www.linear.com/LT8710 parameter conditions min typ max units positive fbx pin bias current v fbx = positive fbx reg voltage, current into pin l 81.9 83.7 85.6 a negative fbx pin bias current v fbx = negative fbx reg voltage, current out of pin l 81.1 83.1 85.2 a fbx amp transconductance, ea1 or ea2 i = 2a 200 mhos fbx amp v oltage gain, ea1 or ea2 70 v/v fbx line regulation 4.5v v in 80v, v bias = 0v C0.02 C0.001 0.02 %/v output current sense regulation voltage, v isp C v isn v isn = 80v, v fbx = 1v v isn = 12v, v fbx = 1v v isn = 0v, v fbx = 1v v isn = 12v, v fbx = 1v, intv ee in uvlo and v ss > 1.8v l l l l 43 43 40 17 50 50 50 25 57 57 60 34 mv mv mv mv imon regulation v oltage, ea3 v fbx = 1v v fbx = 1v, intv ee in uvlo and v ss > 1.8v l l 1.184 0.885 1.213 0.916 1.24 0.947 v v output current sense amp transconductance, a6 i = 10a 1000 mhos output current sense amp voltage gain, a6 11.9 v/v output current sense amp input dynamic range, a6 negative input range, v isp C v isn positive input range, v isp C v isn 500 C51.8 mv mv imon amp t ransconductance, ea3 i = 2a, v fbx = 1v 165 mhos imon amp voltage gain, ea3 v fbx = 1v 65 v/v en/fbin input regulation voltage, ea4 v fbx = 1v l 1.55 1.607 1.662 v en/fbin amp transconductance, ea4 i = 2a, v fbx = 1v 140 mhos en/fbin amp voltage gain, ea4 v fbx = 1v 55 v/v mode forced ccm threshold to exit forced ccm mode, mode rising to enter forced ccm mode, mode falling l l 1.19 1.125 1.224 1.175 1.258 1.23 v v mode for ced ccm threshold hysteresis 49 mv dcm comparator threshold in pulse-skipping mode, mode = 2v v isn = 80v, to enter dcm mode, v isp C v isn falling v isn = 12v, to enter dcm mode, v isp C v isn falling v isn = 0v, to enter dcm mode, v isp C v isn falling l l l C4.5 C4.5 C7.5 2.8 2.8 2.8 10 10 13 mv mv mv dcm comparator threshold in for ced ccm, mode =0v v isn = 80v, to enter dcm mode, v isp C v isn falling v isn = 12v, to enter dcm mode, v isp C v isn falling v isn = 0v, to enter dcm mode, v isp C v isn falling l l l C220 C220 C220 C300 C300 C300 C380 C380 C380 mv mv mv oscillator switching frequency, f osc r t = 46.4k r t = 357k l l 640 85 750 100 860 115 khz khz switching frequency in foldback compared to normal f osc 1/5 ratio switching frequency range free-running or synchronizing l 100 750 khz sync high level for sync l 1.5 v sync low level for sync l 0.4 v sync clock pulse duty cycle v sync = 0v to 3v 20 80 % recommended min sync ratio f sync /f osc 3/4 e lec t rical c harac t eris t ics the l denotes the specifications which apply over the full operating temperature range, otherwise specifications for each channel are at t a = 25c. v in = 12v, v en/fbin = 12v, v bias = 12v, unless otherwise noted (note 2). lt 8710 8710f
5 for more information www.linear.com/LT8710 parameter conditions min typ max units gate drivers, bg and tg bg rise time c bg = 3300pf (note 3) 24 ns bg fall time c bg = 3300pf (note 3) 21 ns tg rise time c tg = 3300pf (note 3) 15 ns tg fall time c tg = 3300pf (note 3) 16 ns bg and tg non-overlap time tg rising to bg rising, c bg = c tg = 3300pf (note 3) bg falling to tg falling, c bg = c tg = 3300pf (note 3) 80 45 140 90 220 150 ns ns bg minimum on-t ime c bg = c tg = 3300pf 150 420 ns bg minimum off-time c bg = c tg = 3300pf 100 480 ns tg minimum on-time c bg = c tg = 3300pf 0 150 ns tg minimum off-time c bg = c tg = 3300pf 290 770 ns c/10 and power good indicators, flag flag c/10 indicator threshold v isp C v isn falling, v fbx = 1.215v v isp C v isn rising, v fbx = 1.215v l l 1 4 5 10 16 23 mv mv flag c/10 indicator hysteresis 5 mv flag power good threshold for positive fbx v oltage v fbx rising, v isp C v isn = 0v v fbx falling, v isp C v isn = 0v l l 1.127 1.062 1.153 1.095 1.184 1.126 v v flag power good threshold for negative fbx v oltage v fbx falling, v isp C v isn = 0v v fbx rising, v isp C v isn = 0v l l 46 103 68.5 126 90 152 mv mv flag power good hysteresis for positive or negative fbx v oltage 58 mv flag anti-glitch delay from c/10 or power good threshold t rip to flag toggle 100 s flag output v oltage low 100a into flag pin l 9 50 mv flag leakage current v flag = 7v, flag off 0.01 1 a note 1: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. exposure to any absolute maximum rating condition for extended periods may affect device reliability and lifetime. note 2: the LT8710e is guaranteed to meet performance specifications from 0c to 125c junction temperature. specifications over the C40c to 125c operating temperature range are assured by design, characterization and correlation with statistical process controls. the LT8710i is guaranteed over the full C40c to 125c operating junction temperature range. note 3: rise and fall times are measured using 10% and 90% levels. delay times are measured using 50% levels. note 4: this ic includes overtemperature protection that is intended to protect the device during momentary overload conditions. junction temperature will exceed 125c when overtemperature protection is active. continuous operation over the specified maximum operating junction temperature may impair device reliability. note 5 : do not apply a positive or negative voltage or current source to the bg, tg, and intv ee pins, otherwise permanent damage may occur. e lec t rical c harac t eris t ics the l denotes the specifications which apply over the full operating temperature range, otherwise specifications for each channel are at t a = 25c. v in = 12v, v en/fbin = 12v, v bias = 12v, unless otherwise noted (note 2). lt 8710 8710f
6 for more information www.linear.com/LT8710 positive and negative output voltage regulation (fbx) positive and negative fbx current at output voltage regulation input voltage regulation (en/fbin) input voltage regulation vs fbx (en/fbin) output current sense regulation voltage (isp-isn and imon) output current sense regulation voltage vs fbx (isp-isn and imon) max current limit vs duty cycle (csp - csn) max current limit vs temperature at min dc (csp - csn) max current limit vs ss (csp - csn) typical p er f or m ance c harac t eris t ics t a = 25c, unless otherwise noted. duty cycle (%) 0 max positive csp-csn (mv) max negative csp-csn (mv) 60 50 55 40 30 45 35 25 20 ?20 ?30 ?25 ?40 ?50 ?35 ?45 ?55 ?60 50 20 70 80 90 8710 g01 100 30 40 10 60 f osc = 300khz temperature (c) ?50 max positive csp-csn (mv) max negative csp-csn (mv) 56 52 54 50 48 46 44 ?26 ?30 ?28 ?34 ?32 ?36 ?38 50 ?25 75 100 8710 g02 125 0 25 ss (v) 0.0 csp-csn (mv) 60 40 50 30 20 10 0 0.8 0.2 1 1.2 1.4 8710 g03 1.6 0.4 0.6 temperature (c) ?50 en/fbin voltage (v) 1.63 1.61 1.62 1.60 1.59 1.58 1.57 ?25 50 75 100 8710 g06 125 0 25 fbx (v) 0.6 en/fbin (v) 2.0 1.8 1.9 1.7 1.6 1.5 1.4 0.7 1 1.1 1.2 8710 g07 1.3 0.8 0.9 temperature (c) ?50 positive fbx voltage (v) negative fbx voltage (mv) 1.2225 1.2175 1.2200 1.2150 1.2125 1.2100 1.2075 15.0 10.0 12.5 7.5 5.0 2.5 0 ?25 50 75 100 8710 g04 125 0 25 temperature (c) ?50 positive fbx current into pin (a) negative fbx current out of pin (a) 86 84 85 83 82 81 80 86 84 85 83 82 81 80 ?25 50 75 100 8710 g05 125 0 25 temperature (c) ?50 average isp-isn (mv) imon (v) 57.5 52.5 55.0 50.0 47.5 45.0 42.5 1.2175 1.2125 1.2150 1.2100 1.2075 1.2050 1.2025 ?25 50 75 100 8710 g08 125 0 25 imon ave isp-isn fbx (v) 0.6 average isp-isn (mv) imon (v) 60 50 55 45 40 35 30 1.30 1.20 1.25 1.15 1.10 1.05 1.00 0.7 1 1.1 1.2 8710 g09 1.3 0.8 0.9 imon ave isp-isn lt 8710 8710f
7 for more information www.linear.com/LT8710 mode forced ccm thresholds en/fbin chip enable and active mode thresholds en/fbin pin current oscillator frequency vs temperature oscillator frequency during soft-start bg and tg transition time dcm thresholds (isp-isn) power good thresholds (fbx) c/10 thresholds (isp-isn) typical p er f or m ance c harac t eris t ics t a = 25c, unless otherwise noted. temperature (c) ?50 positive fbx (v) negative fbx (v) 1.16 1.14 1.15 1.13 1.12 1.11 1.10 1.09 1.08 140 120 130 110 100 90 80 70 60 ?25 50 75 100 8710 g11 125 0 25 falling rising en/fbin voltage (v) 0 en/fbin pin current (a) 35 30 25 15 10 20 5 0 0.25 1 1.25 1.5 1.75 8710 g15 2 0.5 0.75 ?40c 25c 125c fbx voltage (v) 0 normalized oscillator frequency (f sw /f nom ) 1 1/2 1/3 1/5 1/4 0 0.2 0.8 1 1.2 8710 g17 0.4 0.6 noninverting configurations inverting configurations temperature (c) ?50 f osc (khz) 900 800 700 500 400 200 100 600 300 0 ?25 50 75 100 125 8710 g16 0 25 r t = 46.4k r t = 357k temperature (c) ?50 isp-isn (mv) isp-isn (mv) 6 4 5 3 2 1 0 ?280 ?300 ?290 ?310 ?320 ?330 ?340 ?25 50 75 100 8710 g10 125 0 25 mode = 0v, fcm mode = 2v, dcm temperature (c) ?50 average isp-isn (mv) 14 10 12 8 6 4 2 0 ?25 50 75 100 8710 g12 125 0 25 falling rising cap load (nf) 0 transition time (ns) 80 70 60 40 30 10 50 20 0 2 8 10 8710 g18 4 6 bg rising bg falling tg rising tg falling temperature (c) ?50 mode (v) 1.24 1.22 1.23 1.21 1.20 1.18 1.17 1.19 1.16 1.15 1.14 ?25 50 75 100 8710 g13 125 0 25 falling, enter fcm rising, exit fcm temperature (c) ?50 en/fbin chip enable (v) en/fbin active mode (v) 1.40 1.36 1.38 1.34 1.32 1.28 1.26 1.30 1.24 1.22 1.20 1.75 1.71 1.73 1.69 1.67 1.63 1.61 1.59 1.57 1.65 1.55 ?25 50 75 100 8710 g14 125 0 25 falling rising rising only lt 8710 8710f
8 for more information www.linear.com/LT8710 intv cc current limit vs v in or bias intv cc dropout from v in or bias intv ee vs temperature intv ee uvlo vs temperature intv ee current limit vs bias intv ee dropout (bias = 6v) minimum operating input voltage intv cc vs temperature intv cc uvlo vs temperature typical p er f or m ance c harac t eris t ics t a = 25c, unless otherwise noted. temperature (c) ?50 v in or v bias (v) 4.35 4.33 4.29 4.25 4.23 4.21 4.19 4.17 4.31 4.27 4.15 ?25 75 100 125 8710 g19 0 25 50 temperature (c) ?50 intv cc (v) 6.40 6.28 6.24 6.36 6.32 6.20 ?25 75 100 125 8710 g20 0 25 50 i intvcc = 10ma temperature (c) ?50 intv cc (v) 4.2 3.9 3.8 3.7 3.6 4.1 4.0 3.5 ?25 75 100 125 8710 g21 0 25 50 rising falling input voltage (v) 10 intv cc current limit (ma) 150 100 75 50 25 125 0 20 60 70 80 8710 g22 30 40 50 v in bias v in or bias intv cc > 3.5v intv cc > 3.5v intv cc < 3.5v intv cc load current (ma) 100 input - intv cc (v) 500 400 350 300 250 450 200 20 60 70 80 8710 g23 30 40 50 v in bias temperature (c) ?25?50 bias - intv ee (v) 3.6 3.4 3.3 3.2 3.1 3.5 3.0 0 100 125 8710 g25 25 50 75 falling rising bias (v) 2010 intv ee current limit (ma) 75 45 30 15 60 0 30 70 80 8710 g26 40 50 60 bias - intv ee = 5v intv ee load current (ma) 100 intv ee (v) 1.2 1.0 0.9 0.7 0.6 0.5 0.8 1.1 0.4 40 50 8710 g27 20 30 ?40c 25c 125c temperature (c) ?25?50 bias - intv ee (v) 6.28 6.20 6.16 6.12 6.24 6.08 0 100 125 8710 g24 25 50 75 i intvee = 10ma lt 8710 8710f
9 for more information www.linear.com/LT8710 p in func t ions fbx (pin 1): positive and negative feedback pin. for a boost, sepic, or inverting converter, tie a resistor from the fbx pin to v out according to the following equations: r fbx = v out ? 1.213v 83.7a ? ? ? ? ; boost or sepic converter r fbx = |v out |+9.6mv 83.1a ? ? ? ? ; inverting converter v c (pin 2): error amplifier output pin. tie external com- pensation network to this pin. ss ( pin 3): soft-start pin. place a soft-start capacitor here that is greater than 5 x the imon capacitor. upon start-up, the ss pin will be charged by a (nominally) 260 k resistor to ~2.7 v. during a current overload as seen by isp - isn, overtemperature, or uvlo condition, the ss pin will be quickly discharged to reset the part. once those conditions are clear, the part will attempt to restart. flag (pin 4): power good or c/10 indication pin. the flag pin functions as an active high power good pin if c/10 is true. alternatively, the flag pin functions as an active high c/10 indication pin if power is good. power is good when fbx < 68.5 mv or fbx > 1.153 v and has 58mv of hysteresis. when fbx = 1.153 v, its 5% below regulation which corresponds to ~10% below regulation on v out ( for v out > 8 v). active high c/10 indication is when the charge current seen by the isp and isn pins is less than 10% of full current ( v isp C v isn < 5 mv) as the charge current decreases. for increasing charge currents, the c/10 threshold has to reach 20% of full current (v isp C v isn > 10 mv). the c/10 indication can be used to set the bulk and float voltage when charging a battery. for either c/10 or power good indicators, there is a 100s anti-glitch delay. a pull-up resistor or some other form of pull-up network needs to exist on this pin to use these features. see the block diagram and applications section for more information. imon (pin 5): output current sense monitor output pin. outputs a voltage that is proportional to the voltage seen across the isp and isn pins. v imon = 11.9 ? (v isp C isn + 51.8mv) since the voltage across the isp and isn pins is ac, a filtering capacitor is needed on the imon pin to average out the isp and isn voltage. recommended capacitor value is 10 nf to 100 nf. a 51.8 mv offset is added to the amplifier, so when the average isp C isn voltage is 0v, the imon voltage is 616 mv. when the average voltage across the isp and isn pins is 50 mv, the imon pin will output 1.213v. do not resistively load down this pin. isn, isp (pins 6, 7): output current sense negative and positive input pins respectively. kelvin connect isn and isp pins to a sense resistor to limit the output current. the commanded nfet current will limit the voltage difference across the sense resistor to 50mv. bias (pin 8): alternate input supply and pfet bias pin. must be locally bypassed. the bias pin sets the top rail for the tg gate driver. must connect to the converters v out for a positive output voltage or intv cc for a converters negative output voltage. intv ee (pin 9): 6.18 v-below-bias regulator pin. must be locally bypassed with a minimum capacitance of 2.2f to bias. this pin sets the bottom rail for the tg gate driver. the tg gate driver can begin switching when bias C intv ee exceeds 3.42v ( typical). connect pin to ground for an inverting converter. tg (pin 10): pfet gate drive pin. low and high levels are bias C intv ee and bias respectively. bg (pin 11): nfet gate drive pin. low and high levels are gnd and intv cc respectively. intv cc (pin 12): 6.3 v dual input ldo regulator pin. must be locally bypassed with a minimum capacitance of 2.2f to gnd. logic will choose to run intv cc from the v in or bias pins. a maximum 5 ma external load can connect to the intv cc pin. the undervoltage lockout on intv cc is 4v ( typical). the bg gate driver can begin switching when intv cc exceeds 4v (typical). v in (pin 13): input supply pin. must be locally bypassed. can run down to 0v as long as bias > 4.5v. csn, csp (pins 14, 15): nfet current sense negative and positive input pins respectively. kelvin connect these pins to a sense resistor to limit the nfet switch current. the maximum sense voltage at low duty cycle is 50mv. en/fbin (pin 16): enable and input voltage regulation pin. in conjunction with the uvlo ( undervoltage lockout) circuit, this pin is used to enable/disable the chip and restart the soft-start sequence. the en/fbin pin is also lt 8710 8710f
10 for more information www.linear.com/LT8710 p in func t ions used to limit the nfet current to avoid collapsing the input supply. drive below 0.3 v to disable the chip with very low quiescent current. drive above 1.7v ( typical) to activate the chip and restart the soft-start sequence. the commanded nfet current will adjust when the en/ fbin pin voltage drops between 1.55 v and 1.662 v. see the block diagram and applications section for more information. do not float this pin. mode ( pin 17): forced ccm mode pin. drive below 1.175v (typical) to operate in forced ccm. drive above 1.224v (typical) to operate in dcm and/or pulse-skipping mode at light loads. if ss < 1.8v ( typical) or intv ee is in uvlo, the part will operate in dcm at light load. rt (pin 18): timing resistor pin. adjusts the LT8710s switching frequency. place a resistor from this pin to ground to set the frequency to a fixed free-running level. do not float this pin. sync (pin 19): to synchronize the switching frequency to an outside clock, simply drive this pin with a clock. the high voltage level of the clock must exceed 1.5 v, and the low level must be less than 0.4 v. drive this pin to less than 0.4 v to revert to the internal free running clock. see the applications information section for more information. gnd (pin 20, exposed pad pin 21): ground. must be soldered directly to local ground plane. b lock diagra m figure 1. block diagram 2.7v mode dcm_en isn imon dcm_en 666.5mv chrg pg isp dcm_en 8710 bd tg driver disable ? + ss gnd uvlo 100s anti-glitch level shift start-up and reset logic adjustable oscillator soft-start 51.5k 1.3v 1.7v r in2 ? + ? + ea1 ea2 rt v c r c r t sync imon isn fbx isp n ss en/fbin 1.607v sync block slope compensation c vcc 6.3v v in v in intv cc en/fbin bias csn mn r sense1 r sense2 bg tg bias driver driver bias ? 6.18v intv ee intv cc flag intv cc bias ? + a5 csp l1 c in c1 mp ? l2 ? ldo logic ldo uvlo 1.213v reference en/fbin logic imon 1.38v ? + die temp 175c ? + 1.153v ? + 68.5mv 1.213v ? + ? + 1.224v ? + 1.8v ? + 50mv fbx dcm_en 260k driver disable c ss r in1 frequency foldback a7 sr1 r s q ? + 14.5k 14.5k 1.213v 11.9k 51.8mv ? + ea4 ? + ea3 ? + a6 +? c imon c f c c ldo c vee r fbx c out v out c2 r1 d1 lt 8710 8710f
11 for more information www.linear.com/LT8710 s t a t e diagra m figure 2. state diagram 8710 sd ? all switches disabled chip off ? ss pulled low ? intv cc charges up initialize ? ss slowly charges up ? v c pulled low active mode ? pfet turns off for remainder of cycle if isp-isn voltage falls below 2.8mv (typ) ? for very light load, part may skip pulses dcm at light load ? v c commands peak inductor current to maintain regulation regulation ? output current limited to 25mv (typ) average across the isp-isn pins output current foldback ? bg and tg switch at constant frequency ? inductor current can reverse ? if isp-isn voltage goes below C300mv (typ), pfet turns off so inductor current goes more positive forced ccm operation ? ss discharges quickly ? switcher disabled en/fbin < 1.3v (typ) or v in and bias < 4.5v (max) 1.3v < en/fbin < 1.7v (typ) and v in or bias > 4.5v en/fbin > 1.7v and v in or bias > 4.5v and intv cc > 4v (typ) intv ee regulator in uvlo and ss > 1.8v (typ) mode < 1.175v (typ) and ss > 1.8v (typ) mode > 1.224v (typ) ss < 50mv reset reset detected ? no reset conditions detected reset over reset reset ? nfet begins switching ? pfet starts switching when intv ee regulator is out of uvlo begin switching reset reset reset regulation = output voltage (fbx) input voltage (en/fbin) output current (isp-isn and imon) reset = uvlo on v in or bias ( < 4.5v (max)) uvlo on intv cc ( < 4v (typ)) en/fbin < 1.7v (typ) at 1st power-up en/fbin < 1.26v (typ) after active mode set overcurrent (isp C isn > 63.6mv average (typ)) overtemperature (t j > 175c (typ)) lt 8710 8710f
12 for more information www.linear.com/LT8710 o pera t ion operation C overview the LT8710 uses a constant frequency, current mode control scheme to provide excellent line and load regula - tion. the parts undervoltage lockout ( uvlo) function, together with soft-start and frequency foldback, offers a controlled means of starting up. output voltage, output current, and input voltage have control over the commanded peak current which allows a wide range of applications to be built using the LT8710. synchronous switching makes high efficiency and high output current applications pos - sible. when operating at light currents with the mode pin > 1.224 v ( typical), the LT8710 will disable synchronous operation for part of the cycle to prevent negative switch currents. refer to the block diagram (figure 1) and the state diagram (figure 2) for the following description of the parts operation. operation C start-up several functions are provided to enable a very clean start-up of the LT8710. precise turn-on voltages the en/fbin pin has two voltage levels for activating the part; one that enables the part and allows internal rails to operate and a 2 nd voltage threshold which activates a soft-start cycle and switching can begin. to enable the part, take the en/fbin pin above 1.3v (typical ). this com- parator has 44 mv of hysteresis to protect against glitches and slow ramping. to activate a soft-start cycle and allow switching, take en/fbin above 1.7v ( typical). when en/ fbin exceeds 1.7v ( typical), the logic state is latched so that if en/fbin drops between 1.3 v to 1.7 v ( typical), the ss pin is not pulled low by the en/fbin pin. the en/fbin pin is also used for input voltage regulation which is at 1.607v ( typical). input voltage regulation is explained in more detail in the operation C regulation section. taking the en/fbin pin below 0.3 v shuts down the chip, result - ing in extremely low quiescent current. see figure 3 that illustrates the different en/fbin voltage thresholds. under voltage lockout (uvlo) the LT8710 has internal uvlo circuitry that disables the chip when the greater of v in or bias < 4.5v (maximum) or intv cc < 4v ( typical). the en/fbin pin can also be used to create a configurable uvlo. see the applications section for more information. soft-start of switch current the soft-start circuitry provides for a gradual ramp-up of the switch current ( refer to max current limit vs ss in typical performance characteristics). when the part is brought out of shutdown, the external ss capacitor is first discharged which resets the states of the logic circuits in the chip. once intv cc comes out of uvlo (> 4 v typical ) and the chip is in active mode, an integrated 260k resistor pulls the ss pin to ~2.7 v at a ramp rate set by the external capacitor connected to the pin. typical values for the soft-start capacitor range from 100 nf to 1f. the soft-start capacitor should also be at least 5x greater than the external capacitor connected to the imon pin to avoid start-up issues. figure 3. en/fbin modes of operation 8710 f03 active mode threshold (tolerance) normal operation if active mode set input voltage regulation (only if active mode set) en/fbin (v) chip enable threshold (hystersis and tolerance) lockout (switch off, ss cap discharged, intv cc and intv ee disabled) shutdown (low quiescent current) switch off, intv cc and intv ee enabled, ss cap discharged if active mode not set active mode (normal operation) (mode latched until en/fbin drops below chip enable treshold) 1.76v 1.64v 1.662v 1.55v 1.38v 1.18v 0.3v 0v lt 8710 8710f
13 for more information www.linear.com/LT8710 frequency foldback the frequency foldback circuitry reduces the switching frequency when 175mv < fbx < 1.01v ( typical). this feature lowers the minimum duty cycle that the part can achieve, thus allowing better control of the inductor current at start-up. when the fbx voltage is pulled outside of this range, the switching frequency returns to normal. if the part is configured to be in forced continuous conduction mode (mode pin is driven below 1.175 v), then the frequency foldback circuitry is disabled as long as intv ee is not in uvlo and the ss pin is higher than the ss hi threshold. note that the peak inductor current at start-up is a function of many variables including load profile, output capacitance, target v out , v in , switching frequency, etc. operation C regulation use the block diagram when stepping through the following description of the LT8710 operating in regulation. also, assume the converters load current is high enough such that the part is operating in synchronous switching. the LT8710 has three modes of regulation: 1. output v oltage (via fbx pin) 2. input v oltage (via en/fbin pin) 3. output current (via isp, isn, and imon pins) all three of these regulation loops control the peak com- manded current through the external nfet, mn. this operation is the same regardless of the regulation mode, so that will be described first. at the start of each oscillator cycle, the sr latch ( sr1) is set, which first turns off the external pfet, mp, and then turns on the external nfet, mn. the nfets source current flows through an external current sense resistor (r sense1 ) generating a voltage proportional to the nfet switch current. this voltage is then amplified by a5 and added to a stabilizing ramp. the resulting sum is fed into the positive terminal of the pwm comparator a7. when the voltage on the positive input of a7 exceeds the voltage on the negative input (v c pin), the sr latch is reset, turning off the nfet and then turning on the pfet. the voltage on the v c pin is controlled by one of the regulation loops, or a combination of regulation loops. for simplicity, each mode of regulation will be described independently so that only one of the modes of regulation is in command of the LT8710. output voltage regulation a single external resistor is used to set the target output voltage. see the pin functions section for selecting the feedback resistor for a desired output voltage. the v c pin voltage ( negative input of a7) is set by ea1 ( or ea2), which is simply an amplified difference between the fbx pin voltage and the reference voltage (1.213 v if the LT8710 is configured as a noninverting converter or 9.6 mv if configured as an inverting converter). in this manner, the fbx error amplifier sets the correct peak current level to maintain output voltage regulation. input voltage regulation a single resistor or resistor divider from the en/fbin pin to the converters input voltage sets the input voltage regulation. it is recommended to use a resistor divider for improved accuracy as described in the setting the input voltage regulation or undervoltage lockout section. the en/fbin pin voltage connects to the positive input of amplifier ea4. the v c pin voltage is set by ea4, which is simply an amplified difference between the en/fbin pin voltage and a 1.607 v reference voltage. in this manner, the en/fbin error amplifier sets the correct peak current level to maintain input voltage regulation. output current regulation an external sense resistor connected between the isp and isn pins ( r sense2 ) sets the maximum output current of the converter when placed in the source of the pfet, mp. a built-in 51.8 mv offset is added to the voltage seen across r sense2 . that voltage is then amplified and outputs to the imon pin. an external capacitor must be placed from imon to ground to filter the amplified chopped voltage thats sensed across r sense2 . the voltage at the imon pin is fed to the negative input of the imon error amplifier, ea3. the v c pin voltage is set by ea3, which is simply an amplified difference between the imon pin voltage and the 1.213v reference voltage. in this manner, the imon error amplifier sets the correct peak current level to maintain output current regulation. o pera t ion lt 8710 8710f
14 for more information www.linear.com/LT8710 note that if the intv ee ldo is in uvlo and ss > 1.8v (typical), then the voltage reference at the positive input of ea3 is 916mv ( typical), resulting in limiting the output current to about half of its set limit. operation C reset conditions the LT8710 has three reset cases. when the part is in reset, the ss pin is pulled low and both power switches, mn and mp, are forced off. once all of the reset conditions are gone, the part is allowed to begin a soft-start sequence and switching can commence. each of the following events can cause the LT8710 to be in reset: 1. uvlo a. the greater of v in and bias is < 4.5v (maximum) b. int v cc < 4v (typical) c. en/fbin < 1.7v (typical) at first power-up 2. over current sensed by imon > 1.38v (typical) 3. die t emperature > 175c operation C power switch control the main power switch is the external nfet ( mn in block diagram) and the synchronous power switch is the ex - ternal pfet ( mp in block diagram). the two switches are never on at the same time, and there is a non-overlap time of ~140 ns and ~90 ns on the rising and falling edges respectively ( see electrical characteristics) to prevent cross conduction. figure 4 below shows the bg and tg (biasCtg) signals: light load current (mode pin) the mode pin can be used to tell the LT8710 to operate in forced ccm regardless of load current, or operate in dcm at light loads. ? mode < 1.175v (typical) = for ced ccm or fcm ? mode > 1.224v (typical) = dcm or pulse-skipping the forced continuous mode ( fcm) allows the inductor current to reverse directions without any switches being forced off. at very light load currents, the inductor cur - rent will swing positive and negative as the appropriate average current is delivered to the output. there are some exceptions that negate the mode pin and force the part to operate in dcm at light loads: 1. the intv ee ldo is in uvlo ( bias C intv ee < 3.42 v typical). 2. ss < 1.8v (typical). 3. the part is in a reset condition. when the LT8710 is in discontinuous mode ( dcm), syn - chronous switch mp is held off whenever mps current falls near 0 current ( less than 2.8mv ( typical) across r sense2 ). this is to prevent current draw from the output and/or feeding current to the input supply. under very light loads, the current comparator a7, may also remain tripped for several cycles ( i.e. skipping pulses). since mp is held off during the skipped pulses, the inductor current will not reverse. operation C c/10 and power good (flag pin) the flag pin is an open-drain pin that functions as an ac - tive high c/10 and power good pin. the flag pin changes states 100s ( typical) after the internal comparators tell the flag pin to change states to reject glitches or tran - sient events. o pera t ion figure 4. synchronous switching 8710 f04 bg on tg on 140ns 90ns lt 8710 8710f
15 for more information www.linear.com/LT8710 c/10 indication if power is good, then the flag pin will function as an active high c/10 indication pin. c/10 is when the charging current ( output current) has dropped to 1/10 its maximum and is useful in battery charging applications. the c/10 comparator monitors the voltage at the imon pin, and when the average isp-isn voltage drops below 5mv (typical), the flag pin pull-down device is turned off, and the flag pin voltage is allowed to pull high. the flag pin will pull low again if the average isp-isn voltage rises above 10mv (typical). the imon voltage corresponding to 5 mv and 10mv on isp C isn is 666.5 mv and 727.5 mv respectively. note that if the LT8710 is set to operate in fcm (mode pin low), then the c/10 comparator is disabled and the flag pin operates only as a power good pin. see the ap - plications section for more information. power good indication if c /10 is detected ( average isp- isn < 5mv typical), then the flag pin functions as an active high power good ( pg) pin. power is good when the fbx voltage is greater than 95% of its regulation target, which corresponds to ~90% of the v out regulation target ( for v out > ~8 v). this corresponds to fbx > 1.153v ( typical) for noninverting converters and fbx < 68.5mv ( typical) for inverting converters. the pg comparators have 58mv of hysteresis to reject glitches. operation C ldo regulators (intv cc and intv ee ) the intv cc ldo regulates at 6.3v ( typical) and is used as the top rail for the bg gate driver. the intv cc ldo can run from v in or bias and will intelligently select to run from the best for minimizing power loss in the chip, but at the same time, select the proper input for maintaining intv cc as close to 6.3 v as possible. the intv cc regulator also has safety features to limit the power dissipation in the internal pass device and also to prevent it from dam - age if the pin is shorted to ground. the uvlo threshold on intv cc is 4v ( typical), and the LT8710 will be in reset until the ldo comes out of uvlo. the intv ee regulator regulates to 6.18v ( typical) below the bias pin voltage. the bias and intv ee voltages are used for the top and bottom rails of the tg gate driver respectively. just like the intv cc regulator, the intv ee regulator has a safety feature to limit the power dissipation in the internal pass device. the tg pin can begin switch- ing after the intv ee regulator comes out of uvlo (3.42v typical across the bias and intv ee pins) and the part is not in a reset condition. o pera t ion lt 8710 8710f
16 for more information www.linear.com/LT8710 boost converter component selection a pplica t ions i n f or m a t ion figure 5. boost converter C the component values given are typical values for a 400khz, 4.5v to 9v to 12v/6a boost. the LT8710 can be configured as a boost converter as in figure 5. this topology generates a positive output voltage where the input voltage is lower than the output voltage. a single feedback resistor sets the output voltage. for a desired output current and output voltage over a given input voltage range, table 1 is a step-by-step set of equations to calculate component values for the LT8710 when operating as a boost converter. refer to more detail in this section and the appendix for further information on the design equations presented in table 1. variable definitions: v in(min) = minimum input voltage v in(max) = maximum input voltage v out = output voltage i out = output current of converter f = switching frequency dc max = power switch duty cycle at v in(min) v cspn = current limit voltage at dc max table 1. boost design equations parameters/equations step 1: inputs pick v in , v out , i out , and f to calculate equations below. step 2: dc max d c max ? 1C v in(min) v out step 3: v cspn see max current limit vs duty cycle plot in typical performance characteristics to find v cspn at dc max . step 4: r sense1 r sense1 0.58 ? v cspn i out ? (1C dc max ) step 5: r sense2 r sense2 0.05 1.6 ? i out step 6: l l typ = r sense1 ? v in(min) 12.5m ? f ? 1? v in(min) v out ? ? ? ? (1) l min = r sense1 ? v out 40m ? f ? 1? v in(min) v out ? v in(min) ? ? ? ? (2) l max1 = r sense1 ? v in(min) 5m ? f ? 1? v in(min) v out ? ? ? ? (3) l max2 = r sense1 ? v in(max) 5m ? f ? 1? v in(max) v out ? ? ? ? (4) ? solve equations 1 to 4 for a range of l values. ? the minimum value of the l range is the higher of l typ and l min . the maximum of the l value range is the lower of l max1 and l max2 . step 7: c out c out i out ? dc max f ? 0.005 ? v out step 8: c in c in dc max 8 ? l ? f 2 ? 0.005 step 9: c imon c imon 100 ? dc max 0.005 ? f step 10: r fbx r fbx = v out C 1.213v 83.7a step 11: r t r t = 35,880 f C 1; f in khz and r t in k? note: the final values for c out and c in may deviate from the above equations in order to obtain desired load transient performance for a particular application. the c out and c in equations assume zero esr, so increase the capacitance accordingly based on the combined esr. imon ss gnd csp tg csn bg LT8710 8710 f05 mode intv cc rt sync v in en/fbin bias intv ee fbx flag v c isp isn v out 12v 6a v in 4.5v to 9v r in1 13.3k r in2 10k l1 1.3h r sense1 r sense2 5m mn 2 c in2 330f 2.2f c out1 22f 4 c in1 22f 4 r t 88.7k 1m mp r fbx 130k r c 18k 2.2f c out2 330f + c ss 220nf c imon 47nf c c 3.3nf c f 100pf + lt 8710 8710f
17 for more information www.linear.com/LT8710 imon ss gnd csp tg csn bg LT8710 8710 f06 mode intv cc rt sync v in en/fbin bias intv ee fbx flag v c isp isn v out 5v 5a v in 3v to 40v(operating) 4.5v to 40v(start-up) r in1 4.02k r in2 10k l1 2.9h r sense1 r sense2 6m mn c in2 220f 2.2f c out1 100f 4 r t 178k 1.5m mp ? r fbx 45.3k r c 8.87k 2.2f c out2 330f + c ss 220nf c imon 47nf c c 6.8nf c f 100pf + l2 2.9h ? c1 10f 2 c in1 10f 6 sepic converter component selection C coupled or uncoupled inductors a pplica t ions i n f or m a t ion figure 6. sepic converter C the component values given are typical values for a 200khz, 3v to 40v to 5v/5a sepic topology using coupled inductors. the LT8710 can also be configured as a sepic as in figure 6. this topology generates a positive output volt- age where the input voltage can be lower, equal, or higher than the output voltage. output disconnect is inherently built into the sepic topology, meaning no dc path exists between the input and output due to capacitor c1. for a desired output current and output voltage over a given input voltage range, table 2 is a step-by-step set of equations to calculate component values for the LT8710 when operating as a sepic converter. refer to more detail in this section and the appendix for further information on the design equations presented in table 2. variable definitions: v in(min) = minimum input voltage v out = output voltage i out = output current of converter f = switching frequency dc max = power switch duty cycle at v in(min) v cspn = current limit voltage at dc max table 2. sepic design equations parameters/equations step 1: inputs pick v in , v out , i out , and f to calculate equations below. step 2: dc max dc max ? v out v in(min) + v out step 3: v cspn see max current limit vs duty cycle plot in typical performance characteristics to find v cspn at dc max . step 4: r sense1 r sense1 0.58 ? v cspn i out ? (1Cdc max ) step 5: r sense2 r sense2 0.05 1.6 ? i out step 6: l l typ = r sense1 ? v out 12.5m ? f ? v in(min) v in(min) + v out ? ? ? ? (1) l min = r sense1 ? v out 40m ? f ? 1? v in(min) v out ? ? ? ? ? ? ? ? 2 ? ? ? ? (2) l max = r sense1 ? v out 5m ? f ? v in(min) v in(min) + v out ? ? ? ? (3) ? solve equations 1, 2, and 3 for a range of l values. ? the minimum value of the l range is the higher of l typ and l min . the maximum of the l value range is l max . ? l = l 1 = l 2 for coupled inductors. ? l = l 1 || l 2 for uncoupled inductors. step 7: c1 c110f typical ( ) ;v rating > v in step 8: c out c out i out ? dc max f ? 0.005 ? v out step 9: c in c in dc max 8 ? l ? f 2 ? 0.005 step 10: c imon c imon 100 ? dc max 0.005 ? f step 11: r fbx r fbx = v out C 1.213v 83.7a step 12: r t r t = 35,880 f C 1; f in khz and r t in k? note: the final values for c out and c in may deviate from the above equations in order to obtain desired load transient performance for a particular application. the c out and c in equations assume zero esr, so increase the capacitance accordingly based on the combined esr. lt 8710 8710f
18 for more information www.linear.com/LT8710 dual inductor inverting component selection C coupled or uncoupled inductors a pplica t ions i n f or m a t ion figure 7. dual inductor inverting converter C the component values given are typical values for a 300khz, 4.5v to 25v to C5v/7a inverting topology using coupled inductors. due to its unique fbx pin, the LT8710 can work in a dual inductor inverting configuration as in figure 7. changing the connections of l2 and the pfet in the sepic topol- ogy, results in generating negative output voltages. this solution results in very low output voltage ripple due to inductor l2 in series with the output. output disconnect is inherently built into this topology due to the capacitor c1. for a desired output current and output voltage over a given input voltage range, table 3 is a step-by-step set of equations to calculate component values for the LT8710 when operating as a dual inductor inverting converter. refer to more detail in this section and the appendix for further information on the design equations presented in table 3. variable definitions: v in(min) = minimum input voltage v in(max) = maximum input voltage v out = output voltage i out = output current of converter f = switching frequency dc max = power switch duty cycle at v in(min) v cspn = current limit voltage at dc max table 3. dual inductor inverting design equations parameters/equations step 1: inputs pick v in , v out , i out , and f to calculate equations below. step 2: dc max dc max ? | v out | v in(min) + |v out | step 3: v cspn see max current limit vs duty cycle plot in typical performance characteristics to find v cspn at dc max . step 4: r sense1 r sense1 0.58 ? v cspn i out ? (1Cdc ma x ) step 5: r sense2 r sense2 0.05 1.6 ? i out step 6: l l typ = r sense1 ? | v out | 12.5m ? f ? v in(min) v in(min) + |v out | ? ? ? ? (1) l min = r sense1 ? |v out | 40m ? f ? 1? v in(min) v out ? ? ? ? ? ? ? ? 2 ? ? ? ? (2) l max = r sense1 ? |v out | 5m ? f ? v in(min) v in(min) + |v out | ? ? ? ? (3) ? solve equations 1, 2, and 3 for a range of l values. ? the minimum value of the l range is the higher of l typ and l min . the maximum of the l value range is l max . ? l = l 1 = l 2 for coupled inductors. ? l = l 1 || l 2 for uncoupled inductors. step 7: c1 c110f typical ( ) ;v rating > v in +|v out | step 8: c out c out 1 8 ? f 2 ? 0.005 ? v in(max) v in(max) + |v out | ? ? ? ? step 9: c in c in dc max 8 ? l ? f 2 ? 0.005 step 10: c imon c imon 100 ? dc max 0.005 ? f step 11: r fbx r fbx = |v out | +9. 6mv 83.1a step 12: r t r t = 35,880 f C 1; f in khz and r t in k? note: the final values for c out and c in may deviate from the above equations in order to obtain desired load transient performance for a particular application. the c out and c in equations assume zero esr, so increase the capacitance accordingly based on the combined esr. imon ss gnd csp tg csn bg LT8710 8710 f07 mode intv cc rt sync v in en/fbin bias intv ee fbx flag v c isn isp v out ?5v 7a v in 4.5v to 25v r in1 13.3k r in2 10k l1 2.2h r sense1 intv cc r sense2 mn c in2 120f 2.2f c out1 100f 2 r t 118k 1.5m mp ? l2 2.2h ? r fbx 60.4k r1 499 d1 4m r c 11.5k 2.2f c2 0.47f c out2 330f + c ss 220nf c imon 47nf c c 3.3nf c c 100pf + c1 10f 2 c in1 10f 4 lt 8710 8710f
19 for more information www.linear.com/LT8710 8710 f08 gnd v in v in r in1 r in2 (optional) en/fbin 1.7v 1.3v ? + 1.607v v c 51.5k 17.6a at 1.607v ea4 chip enable en/fbn logic active mode setting the output voltage regulation the LT8710 output voltage is set by connecting an external resistor (r fbx ) from the converters output, v out , to the fbx pin. the equations below determines r fbx : r fbx = v out C 1.213v 83.7a ; boost or sepic converter r fbx = | v out | C9.6mv 83.1a ; inverting converter see the electrical characteristics for tolerances on the fbx regulation voltage and current. setting the input voltage regulation or undervoltage lockout by connecting a resistor divider between v in , en/fbin, and gnd, the en/fbin pin provides a mean to regulate the input voltage or to create an undervoltage lockout function. referring to error amplifier ea4 in the block diagram, when en/fbin is lower than the 1.607 v refer - ence, v c is pulled low. for example, if v in is provided by a relatively high impedance source ( e.g. a solar panel) and the current draw pulls v in below a preset limit, v c will be reduced, thus reducing current draw from the input supply and limiting the input voltage drop. note that using this function in forced continuous mode ( mode pin low) can result in current being drawn from the output and forced into the input. if this behavior is not desired then set the mode pin high to prevent reverse current flow. to set the minimum or regulated input voltage use: v in(min? reg) = 1.607v ? 1+ r in1 r in2 ? ? ? ? ? ? +17.6a ? r in1 r in1 = v in(min?reg) ? 1.607v 1.607v r in2 ? ? ? ? +17.6a where r in1 and r in2 are shown in figure 8. for increased accuracy, set r in2 10 k. the resistor r in2 is optional, but it is recommended to be used to increase the accuracy of the input voltage regulation by making the r in1 current much higher than the en/fbin pin current. a pplica t ions i n f or m a t ion figure 8. configurable uvlo this same technique can be used to create an undervoltage lockout if the LT8710 is not in forced continuous mode. when in discontinuous mode, forcing v c low will stop all switching activity. note that this does not reset the soft start function, therefore resumption of switching activity will not be accompanied by a soft-start. note that for very low input impedance supplies, a capaci - tor from en/fbin to ground may be needed to prevent oscillations from the input voltage regulation control loop. at start-up, the minimum voltage on en/fbin must exceed 1.7v ( typical) to begin a soft-start cycle. afterwards, the en/fbin voltage can drop below 1.7 v and the input can be regulated such that the en/fbin voltage is at ~1.607v. so the equation below gives the start-up v in for a desired input regulation voltage: v in(start-up) = 1.7v 1.607v ? v in(min C reg) +0.78a ? r in1 output current monitoring and limiting (r sense2 and isp-isn and imon p ins ) the LT8710 has an output current monitor circuit that can be used to monitor and/or limit the output current. the current monitor circuit works as shown in figure 9. if it is not desirable to monitor and limit the output cur - rent, simply connect the imon pin to ground. note that the current sense resistor connected to the isp and isn pins must still be used, and the value should follow the guidelines in the next couple sections. lt 8710 8710f
20 for more information www.linear.com/LT8710 the current through r sense2 is sensing the current through mp which is turning on and off every clock cycle. since the current through r sense2 is chopped, a filter capacitor connected from the imon pin to ground is needed to filter the voltage at the imon pin before heading to ea3. below is the equation to calculate the required imon pin capacitor : c imon 100a ? dc max 5mv ? f where dc max is the maximum duty cycle of the converters application (v in at the lowest of its input range) and f is the switching frequency. to prevent start-up issues, the imon capacitor should charge up faster than the ss capacitor. it is recommended to size the ss capacitor at least 5 x greater than the imon capacitor. output current monitoring the voltage at the imon pin is a gained up version of the voltage seen across the isp and isn pins. below are the equations relating the r sense2 current to the imon pin voltage. assume the current through r sense2 is steady state and that its time average current is approximately equal to the converters load current: v imon =11.9 ? i rsense2(ave) ? r sense2 +51.8mv ( ) i out i rsense2(ave) = v imon 11.9 C 51.8mv r sense2 output current limiting as shown in figure 9, imon voltages exceeding 1.213v (typical) causes the v c voltage to reduce, thus limiting the inductor current. this voltage on imon corresponds to an average voltage of 50 mv across r sense2 . below is the equation for selecting the r sense2 resistor for limiting the output current at steady state: r sense2 = 50mv i out(limit) if it is not desirable to limit the output current, size r sense2 by setting i out(limit) at least 60% higher than the maximum output current of the converter. this current sense resistor is needed if using the synchronous pfet in the converter. if the pfet is replaced with a schottky, then r sense2 is not needed if output current limiting or monitoring isnt required. note that if the intv ee ldo is in uvlo and ss > 1.8 v ( typi- cal), then the reference voltage at ea3 reduces to 916 mv, and the output current is limited to about half its set point. output overcurrent as shown in figure 9, a comparator monitors the voltage at the imon pin and triggers a reset condition if the imon pin voltage exceeds 1.38 v ( typical). this corresponds to an average voltage of 63.6mv ( typical) across the isp and isn pins: i out(overcurrent) = 63.6mv r sense2 i out(overcurrent) =1.27 ? i out(limit) a pplica t ions i n f or m a t ion figure 9. output current monitor and control 8710 f09 isn to system v out r sense2 mp 51.8mv ? + 1.213v 11.9k 1.38v over current v c ? + ea3 gnd imon c imon isp tg ? + + ? chrg ? + 666.5mv 1ma/v a7 lt 8710 8710f
21 for more information www.linear.com/LT8710 r fbx = v out(float) C 1.213v 83.7a r flag =r fbx ? 1.213v v out(bulk) C v out(float) battery charging and c/10 a useful application for limiting the output current is to charge a battery. when charging a battery such as a 12v lead acid battery, it may be useful to charge to a bulk and float voltage, in which case, the c/10 function of the flag pin can be used. for decreasing charge currents, c/10 is detected when the imon voltage falls below 666.5mv (typical) and corresponds to an average isp C isn voltage of 5mv (typical). for increasing charge currents, c/10 is cleared when imon gets above 727.5mv (typical) which corresponds to an average isp C isn voltage of 10 mv (typical). to set a bulk and float battery voltage, simply connect a resistor from the flag pin to the fbx pin . when the battery charging current is high ( c/10 not detected), the target output voltage is the bulk battery voltage as set by the resistor connected between the flag and fbx pins . once the charging current drops such that c /10 is detected , the target output voltage drops to the float battery voltage as set by the external fbx resistor. see figure 10 below on the flag pin connections and equations for setting the bulk and float battery voltages . note that in order to use the c/10 feature, the mode pin must be high to operate in dcm at light loads. a pplica t ions i n f or m a t ion figure 10. flag pin connections and equations for battery charging 8710 f10 fbx v out from controller v out r fbx lead acid battery 1.213v flag 100s anti-glitch gnd pg c out + 83.7a r flag imon dcm_en chrg ? + 666.5mv capacitor charging when the application is to charge a bank of capacitors such as supercaps, the charging current is set by r sense2 and the flag pin isnt necessarily needed as in the case of charging a battery. temperature dependent output voltage using ntc resistor it may be desirable to regulate the converter s output based on the ambient temperature. the intv cc ldo regulated voltage is 6.3v 1.6% ( see electrical characteristics), and a negative temperature coefficient ( ntc) resistor can be used to sum into the fbx pin to create an output voltage that decreases with temperature. see figure 11 for the necessary connections. the fbx voltages regulates to 1.213v ( typical) for posi - tive output voltages. for an accurate room temperature output voltage, size the resistor divider off the intv cc pin to give 1.213 v such that the current through r2 is ~0 at room temperature. choose r ntc(25) 10 k and use the equations below to calculate r 1 , r fbx , and v out at room temperature and r 2 for a desired v out change over temperature. v out(25) ? 1.213v +83.7a ? r fbx + r r fbx 2 ? 1.213v ? 6.3v ? r 1 r 1 +r ntc(25) ? ? ? ? r ntc =r ntc(25) ? e ? 1 t ? 1 t 25 ( ) ? v out = ?6.3v ? r fbx r 2 ? r 1 ? 1 r 1 +r ntc(t(max)) ? 1 r 1 +r ntc(t(min)) ? ? ? ? ? ? ? 1 r 1 +r ntc(t(max)) ? 1 r 1 +r ntc(t(min)) ? ? ? ? ? ? ? 1 =rr ntc(25) 6.3 ? 1.213v 1.213v 2 = ?6.3v ?v out ? r fbx ? ? r r 1 lt 8710 8710f
22 for more information www.linear.com/LT8710 where: r ntc(25) = resistance of the ntc resistor at 25c b = material- specific constant of ntc resistor. specified at two temperatures such as b 25/85 . if more than two b s are specified, use the most appropriate for the application. t = absolute temperature in kelvin t 25 = room temperature in kelvin (298.15k) to provide a desired load current for any given application, r sense1 must be sized appropriately. the switch current will be at its highest when the input voltage is at the lowest of its range. the equation below calculates r sense1 for a desired output current: r sense1 0.74 ? ? v cspn i out ? 1Cdc max ( ) ? 1C i ripple 2 ? ? ? ? ? ? where = converter efficiency (assume ~90%) v cspn = max current limit voltage (see max current limit vs duty cycle (csp-csn) plot in the typical per formance characteristics) i out = converter load current dc max = switching duty cycle at minimum v in (see power switch duty cycle in appendix) i ripple = peak- to - peak inductor ripple current percent - age at minimum v in (recommended to use 25%) r everse c urrent a pplica tions (mode p in l ow ) when the forced continuous mode is selected ( mode pin low), inductor current is allowed to reverse directions and flow from the v out side to the v in side. this can lead to current sinking from the output and being forced into the input. the reverse current is at a maximum magnitude when v c is lowest. the graph of max current limit vs duty cycle (csp C csn) in the typical performance character- istics section can help to determine the maximum reverse current capability. the imon pin voltage will indicate negative inductor cur - rents. refer to the equation for imon in the pin functions. note that the imon voltage is only accurate if the dynamic voltage across r sense2 stays within C51.8 mv to 500mv. if the valley inductor current goes more negative than C300mv as sensed by r sense2 , the external pfet will turn off, and the inductor current will start going more positive. a pplica t ions i n f or m a t ion switch current limit (r sense1 and csp-csn pins) the external current sense resistor (r sense1 ) sets the maximum peak current though the external nfet switch (mn). the maximum voltage across r sense1 is 50 mv (typical) at very low switch duty cycles, and then slope compensation decreases the current limit as the duty cycle increases ( see the max current limit vs duty cycle (csp- csn) plot in the typical performance characteristics). the equation below gives the switch current limit for a given duty cycle and current sense resistor ( find v cspn at the operating duty cycle in the plot mentioned). i sw(limit) = v cspn r sense1 figure 11. temperature dependent output using an ntc resistor divider 8710 f11 v c gnd 6.3v r1 r ntc fbx intv cc ? + ea1 ? + ea2 14.5k 14.5k 1.213v from system r2 r fbx v out lt 8710 8710f
23 for more information www.linear.com/LT8710 approach, as v in approaches the ovp point, the mode pin approaches the mode fcm threshold (1.224 v typical) and the LT8710 won't allow reverse current flow, preventing v in to go above the ovp point. current sense filtering certain applications may require filtering of the inductor current sense signals due to excessive switching noise that can appear across r sense1 and/ or r sense2 . higher operat - ing voltages , higher values of r sense , and more capacitive mosfets will all contribute additional noise across r sense when mosfets transition. the csp/csn and/or the isp/ isn sense signals can be filtered by adding one of the rc networks shown in figure 14. the filter shown in figure 14a filters out differential noise, whereas the filter in figure 14b filters out the differential and common mode noise at the expense of an additional capacitor and approximately twice the capacitance value . it is recommended to kelvin the ground connection directly to the paddle of the LT8710 if using the filter in figure 14b. the filter network should be placed as close as possible to the LT8710 . resistors greater than 10 should be avoided as this can increase the offset voltages at the csp/csn and isp/isn pins . a pplica t ions i n f or m a t ion figure 12. backup power converter figure 13. input overvoltage protection backup power with the use of reverse current control and input voltage regulation, the LT8710 can be used as a backup power converter as shown in figure 12 below. with the mode pin low to operate in fcm, when the input source is removed, the output can supply current into the input and keep the input regulated for some amount of time. the amount of time depends on the output capacitance and the load current at the input. figure 14a . differential rc filter on csp/ csn and/ or isp/ isn pins once v out drops low enough to put the intv ee ldo in uvlo (v out at ~4.25 v), the pfet will stop switching and the current will stop flowing from v out to v system . for this type of application, it is recommended to use a pfet that is in the linear mode of operation with only 4 v of gate drive. input overvoltage protection whenever the mode pin is low to allow current to flow from output to input, it is strongly recommended to add a couple external components to protect the input from overvoltage as shown in figure 13 below. with either figure 14b. differential and common mode rc filter on csp/ csn and/or isp/isn pins gnd csp tg csn bg LT8710 8710 f12 mode v in en/fbin bias intv ee fbx isp isn v out v system v pwr if v pwr is present 10.5v if v pwr is removed v pwr 12v 5% input power source can be removed ideal diode r in1 49.9k l1 c in2 r in2 10k r sense2 r sense1 l2 ? ? c1 mn mp r fbx cap bank + + c in1 8710 f13 v in mode v in_ovp = v z + 1.224v v in_ovp = 1.224v ? 1 + or 1k v in mode r ovp1 r ovp2 r ovp2 r ovp1 ( ) 8710 f014a r sense1 , r sense2 2.2nf 5.1 5.1 csp or isp LT8710 csn or isn 8710 f014b r sense1 , r sense2 4.7nf 5.1 5.1 csp or isp LT8710 csn or isn 4.7nf lt 8710 8710f
24 for more information www.linear.com/LT8710 the rc product should be kept less than 30 ns, which is simply the total series r (5.1+5.1 in this case) times the equivalent capacitance seen across the sense pins (2.2nf for figure 14a and 2.35nf for figure 14b). switching frequency the LT8710 uses a constant frequency architecture between 100khz and 750 khz. the frequency can be set using the internal oscillator or can be synchronized to an external clock source. selection of the switching frequency is a trade-off between efficiency and component size. low frequency operation increases efficiency by reducing mosfet switching losses, but requires larger inductance and/or capacitance to maintain low output ripple voltage. for high power applications, consider operating at lower frequencies to minimize mosfet heating from switching losses. the switching frequency can be set by placing an appropriate resistor from the rt pin to ground and tying the sync pin low. the frequency can also be synchronized to an external clock source driven into the sync pin. the following sections provide more details. oscillator timing resistor (r t ) the operating frequency of the LT8710 can be set by the internal free-running oscillator. when the sync pin is driven low (< 0.4 v), the frequency of operation is set by a resistor from the rt pin to ground. the oscillator frequency is calculated using the following formula: f = 35,880 r t +1 ( ) where f is in khz and r t is in k. conversely, r t ( in k) can be calculated from the desired frequency (in khz) using: r t = 35,880 f C 1 clock synchronization an external source can set the operating frequency of the LT8710 by providing a digital clock signal into the sync pin (r t resistor still required). the LT8710 will operate at the sync clock frequency. the LT8710 will revert to its internal free-running oscillator clock when the sync pin is driven below 0.4 v for a few free-running clock periods. driving sync high for an extended period of time effec - tively stops the operating clock and prevents latch sr1 from becoming set ( see block diagram). as a result, the switching operation of the LT8710 will stop. the duty cycle of the sync signal must be between 20% and 80% for proper operation. also, the frequency of the sync signal must meet the following two criteria: 1. sync may not toggle outside the frequency range of 100khz to 750 khz unless it is stopped below 0.4v to enable the free-running oscillator. 2. the sync frequency can always be higher than the free-running oscillator frequency ( as set by the r t resistor), f osc , but should not be less than 25% below f osc . after sync begins toggling, it is recommended that switch - ing activity is stopped before the sync pin stops toggling. excess negative inductor current can result when sync stops toggling as the LT8710 transitions from the external sync clock source to the internal free-running oscillator clock. switching activity can be stopped by driving the en/fbin pin low. ldo regulators the LT8710 has two linear regulators to run the bg and tg gate drivers. the intv cc ldo regulates 6.3v (typical) above ground, and the intv ee regulator regulates 6.18v (typical) below the bias pin. intv cc ldo regulator the intv cc ldo is used as the top rail for the bg gate driver for positive output converters. in the case of a nega- tive output converter, the intv cc ldo is used as the top rail for both the bg and tg gate drivers ( bias and intv ee must tie to intv cc and gnd respectively). an external capacitor greater than 2.2 f must be placed from the intv cc pin to ground. the uvlo threshold on intv cc is 4v ( typical), and the LT8710 will be in reset until the ldo comes out of uvlo. the intv cc ldo can run off v in or bias and will intel- ligently select to run off the best for minimizing chip power loss, but at the same time, select the proper input for maintaining intv cc as close to 6.3 v as possible. for a pplica t ions i n f or m a t ion lt 8710 8710f
25 for more information www.linear.com/LT8710 intv ee ldo regulator the bias and intv ee voltages are used for the top and bottom rails of the tg gate driver respectively. an exter- nal capacitor greater than 2.2 f must be placed between the bias and intv ee pins. the uvlo threshold on the regulator ( bias-intv ee ) is 3.42v ( typical) as long as the bias voltage is greater than ~3.36 v. the tg pin can begin switching after the intv ee regulator comes out of uvlo. for positive output converters, bias must be tied to the converter s output voltage. for negative output converters, bias must connect to the intv cc pin and the intv ee pin ties to ground. in this manner, the voltage of the intv ee regulator is driven to the intv cc voltage of 6.3 v and hence the tg gate driver will have levels of 0v and 6.3v. overcurrent protection circuitry typically limits the maxi - mum current draw from the regulator to ~70 ma. if the bias voltage is greater than 20v ( typical), then the current limit of the regulator reduces linearly with input voltage to limit the maximum power in the intv ee pass device. see the intv ee current limit vs bias plot in the typical performance characteristics. the sa me th ermal guidelines from the intv cc ldo regula - tor section apply to the intv ee regulator as well. non-synchronous converter it may be desirable in some applications to replace the external pfet with a schottky diode to make a non- synchronous converter. one example would be a high output voltage application because the voltage drop across the rectifier has a small affect on the efficiency of the converter. in fact, for high output voltage applications, replacing the pfet with a schottky may result in higher efficiency because the LT8710 doesnt have to supply gate drive to the pfet. figure 16 shows the recommended connections for using the LT8710 as a non-synchronous boost converter, however the same concept can be used for any other converter. note that the mode pin must be tied high if using the LT8710 as a non-synchronous converter or else the out - put might not be regulated at light load. also, the tg pin a pplica t ions i n f or m a t ion figure 15. intv cc input voltage selection example, figure 15 is a plot that shows an application where v out /bias is regulated to 12 v and v in starts at 24v and ramps down to 5 v and indicates that intv cc is regulating from v in or bias. overcurrent protection circuitry typically limits the maxi- mum current draw from the ldo to ~125 ma and ~65ma when running from v in and bias respectively. when intv cc is below ~3.5 v during start-up or an overload condition, the typical current limit is reduced to ~25 ma when running from either v in or bias. if the selected input voltage is greater than 20v ( typical), then the current limit of the ldo reduces linearly with input voltage to limit the maximum power in the intv cc pass device. see the intv cc current limit vs v in or bias plot in the typical performance char- acteristics. if the die temperature exceeds 175c (typical), the current limit of the ldo drops to 0. power dissipated in the intv cc ldo should be minimized to improve efficiency and prevent overheating of the LT8710. the current limit reduction with input voltage circuit helps prevent the part from overheating, but these guidelines should be followed. the maximum current drawn through the intv cc ldo occurs under the following conditions: 1. large ( capacitive) mosfets being driven at high frequencies. 2. the converters switch voltage (v out for boost or v in + |v out | for dual inductor converters) is high, thus requiring more charge to turn the mosfet gates on and off. in general, use appropriately sized mosfets and lower the switching frequency for higher voltage applications to keep the intv cc current at a minimum. 8710 f15 bias time selected input voltage bias bias v in v in v in 12v 24v 11.2v 8.5v 8v lt 8710 8710f
26 for more information www.linear.com/LT8710 must be left floating or permanent damage could occur to the tg gate driver. the schematic of figure 16 could be modified if needed. if it is not desirable to monitor and/ or control the output current, r sense2 is not needed and simply tie the isp and isn pins to intv cc . the imon pin can be left floating or can connect to ground. the bias and intv ee pins can tie to ground if the dual input feature of the intv cc ldo is not needed and v in stays above 4.5 v. ? place bypass capacitors for the v in and bias pins (1f or greater) as close as possible to the LT8710. ? place bypass capacitors for the intv cc and intv ee (between bias and intv ee ) pins (2.2 f or greater) as close as possible to the LT8710. ? the load should connect directly to the positive and negative terminals of the output capacitor for best load regulation. boost topology specific layout guidelines ? keep length of loop ( high speed switching path) govern - ing r sense 1 , mn, mp, r sense 2 , c out , and ground return as short as possible to minimize parasitic inductive spikes at the switch node during switching. a pplica t ions i n f or m a t ion figure 17. suggested component placement for boost topology figure 16. simplified schematic of a non-synchronous boost converter layout guidelines for boost, sepic, and dual inductor inverting topologies general layout guidelines ? to optimize thermal performance, solder the exposed pad of the LT8710 to the ground plane with multiple vias around the pad connecting to additional ground planes. ? high speed switching path ( see specific topology below for more information) must be kept as short as possible. ? the fbx, v c , imon, and rt components should be placed as close to the LT8710 as possible, while being far away as practically possible from switching nodes. the ground for these components should be separated from the switch current path. imon gnd csp tg csn bg LT8710 8710 f16 mode intv cc v in en/fbin bias intv ee fbx isp isn v out v in r in1 l1 c in2 r in2 r sense2 r sense1 mn c in1 r fbx c out2 + c out1 sepic topology specific layout guidelines ? keep length of loop ( high speed switching path) govern - ing r sense1 , mn, c1, mp, r sense2 , c out , and ground return as short as possible to minimize parasitic induc- tive spikes at the switch node during switching. mn LT8710 ckt l1 r sense1 r sense2 8705 f17 v in c in v out c out gnd mp lt 8710 8710f
27 for more information www.linear.com/LT8710 a pplica t ions i n f or m a t ion figure 18. suggested component placement for sepic topology figure 19. suggested component placement for dual inductor inverting topology figure 20. suggested routing and connections of csp/csn and isp/isn lines thermal considerations overview the primary components on the board that consume the most power and produce the most heat are the power switches, mn and mp, the power inductor, and the LT8710 ic. it is imperative that a good thermal path be provided for these components to dissipate the heat generated within the packages. this can be accomplished by taking advantage of the thermal pads on the underside of the packages. it is recommended that multiple vias in the printed circuit board be used to conduct heat away from each of these components and into a copper plane with as much area as possible. for the case of the power switches, the copper area of the drain connections shouldnt be too big as to create a large emi surface that can radiate noise around the board. dual inductor inverting topology specific layout guidelines ? keep ground return path from the low side of r sense1 and r sense2 ( to chip) separated from c in s and c out s ground return path ( to chip ) in order to minimize switch- ing noise coupling into the input and output. notice the cuts in the ground return for the low side of r sense1 and r sense2 . ? keep length of loop ( high speed switching path) govern - ing r sense1 , mn, c1, mp, r sense2 , and ground return as short as possible to minimize parasitic inductive spikes at the switch node during switching. current sense resistor layout guidelines ? route the csp/csn and isp/isn lines differentially (close together) from the chip to the current sense resistor as shown in figure 20. ? place the vias that connect the csp/csn and isp/isn lines directly at the terminals of the current sense resis - tor as shown in figure 20. 8705 f18 LT8710 ckt gnd mn mp l1 l2 r sense1 r sense2 v in c1 c in v out c out ? ? 8705 f19 LT8710 ckt gnd c in c out r sense1 r sense2 r1 d1 c2 c1 mp mn v in v out l1 l2 ? ? 8705 f20 r sense1, 2 to current sense pins lt 8710 8710f
28 for more information www.linear.com/LT8710 a pplica t ions i n f or m a t ion power mosfet loss and thermal calculations the LT8710 requires two external power mosfets, an nfet switch for the bg gate driver and a pfet switch for the tg gate driver. important parameters for estimating the power dissipation in the mosfets are: 1. on-resistance (r dson ) 2. gate-to-drain charge (q gd ) 3. pfet body diode forward voltage (v bd ) 4. v ds of the fets during their off-time 5. switch current (i sw ) 6. switching frequency (f) the power loss in each power switch has a dc and ac term. the dc term is when the power switch is fully on, and the ac term is when the power switch is transitioning from on-off or off-on. the following applies for both the nfet and pfet power switches. for a boost application, the average current through the mosfet (i sw ) during its on-time, is the same as the average input current. the magnitude of the drain- to- source voltage, v ds , during its off- time is approximately v out . for a sepic or dual inductor inverting application, the average current through each mosfet (i sw ) during its on-time, is the sum of the average input current and the output current . the | v ds | voltage during the off-time is approximately v in + |v out |. during the non-overlap time of the gate drivers, the peak and valley inductor current is flowing through the body diode of the pfet. below are the equations for the power loss in mn and mp. p p mosfet i 2 r p swi cht ing p mn = = i n 2 ? r ds n + + v ds ? i n ? f ? t rf p rr ? n p mp =i p 2 ? r dso o n +v bd ? i pk + + i vy 1.6 ? ? f ? 140ns+p rr ? p i sw = i out (1? dc) ; i pk =i sw + + i ripple 2 ; i vy =i sw ? i ripple 2 i n = dc ? i sw 2 i ripple 2 12 i p = 1?dc ( ) ? ? ? ? ? ? ? ? + i sw 2 i ripple 2 12 ? ? ? ? ? ? ? p rr ? n v ds ? i rr ? t rr ? f p 2 2 rr ? p v ds ? i rr ? t rr ? f where: f = switching frequency i n = nfet rms current i p = pfet rms current t rf = average of the rise and fall times of the nfets drain voltage i sw = average switch current during its on-time i pk = peak inductor current i vy = valley inductor current i ripple = inductor ripple current dc = switch duty cycle ( see power switch duty cycle section in appendix) v bd = pfet body diode forward voltage at i sw v ds = voltage across the fet when its off. v out for a boost, v in + |v out | for a dual inductor inverting or sepic converter p rr-n = pfet body diode reverse recovery power loss in the nfet p rr-p = pfet body diode reverse recovery power loss in the pfet lt 8710 8710f
29 for more information www.linear.com/LT8710 a pplica t ions i n f or m a t ion i rr = current needed to remove the pfet body diode charge t rr = reverse recover y time of pfet body diode typical values for t rf are 10 ns to 40 ns depending on the mosfet capacitance and drain voltage. in general, the lower the q gd of the mosfet, the faster the rise and fall times of its drain voltage. for best calculations, measure the rise and fall times in the application. pfet body diode reverse recovery power loss is depen - dent on many factors and can be difficult to quantify in an application. in general, this power loss increases with higher v ds and/or higher switching frequency. chip power and thermal calculations power dissipation in the LT8710 chip comes from three primary sources: intv cc and intv ee ldos providing gate drive to the bg and tg pins and additional input quiescent current. the average current through each ldo is deter - mined by the gate charge of the power switches, mn and mp, and the switching frequency. below are the equations for calculating the chip power loss followed by examples. noninverting converter: the intv cc ldo primarily sup- plies voltage for the bg gate driver. the bias and intv ee voltages supply the top and bottom rails of the tg gate driver respectively. the chip q current comes from the higher of v in and bias. below are the chip power equa- tions for a noninverting converter: p vcc = 1.04 ? q mn ? f ? v select p vee1 = q mp ? f ? v bias p vee2 = 3.1ma ? (1 C dc) ? v bias p q = 4ma ? v max where: f = switching frequency dc = switch duty cycle ( see power switch duty cycle section in appendix) q mn = total gate charge of nfet power switch ( mn ) at 6.3v gs q mp = total gate charge of pfet power switch ( mp ) at 6.18v sg v select = intv cc ldo selected input voltage, v in or bias (see ldo regula tors section) v max = higher of v in and bias. inverting converter: due to bias connecting to intv cc and intv ee connecting to ground (see typical applica- tions), all the chip power comes from the v in pin. the intv cc ldo primarily supplies voltage for both the bg and tg gate drivers. the chip q current comes from v in . for consistency, the power thats needed to run the tg gate driver is still labeled as p vee even though the power is coming from intv cc . below are the chip power equations for an inverting converter: p vcc = 1.04 ? q mn ? f ? v in p vee1 = q mp ? f ? v in p vee2 = 3.15ma ? (1 C dc) ? v in p q = 5.5ma ? v in where: f = switching frequency dc = switch duty cycle ( see power switch duty cycle section in appendix) q mn = total gate charge of nfet power switch ( mn) at 6.3v gs q mp = total gate charge of pfet power switch ( mp) at 6.3v sg chip power calculations example table 4 calculates the power dissipation of the LT8710 for a 200khz , 3v C 40v to 5v sepic application when v in is 12v. from p chip in table 4, the die junction temperature can be calculated using the appropriate thermal resistance and worst-case ambient temperature: t j = t a + q ja ? p chip where t j = die junction temperature, t a = ambient tem- perature and ja is the thermal resistance from the silicon junction to the ambient air. the published ja value is 38 c/w for the tssop exposed pad package. in practice, lower ja values are realizable if board layout is performed with appropriate grounding lt 8710 8710f
30 for more information www.linear.com/LT8710 a pplica t ions i n f or m a t ion table 4. power calculations example for a 200khz, 3 v to 40 v to 5 v /5 a sepic ( v in = 12v , mn = fdms86500 l and mp = sud50p 06-15) definition of variables equation design example value dc = switch duty cycle d c ? v out v in + v out d c ? 5v 12v + 5v dc ? 29.4% p vcc = intv cc ldo power driving the bg gate driver q mn = nfet total gate charge at v gs = 6.3v f = switching frequency v select = ldo chooses v in p vcc = 1.04 ? q mn ? f ? v select p vcc = 1.04 ? 73nc ? 200khz ? 12 v p vcc = 182.2mw p vee1 = intv ee ldo power driving the tg gate driver q mp = pfet total gate charge at v sg = 4.25v p vee1 = q mp ? f ? v bias p vee1 = 55nc ? 200khz ? 5v p vee1 = 55mw p vee2 = additional tg gate driver power loss p vee2 = 3.1ma ? (1 C dc) ? v bias p vee2 = 3.1ma ? (1C 0.294) ? 5v p vee2 = 10.9mw p q = chip bias loss v max = higher voltage of v in and bias p q = 4ma ? v max p q = 4ma ? 12v p q = 48mw p chip = 296.1mw (accounting for heat sinking properties of the board) and other considerations listed in the layout guidelines sec- tion. for instance, a ja value of ~22 c/w was consistently achieved when board layout was optimized as per the suggestions in the layout guidelines section. thermal lockout if the die temperature reaches ~175 c, the part will go into reset, so the power switches turn off and the soft-start capacitor will be discharged. the LT8710 will come out of reset when the die temperature drops by ~5c (typical). lt 8710 8710f
31 for more information www.linear.com/LT8710 a pp en d ix power switch duty cycle in order to maintain loop stability and deliver adequate current to the load, the external power nfet ( mn in the block diagram) cannot remain on for 100% of each clock cycle. the maximum allowable duty cycle is given by: dc max = t p Cminofftime ( ) t p ? 100% where t p is the clock period and minofftime ( found in the electrical characteristics) is a maximum of 480ns. conversely, the external power nfet ( mn in the block diagram) cannot remain off for 100% of each clock cycle, and will turn on for a minimum on time ( minontime) when in regulation. this minontime governs the minimum al - lowable duty cycle given by: dc min = (minontime) t p ? 100% where t p is the clock period and minontime ( found in the electrical characteristics) is a maximum of 420ns. the application should be designed such that the operating duty cycle is between dc min and dc max . duty cycle equations for several common topologies are given below where v on_mp is the voltage drop across the external power pfet ( mp) when it is on, and v on_mn is the voltage drop across the external power nfet (mn) when it is on. for the boost topology (see figure 5): dc boost ? v out C v in + v on_mp v out + v on_mp C v on_mn for the sepic or dual inductor inverting topology (see figures 6 and 7): dc sepic_&_invert ? | v out |+ v on_mp v in + | v out |+v on_mp C v on_mn the LT8710 can be used in configurations where the duty cycle is higher than dc max , but it must be operated in the discontinuous conduction mode ( mode pin must be high) so that the effective duty cycle is reduced. inductor selection for high efficiency, choose inductors with high frequency core material, such as ferrite, to reduce core losses. also to improve efficiency, choose inductors with more volume for a given inductance. the inductor should have low dcr ( copper-wire resistance ) to reduce i 2 r losses, and must be able to handle the peak inductor current without saturat- ing. note that in some applications, the current handling requirements of the inductor can be lower, such as in the sepic topology where each inductor carries a fraction of the total switch current. molded chokes or chip inductors do not have enough core area to support peak inductor currents in the 5 a to 15 a range. to minimize radiated noise, use a toroidal or shielded inductor. see table 5 for a list of inductor manufacturers. table 5. inductor manufacturers coilcraft mss1278, xal1010, and msd1278 series www.coilcraft.com cooper bussmann drq 127, dr127, and hcm1104 series www.cooperbussmann.com vishay ihlp series www.vishay.com wrth we-dct series we-cfwi series www .we-online.com minimum inductance although there can be a trade-off with efficiency, it is often desirable to minimize board space by choosing smaller inductors. when choosing an inductor, there are three conditions that limit the minimum inductance; (1) providing adequate load current, and (2) avoidance of subharmonic oscillation, and (3) supplying a minimum ripple current to avoid false tripping of the current comparator. lt 8710 8710f
32 for more information www.linear.com/LT8710 a pp en d ix adequate load current small value inductors result in increased ripple currents and thus, due to the limited peak switch current, decrease the average current that can be provided to the load. in order to provide adequate load current, l should be at least: l boost v in ? dc 2 ? f ? v cspn r sense1 ? v out ? i out v in ? ? ? ? ? ? ? or l dual v in ? dc 2 ? f ? v cspn r sense1 ? |v out | ? i out v in ? ?i out ? ? ? ? ? ? where: l boost = l 1 for boost topologies (see figure 5) l dual = l 1 = l 2 for coupled dual inductor topologies (see figures 6 and 7) l dual = l 1 || l 2 for uncoupled dual inductor topolo- gies (see figures 6 and 7) dc = switch duty cycle (see previous section) v cspn = current limit voltage at the operating switch duty cycle (see max current limit vs duty cycle ( csp C csn) plot in the typical per- formance characteristics) r sense1 = current sense resistor connected across the csp-csn pins (see block diagram) = power conversion efficiency (assume 90%) f = switching frequency i out = maximum output current negative values of l boost or l dual indicate that the out- put load current, i out , exceeds the switch current limit capability of the converter. decrease r sense1 to increase the switch current limit. avoiding subharmonic oscillations the LT8710s internal slope compensation circuit will prevent subharmonic oscillations that can occur when the duty cycle is greater than 50%, provided that the in - ductance exceeds a minimum value. in applications that operate with duty cycles greater than 50%, the inductance must be at least: l min v in ? r sense1 ? (2 ? dc C 1) 40m ? dc ? f ? (1Cdc) where l min = l 1 for boost topologies (see figure 5) l min = l 1 = l 2 for coupled dual inductor topologies (see figures 6 and 7) l min = l 1 || l 2 for uncoupled dual inductor topologies (see figures 6 and 7) maximum inductance excessive inductance can reduce ripple current to levels that are difficult for the current comparator ( a5 in the block diagram) to cleanly discriminate, thus causing duty cycle jitter and/or poor regulation. the maximum inductance can be calculated by: l max v in ? r sense1 ? dc 5m ? f where: l max = l 1 for boost topologies (see figure 5) l max = l 1 = l 2 for coupled dual inductor topologies (see figures 6 and 7) l max = l 1 || l 2 for uncoupled dual inductor topologies (see figures 6 and 7) inductor current rating the inductor(s) must have a rating greater than its (their) peak operating current to prevent inductor saturation, which would result in efficiency losses. the maximum boost topology sepic or inverting topologies lt 8710 8710f
33 for more information www.linear.com/LT8710 a pp en d ix inductor current ( considering start-up and steady-state conditions) is given by: i l_peak = 54mv C 16mv ? dc 2 r sense1 + v in ? t min_prop l where i l_peak = peak inductor current in l 1 for a boost topology, or the sum of the peak inductor currents for dual inductor topologies. t min_prop = 100ns ( propagation delay through the current feedback loop). for wide input voltage range applications, as the input volt - age increases , the max peak inductor current also increases due to the duty cycle decreasing. it is recommended to utilize the output current limiting feature to reduce the max peak inductor current given by the following equation: i l_peak = v ispn r sense2 ? (1Cdc) + v in ? dc 2 ? f ? l where. v ispn = 57 mv max for noninverting converters and 60mv max for inverting converters. note that these equations offer conservative results for the required inductor current ratings. the current ratings could be lower for applications with light loads, and if the ss capacitor is sized appropriately to limit inductor currents at start-up. power mosfet selection the LT8710 requires two external power mosfets, an nfet switch for the bg gate driver and a pfet switch for the tg gate driver. it is important to select mosfets for optimizing efficiency. for choosing an nfet and pfet, the important device parameters are: 1. breakdown voltage (bv dss ) 2. gate threshold voltage (v gsth ) 3. on-resistance (r dson ) 4. total gate charge (q g ) 5. turn-off delay time (t d(off) ) 6. package has exposed paddle the drain-to-source breakdown voltage of the nfet and pfet power mosfets must exceed: ? bv dss > v out for boost converter ? bv dss > v in +|v out | for sepic or dual inductor inverting converter if operating close to the bv dss rating of the mosfet, check the leakage specifications on the mosfet because leakage can decrease the efficiency of the converter. the nfet and pfet gate-to-source drive is approximately 6.3 v and 6.18 v respectively, so logic level mosfets are required. the bg gate driver can begin switching when the intv cc voltage exceeds ~4 v, so ensure the selected nfet is in the linear mode of operation with 4 v of gate- to-source drive to prevent possible damage to the nfet. the tg gate driver can begin switching when the bias- intv ee voltage exceeds ~3.42 v, so it is optimal that the pfet be in the linear mode of operation with 3.42 v of gate-to-source drive. however, the pfet is less likely to get damaged if its not operating in the linear region since the drain-to-source voltage is clamped by its body diode during the nfets off-time. having said that, try to choose a pfet with a low body diode reverse recovery time to minimize stored charge in the pfet. the stored charge in the pfet body diode gets removed when the nfet switch turns on and can lead to efficiency hits especially in ap - plications where the v ds of the pfet ( during off-time) is high. for these applications, it may be beneficial to put a schottky diode across the pfet to reduce the amount of charge in the pfet body diode. in applications where the output voltage is high in magnitude, it may be better to replace the pfet with a schottky diode since the converter may be more efficient with a schottky. power mosfet on-resistance and total gate charge go hand-in-hand and are typically inversely proportional to each other; the lower the on-resistance, the higher total gate charge. choose mosfets with an on-resistance to give a voltage drop to be less than 300 mv at the peak lt 8710 8710f
34 for more information www.linear.com/LT8710 a pp en d ix current. at the same time, choose mosfets with a lower total gate charge to reduce LT8710 power dissipation and mosfet switching losses. the turn-off delay time (t d(off) ) of available nfets is generally smaller than the LT8710s non-overlap time. however, the turn-off time of the available pfets should be looked at before deciding on a pfet for a given applica - tion. the turn-off time must be less than the non-overlap time of the LT8710 or else the nfet and pfet could be on at the same time and damage to external components may occur. if the pfet turn-off delay time as specified in the data sheet is less than the LT8710 non-overlap time, then the pfet is good to use. if the turn-off delay time is longer than the non-overlap time, it doesnt necessarily mean it cant be used. it may be unclear how the pfet manufacturer measures the turn-off delay time, so it is best to measure the pfet turn-off delay time with respect to the pfet gate voltage. finally, both the nfet and pfet power mosfets should be in a package with an exposed paddle for the drain connection to be able to dissipate heat. the on-resistance of mosfets is proportional to temperature, so its more efficient if the mosfets are running cool with the help of the exposed paddle. see table 6 for a list of power mosfet manufacturers. table 6. power mosfet (nfet and pfet) manufacturers fairchild semiconductor www.fairchildsemi.com on-semiconductor www.onsemi.com vishay www.vishay.com diodes inc. www.diodes.com input and output capacitor selection input and output capacitance is necessary to suppress voltage ripple caused by discontinuous current moving in and out of the regulator. a parallel combination of ca - pacitors is typically used to achieve high capacitance and low esr ( equivalent series resistance). tantalum, special polymer, aluminum electrolytic and ceramic capacitors are all available in surface mount packages. capacitors with low esr and high ripple current ratings, such as os-con and poscap are also available. ceramic capacitors should be placed near the regulator input and output to suppress high frequency switching noise. a minimum 1 f ceramic capacitor should also be placed from v in to gnd and from bias to gnd as close to the LT8710 pins as possible. due to their excellent low esr characteristics, ceramic capacitors can significantly reduce ripple voltage and help reduce power loss in the higher esr bulk capacitors. x5r or x7r dielectrics are preferred, as these materials retain their capacitance over wide voltage and temperature ranges. many ceramic ca - pacitors, particularly 0805 or 0603 case sizes, have greatly reduced capacitance at the desired operating voltage. input capacitor, c in the input capacitor, c in , sees the ripple current of the input inductor, l 1 , which eases the capacitance requirements of c in . below is the equation for calculating the capacitance of c in for 0.5% input voltage ripple: c in > dc 8 ? l ? f 2 ? 0.005 where: dc = switch duty cycle ( see power switch duty cycle section) l = l boost or l dual ( see inductor selection section) f = switching frequency the worst-case for the input capacitor ( largest capacitance needed) is when the input voltage is at its lowest because the duty cycle is the highest. keep in mind that the volt - age rating of the input capacitor needs to be greater than the maximum input voltage. this equation calculates the capacitance value during steady-state operation and may need to be adjusted for desired transient response. also, this assumes no esr, so the input capacitance may need to be larger depending on the equivalent esr of the input capacitor(s). output capacitor, c out the output capacitor, c out , in a boost or sepic topology has chopped current flowing through it, whereas the output capacitor in a dual inductor inverting topology sees the lt 8710 8710f
35 for more information www.linear.com/LT8710 a pp en d ix inductor ripple current. below is the equation for calculating the capacitance of c out for 0.5% output voltage ripple: c out > i out ? dc f ? 0.005 ? v out or c out > 1Cdc 8 ? l ? f 2 ? 0.005 where: i out = maximum output current of converter dc = switch duty cycle ( see power switch duty cycle section) l = l boost or l dual ( see inductor selection section ) f = switching frequency the worst- case for the output capacitor ( largest capacitance needed) is when the output regulation voltage is relatively low. this equation calculates the capacitance value during steady-state operation and may need to be adjusted for desired transient response. also, this assumes no esr, so the output capacitance may need to be larger depending on the equivalent esr of the output capacitor(s). see table 7 for a list of ceramic capacitor manufacturers. table 7. ceramic capacitor manufacturers tdk www.tdk.com murata www.murata.com taiyo yuden www.t-yuden.com compensation C adjustment to compensate the feedback loop of the LT8710, a series resistor capacitor network in parallel with an optional single capacitor should be connected from the v c pin to gnd. for most applications, choose a series capacitor in the range of 1 nf to 10 nf with 4.7 nf being a good starting value. the optional parallel capacitor should range in value from 47 pf to 220 pf with 100 pf being a good starting value. the compensation resistor, r c , is usually in the range of 5 k to 50 k. a good technique to compensate a new application is to use a 100 k potentiometer in place of the series resistor r c . with the series and parallel capacitors at 4.7 nf and 100 pf respectively, adjust the potentiometer while observing the transient response and figure 21c. transient response is well damped figure 21a. transient response shows excessive ringing figure 21b. transient response is better the optimum value for r c can be found. the series capaci- tor can be reduced or increased from 4.7 nf to speed up the converter or slow down the converter, respectively. for the circuit in figure 7, a 3.3 nf series cap was used. figures 21 a to 21 c illustrate this process for the circuit of figure 7 with a load current stepped between 2 a and 5.5a with an input voltage of 9 v. figure 21 a shows the transient response with r c equal to 1 k. the phase mar- gin is poor as evidenced by the excessive ringing in the output voltage and inductor current. in figure 21 b, the value of r c is increased to 4 k, which results in a more damped response. figure 21 c shows the results when r c is increased further to 11.5 k. the transient response is nicely damped and the compensation procedure is complete. dual inductor inverting topology boost or sepic t opologies 8705 f21a v out 200mv/div ac-coupled load step 5a/div i l1 + i l2 5a/div r c = 1k 200s/div 8705 f21b v out 200mv/div ac-coupled load step 5a/div i l1 + i l2 5a/div r c = 4k 200s/div 8705 f21c v out 200mv/div ac-coupled load step 5a/div i l1 + i l2 5a/div r c = 11.5k 200s/div lt 8710 8710f
36 for more information www.linear.com/LT8710 a pp en d ix compensation C theory like all other current mode switching regulators, the LT8710 needs to be compensated for stable and efficient operation. tw o feedback loops are used in the LT8710: a fast current loop which does not require compensation, and a slower voltage loop which does. standard bode plot analysis can be used to understand and adjust the voltage feedback loop. as with any feedback loop, identifying the gain and phase contribution of the various elements in the loop is critical. figure 22 shows the key equivalent elements of a boost converter. because of the fast current control loop, the power stage of the ic, inductor and pfet have been re - placed by a c ombination of th e equivalent transconductance amplifier g mp and the current controlled current source (which converts i vin to v in v out i vin ). g mp acts as a current source where the peak input current, i vin , is proportional to the v c voltage and current sense resistor, r sense1 . figure 22. boost converter equivalent model note that the maximum output currents of g mp and g ma are finite. the external current sense resistor, r sense1 , sets the value of: g mp 1 6 ? r sense1 the error amplifier, g ma , is nominally about 200 mhos with a source and sink current of about 12 a and 19a respectively. from figure 22, the dc gain, poles and zeros can be calculated as follows: dc gain: a dc = g ma ? r o ? g mp ? ? v in v out ? r l 2 ? 0.5 ? r 2 r fbx +0.5 ? r 2 output pole: p1= 2 2 ? ? r l ? c out error amp pole: p2 = 1 2 ? ? (r o +r c ) ? c c error amp zero: z1= 1 2 ? ? r c ? c c esr zero: z2 = 1 2 ? ? r esr ? c out rhp zero: z3 = v in 2 ? r l 2 ? ? v out 2 ? l high frequency pole: p3 > f s 3 phase lead zero: z4 = 1 2 ? ? r fbx ? c pl phase lead pole: p4 = 1 2 ? ? r fbx ? 0.5 ? r 2 r fbx +0.5 ? r 2 ? c pl error amp filter pole: p5 = 1 2 ? ? r c ? r o r c +r o ? c f ,c f < c c 10 the current mode zero ( z3) is a right half plane zero which can be an issue in feedback control design, but is manageable with proper external component selection. 8710 f22 c c : compensation capacitor c out : output capacitor c pl : phase lead capacitor c f : high frequency filter capacitor g ma : transconductance amplifier inside ic g mp : power stage transconductance amplifier r c : compensation resistor r l : output resistance defined as v out /i loadmax r o : output resistance of g ma r2, r fbx : feedback resistor divider network r esr : output capacitor esr : converter efficiency (~90% at higher currents) i vin c pl c f ? + ? + 1.213v reference c c r c r o v c r2 r fbx v out r l r2 fbx g ma g mp ? v in v out ? i vin r esr c out r l lt 8710 8710f
37 for more information www.linear.com/LT8710 a pp en d ix using the circuit in figure 24 with a 4 a load as an example, table 9 shows the parameters used to generate the bode plot shown in figure 23. table 9: bode plot parameters parameter value units comment r l 3 application specific c out 88 f application specific r esr 2 m application specific r o 350 k not adjustable c c 3300 pf adjustable c f 100 pf optional/adjustable c pl 0 pf optional/adjustable r c 18 k adjustable r fbx 130 k adjustable r2 14.5 k not adjustable v out 12 v application specific v in 5 v application specific g ma 200 mho not adjustable g mp 167 mho application specific l 1.3 h application specific f osc 400 khz adjustable figure 23. bode plot for example boost converter from figure 23, the phase is C135 when the gain reaches 0db giving a phase margin of 45. the crossover fre- quency is 20 khz, which is about three times lower than the frequency of the rhp zero z3 to achieve adequate phase margin. figure 24. 5v to 12v boost converter imon ss gnd csp tg csn bg LT8710 8710 f24 mode intv cc rt sync v in en/fbin bias intv ee fbx flag v c isp isn v out 12v 6a v in 5v r in1 13.3k l1 1.3h c in2 330f 2.2f c out 22f 4 r in2 10k c in1 22f 4 r t 88.7k 1m r sense2 5m mn 2 mp r sense1 r fbx 130k r c 18k 2.2f c imon 47nf c ss 220nf c c 3.3nf c f 100pf + frequency (hz) gain (db) phase (deg) 140 100 120 80 60 40 20 0 ?20 0 ?90 ?45 ?135 ?180 ?225 ?270 ?315 ?360 10 10k 100k 1m 8710 f23 100 1k phase gain 45 at 20khz lt 8710 8710f
38 for more information www.linear.com/LT8710 typical a pplica t ion 300khz, 4.5v to 25v input to C5v output delivers up to 7a output current efficiency and power loss transient response with 2a to 5.5a to 2a output load step (v in = 12) 8710 ta02c v out 200mv/div ac-coupled load step 5a/div i l1 + i l2 5a/div 200s/div c in1 : 10f, 50v, 1210, x7s c in2 : oscon 120f, 35v, 35svpf120m c out1 : 100f, 6.3v, 1812, x5r c out2 : oscon 330f, 16v, 16seqp330m c1: 10f, 50v, 1210, x7s l1, l2: wrth 2.2h we-cfwi 74485540220 mn: fairchild fdms8333l mp: fairchild fdd4141 r sense1 : 1.5m 2010 r sense2 : 4m 2512 d1: nxp pmeg2010ea imon ss gnd csp tg csn bg LT8710 8710 ta02a mode intv cc rt sync v in en/fbin bias intv ee fbx flag v c isn isp v out ?5v 7a v in 4.5v to 25v 13.3k l1 2.2h c in2 120f 2.2f c out1 100f 2 10k c in1 10f 4 118k 1.5m mn mp r sense1 r sense2 4m l2 2.2h ? ? c1 10f 2 60.4k 11.5k 2.2f intv cc c out2 330f + 47nf 220nf 3.3nf 100pf + 499 d1 0.47f load current (a) 0 efficiency (%) power loss (w) 100 80 90 70 65 50 40 30 20 8 6 7 5 4 3 2 1 0 1 4 5 6 8710 ta02b 7 2 3 v in = 5v v in = 12v lt 8710 8710f
39 for more information www.linear.com/LT8710 typical a pplica t ion 300khz, supercap backup power 8710 ta03c v in 10v/div v out 10v/div v imon 1v/div i l1 + i l2 5a/div 30s/div 8710 ta03d v in 10v/div v out 10v/div v imon 1v/div i l1 + i l2 5a/div 30s/div load current (a) 0 hold-up time (s) 200 150 175 125 100 75 50 25 0 0.5 1.5 2 2.5 8710 ta03b 3 1 v system = 10.5v during hold-up system hold-up time vs system load current supercaps charging when v in is applied supercaps hold-up system at 10.5v for ~83s when v in is removed (i system = 1a) l1, l2: coilcraft 10h msd1278-103ml mn: fairchild fdmc8327l mp: vishay si7611dn r sense1 : 5m 2010 r sense2 : 50m 2512 d in : appropriate schottky diode or ideal diode such as ltc4358, ltc4352, ltc4412, etc. c in1 : 22f, 25v, 1812, x7r c out : 22f, 25v, 1812, x7r c1: 10f, 25v, 1210, x7r c s1-6 : powerstor hb1840-2r5606-r d1: central semi cmdz5245b-ltz imon ss gnd csp tg csn bg LT8710 8710 ta03a mode intv cc rt sync v in en/fbin bias intv ee fbx flag v c isp isn v out 15v v in 12v 5% input power source can be removed d in 49.9k l1, 10h c in2 120f 2.2f 10k d1 15v r t 118k 5m mn mp r sense1 l2 10h ? c1, 10f 165k 14.3k 47nf 220nf 2.2nf 100pf + c in1 22f 2 c out 22f 2 ? r sense2 50m v system = v in when v in is present 10.5v when v in is removed 1k 1.2k 1.2k 1.2k 1.2k 1.2k 1.2k c s1 60f + c s2 60f + c s3 60f + c s4 60f + c s5 60f + c s6 60f + 5.1 5.1 4.7nf 4.7nf 2.2f lt 8710 8710f
40 for more information www.linear.com/LT8710 typical a pplica t ion 400khz, 12v boost converter delivers up to 6a from a 4.5v to 9v input efficiency and power loss transient response with 2a to 5a to 2a output load step (v in = 5v) 8710 ta04c v out 200mv/div ac-coupled load step 2a/div i l1 + i l2 5a/div 200s/div l1: wrth 1.3h we-hci 7443551130 mn: vishay sir802dp mp: vishay si7635dp r sense1 : 1m 2512 r sense2 : 5m 2512 c in1 : 22f, 16v, 1206, x5r c in2 : oscon 330f, 16v, 16seqp330m c out1 : 22f, 25v, 1812, x7r c out2 : oscon 330f, 16v, 16seqp330m imon ss gnd csp tg csn bg LT8710 8710 ta04a mode intv cc rt sync v in en/fbin bias intv ee fbx flag v c isp isn v out 12v 6a v in 4.5 to 9v 13.3k l1 1.3h c out2 330f 2.2f 10k 88.7k 1m mn 2 mp r sense1 130k 18k 2.2f 47nf 220nf 3.3nf 100pf + r sense2 5m c out1 22f 4 c out2 330f + c in1 22f 4 load current (a) 0 efficiency (%) power loss (w) 100 80 90 70 60 50 40 30 20 8 6 7 5 4 3 2 1 0 1 4 5 6 8710 ta04b 2 3 v in = 5v v in = 8v lt 8710 8710f
41 for more information www.linear.com/LT8710 typical a pplica t ion schematic and equations for calculating v out v out cleanly transitions through 0v with a 1v, 100hz sine wave cntl signal (r load = 2) transient response with stepping v cntl from 0v to C1v to 0v with 2 output load 300khz, C5v to 5v output cleanly transitions through 0v with 3a source and sink capability* 8710 ta05c v cntl 1v/div v out 5v/div i l1 + i l2 10a/div 5ms/div 8710 ta05d v cntl 1v/div v out 5v/div i l1 + i l2 10a/div 500s/div l1, l2: wrth 4.4h we-cfwi 74485540440 mn: fairchild fdms8333l mp: fairchild fdd4141 r sense1 : 3m 2010 r sense2 : 10m 2512 * patent pending c in1 : 22f, 25v, 1812, x7r c in2 : oscon 330f, 16v, 16seqp330m c out : 100f, 6.3v, 1812, x5r c1: 10f, 25v, 1210, x7r d1: central semi cmpd1001 imon ss gnd csp tg tg csn bg LT8710 8710 ta05a mode intv cc rt sync v in en/fbin bias intv ee fbx flag v c isp isp isn isn mp tg isp isn v out ?5v to 5v 3a v in v cntl 0v for v out = ?5v ?0.5v for v out = 0v ?1v for v out = 5v = v in 11v to 13v l1 4.4h r sense1 mn c in2 330f 2.2f c out 100f 3 c in1 22f 4 118k 3m ? l2 4.4h ? c1 10f 2 60.4k d1 39.2k 2.2f 6.04k 10nf 47nf 220nf 2.2nf 100pf + r sense2 10m fet bv dss > 2v in ? v out ci vrating > v in ? v out dc = v in ? v out 2v in ? v out fbx ~9.6mv r fbx r cntl v cntl v out ~83.1a 8710 ta05b LT8710 v out = 9.6mv C83.1a ? r fbx ? (v cntl ? 9.6mv) r cntl r fbx lt 8710 8710f
42 for more information www.linear.com/LT8710 300khz, 3a sealed lead acid battery charger with an optional negative temp-co bulk and float battery voltage efficiency vs input voltage bulk and float output voltage with **optional components typical a pplica t ion temperature (c) ?40 output voltage (v) 16.0 15.0 15.5 14.5 14.0 13.5 13.0 12.5 12.0 ?20 40 60 80 8710 ta06b 0 20 bulk float input voltage (v) 5 efficiency (%) 95 90 85 80 75 10 25 30 8710 ta06c 15 20 v out = 12v i out = 3a l1, l2: wrth 3.5h we-cfwi 74485540350 mn: fairchild fdms86500l mp1: vishay sud50p06-15 r sense1 : 1.5m 2010 r sense2 : 16m 2512 c in1 : 10f, 50v, 1210, x7s c out : 22f, 25v, 1812, x7r c1: 10f, 50v, 1210, x7s mp2: vishay si2343cds r ntc : murata ncp18xh103f03rb see the battery charging and c/10 section in applications information for more information on battery charging * mp2 disconnects fbx pin current draw from battery when LT8710 is in shutdown ** place 316k and 100nf as close to the fbx pin as possible. also, connect all grounds of these components to the LT8710 ground imon ss gnd csp tg csn bg LT8710 8710 ta06a mode intv cc rt sync v in en/fbin bias intv ee fbx flag v c isp isn v out 14.7v bulk 13.77v float 3a charge v in 5v to 30v 13.3k l1 3.5h r sense1 mn c in2 100f 2.2f c out 22f 4 10k c in1 10f 4 118k 1.5m ? c1 10f 2 150k *optional mp2 r ntc 10k intv cc 196k 316k 6.19k 2.2f sealed lead acid battery 47nf 220nf 6.8nf 100nf 100pf + l2 3.5h ? mp1 + 2.37k 220nf **optional r sense2 16m 5.1 5.1 4.7nf 4.7nf lt 8710 8710f
43 for more information www.linear.com/LT8710 information furnished by linear technology corporation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no representa- tion that the interconnection of its circuits as described herein will not infringe on existing patent rights. fe20 (cb) tssop rev j 1012 0.09 ? 0.20 (.0035 ? .0079) 0 ? 8 0.25 ref recommended solder pad layout 0.50 ? 0.75 (.020 ? .030) 4.30 ? 4.50* (.169 ? .177) 1 3 4 5 6 7 8 9 10 111214 13 6.40 ? 6.60* (.252 ? .260) 3.86 (.152) 2.74 (.108) 20 1918 17 16 15 1.20 (.047) max 0.05 ? 0.15 (.002 ? .006) 0.65 (.0256) bsc 0.195 ? 0.30 (.0077 ? .0118) typ 2 2.74 (.108) 0.45 0.05 0.65 bsc 4.50 0.10 6.60 0.10 1.05 0.10 3.86 (.152) millimeters (inches) *dimensions do not include mold flash. mold flash shall not exceed 0.150mm (.006") per side note: 1. controlling dimension: millimeters 2. dimensions are in 3. drawing not to scale see note 4 4. recommended minimum pcb metal size for exposed pad attachment 6.40 (.252) bsc fe package 20-lead plastic tssop (4.4mm) (reference ltc dwg # 05-08-1663 rev j) exposed pad variation cb p ackage descrip t ion please refer to http://www .linear.com/designtools/packaging/ for the most recent package drawings. lt 8710 8710f
44 for more information www.linear.com/LT8710 linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7417 (408) 432-1900 fax : (408) 434-0507 www.linear.com/8710 ? linear technology corporation 2014 lt 0114 ? printed in usa r ela t e d p ar t s typical a pplica t ion part number description comments lt3757a boost, flyback, sepic and inverting controller 2.9v v in 40v, 100khz to 1mhz programmable operating frequency, 3mm 3mm dfn-10 and msop-10e packages lt 3758a boost, flyback, sepic and inverting controller 5.5v v in 100v, 100khz to 1mhz programmable operating frequency, 3mm 3mm dfn-10 and msop-10e packages lt 3759 boost, sepic and inverting controller 1.6v v in 42v, 100khz to 1mhz programmable operating frequency, msop-12e package lt 3957a boost, flyback, sepic and inverting converter with 5a, 40v switch 3v v in 40v, 100khz to 1mhz programmable operating frequency, 5mm 6mm qfn package lt 3958 boost, flyback, sepic and inverting converter with 3.3a, 84v switch 5v v in 80v, 100khz to 1mhz programmable operating frequency, 5mm 6mm qfn package lt 3959 boost, sepic and inverting converter with 6a, 40v switch 1.6v v in 40v, 100khz to 1mhz programmable operating frequency, 5mm 6mm qfn package ltc 3786 low i q synchronous step-up controller 4.5v (down to 2.5v after start-up) v in 38v, v out up to 60v, 55a quiescent current, 3mm 3mm qfn-16, msop-16e 200khz, wide input range sepic converter generates a 5v output with up to 5a output current efficiency and power loss l1, l2: wrth 2.9h we-cfwi 74485540290 mn: fairchild fdms86500l mp: vishay sud50p06-15 r sense1 : 1.5m 2010 r sense2 : 6m 2512 c in1 : 10f, 50v, 1210, x7s c out1 : 100f, 6.3v, 1812, x5r c out2 : oscon 330f, 16v, 16seqp330m c1: 10f, 50v, 1210, x7s imon ss gnd csp tg csn bg LT8710 8710 ta07a mode intv cc rt sync v in en/fbin bias intv ee fbx flag v c isp isn v out 5v 5a v in 3v to 40v (operating) 4.5v to 40v (start-up) 4.02k l1 2.9h c in1 10f 6 c in2 220f 2.2f 10k 178k 1.5m mn mp r sense1 45.3k 8.87k 2.2f 47nf 220nf 6.8nf 100pf + r sense2 6m c out1 100f 4 c out2 330f + c1 10f 2 l2 2.9h ? ? load current (a) 0 efficiency (%) power loss (w) 100 80 90 70 60 50 40 30 20 6.00 4.50 5.25 3.75 3.00 2.25 1.50 0.75 0 3 4 5 8710 ta07b 1 2 v in = 5v v in = 12v lt 8710 8710f

▲Up To Search▲

Price & Availability of LT8710

	To Download LT8710 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .