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rf agile transceiver data sheet ad9363 rev. d document feedback information furnished by analog devices is believed to be accurate and reliable. however, no responsibility i s assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. o ne technology way, p.o. box 9106, norwood, ma 02062 - 9106, u.s.a. tel: 781.329.4700 ? 2016 analog devic es, inc. all rights reserved. technical support www.analog.com feature s radio frequency ( rf ) 2 2 transceiver with integrated 12 - bit dacs and adcs w ide bandwidth: 325 mhz to 3.8 ghz supports time division duplex ( tdd ) and frequency division duplex ( fdd ) operation tunable channel bandwidth (bw) : up to 20 mhz rece ivers: 6 differential or 12 single - ended inputs superior receiver sensitivity with a no i se figu re : 3 db receive ( r x) gain control real - time monitor and control signals for manual gain independent automatic gain control (agc) dual transmitters: 4 differential outputs high ly linear broadband transmitter transmit (tx) error vector magnitude (evm) : ? 34 db tx noise: ?15 7 dbm/hz noise floor tx monitor: 66 db dynamic range with 1 db accuracy integrated fractional n synthesizer s 2.4 hz local oscillator (lo) step size cmos/lvds digital interface applications 3g enterprise femtocell base stations 4g femtocell base stations wireless video transmission functional block dia gram f igure 1. general description the ad9363 is a hig h performance, hig hly i ntegrate d rf agile t ransceiver designed for u se i n 3g a nd 4g femtocell app lications . its p rogrammability a n d wideband capability m ake i t i deal f or a broad rang e of transceiver applications. th e devic e combines an rf f ront end wi th a f lexible m ixed - signal b aseband s ection and integrated f requency sy nthesizers, simplifying design - in by providing a configurable digital interface to a processor. the ad9363 operates in the 325 mhz to 3.8 ghz range, covering most li censed and unlicensed bands. c han ne l b andwidths f rom less than 2 00 khz to 2 0 mhz a re supported. t he two i ndependent direct conversion receivers have state - of - the - art noise figure and linearity. each r x subsystem includes independent automatic gain control (agc), dc offset correction, quadrature correction, and digital filtering, thereby eliminating the need for these functions in the digital baseband. the ad9363 also has flexible manual gain modes that can be externally controlled. two high dynamic range adcs per channel digitize the receive d i and q signals and pass them through con figurable decimation filters and 128 - tap finite impulse response ( fir ) filters to produce a 12 - bit output signal at the appropriate sample rat e. the transmitters use a direct conversion architecture that achieves high modulation accuracy with ultralow noise. this transmitter design produces a best - in - class t x evm of ?34 db, all owing significant system margin for the external power amplifier (pa) selection. the on - board t x power monitor can be used as a power detect or, enabling highly accurate tx power measurements. the fully integrated phase - locked loops (pll s) provide low power fractional n frequency synthesis for all receive and transmit channels. channel isolation, demanded by fdd systems, is integrated into the design. all voltage controlled oscillators (vcos) and loop filter components are integrated. the core of the ad9363 can be powered directly from a 1.3 v regulator. the ic is controlled via a standard 4 - wire serial port and four real - time i/o control pins. comprehensive power - down modes are included to minimize power consumption during normal use. the ad9363 i s packaged in a 10 mm 10 mm, 144- ball chip scale package ball grid array (csp_bga). ad9363 rx1b_p, rx1b_n rx1a_p, rx1a_n rx1c_p, rx1c_n rx2b_p, rx2b_n rx2a_p, rx2a_n rx2c_p, rx2c_n tx_mon1 data interface rx lo tx lo tx1a_p, tx1a_n tx1b_p, tx1b_n tx_mon2 tx2a_p, tx2a_n tx2b_p, tx2b_n ctrl auxdacx auxadc ctrl spi dac dac gpo dac adc dac adc adc 10558-001 radio switching notes 1. spi, ctrl, p0_d11/ tx_d5_x t o p0_d0/tx_d0_x, p1_d11/ rx _d5_x t o p1_d0/rx_d0_x , and radio switching c ontain multiple pins. xtaln gpo plls clk_out p0_d 1 1/ tx_d5_x t o p0_d0/ tx_d0_x p1_d 1 1/ rx_d5_x t o p1_d0/ rx_d0_x
ad9363 data sheet rev. d | page 2 of 32 table of contents features .............................................................................................. 1 applications ....................................................................................... 1 functional block diagram .............................................................. 1 general description ......................................................................... 1 revision history ............................................................................... 2 specifications ..................................................................................... 3 current consumption vdd_interface ........................... 8 current consumption vddd1p3_dig and vddax (combination of all 1.3 v supplies) ....................................... 11 absolute maximum ratings ..................................................... 15 reflow profile .............................................................................. 15 thermal resistance .................................................................... 15 esd cautio n ................................................................................ 15 pin configuration and function descriptions ........................... 16 typical performance characteristics ........................................... 20 800 mhz frequency band ......................................................... 20 2.4 gh z frequency band .......................................................... 24 theory of operation ...................................................................... 28 general ......................................................................................... 28 receiver ........................................................................................ 28 transmitter .................................................................................. 28 clock input options .................................................................. 28 synthesizers ................................................................................. 28 digital data interface ................................................................. 29 enable state machine ................................................................. 29 spi interface ................................................................................ 30 control pins ................................................................................ 30 gpo pins (gpo_3 to gpo_0) ................................................. 30 au xiliary converters .................................................................. 30 packaging and ordering information ......................................... 32 outline dimensions ................................................................... 32 ordering guide .......................................................................... 32 revision history 11/2 016r evision d: initial version
data sheet ad9363 rev. d | page 3 of 32 specifications electrical characteristics at vdd_gpo = 3.3 v, vdd_interface = 1.8 v, and all other vdd x pins (vdda1p3_tx_lo, vdda1p3_ tx_vco_ldo, vdda1p3_rx_lo, vdda1p3_rx_vco_ldo, vdda1p3_rx_rf, vdda1p3_rx_tx, vdda1p3_tx_lo_buffer, vdda1p3_tx_synth, vdda1p3_rx_synth, vddd1p3_dig, and vdda1p3_bb) = 1.3 v, t a = 25 c , unless otherwise noted. table 1 . parameter 1 symbol min typ max unit test conditions/comments receivers, general center frequency 325 3800 mhz rx bandwidth 20 mhz gain minimum 0 db maximum 74.5 db at 800 mhz 73.0 db at 2300 mhz (rx1a _x , rx2a _x ) 72.0 db at 2300 mhz (rx1b _x , rx1c _x , rx2b _x , rx2c _x ) gain step 1 db received signal strength indicator rssi range 100 db accuracy 2 db receivers, 800 mhz noise figure nf 2.5 db maximum rx gain third - order input intermod ulation intercept point iip3 ?18 dbm maximum rx gain second - order input intermod ulation intercept point iip2 40 dbm maximum rx gain local oscillator (lo) leakage ?122 dbm at rx front - end input quadrature gain error 0.2 % phase error 0.2 degrees modulation accuracy (evm) ?34 db 19.2 mhz reference clock input return loss s11 ?10 db rx1 x_x to rx2 x_x isolation rx1a _x to rx2a _x , rx1c _x to rx2c _x 70 db rx1b _x to rx2b _x 55 db rx2 _x to rx1 _x isolation rx2a _x to rx1a _x , rx2c _x to rx1c _x 70 db rx2b _x to rx1b _x 55 db receivers, 2.4 ghz noise figure nf 3 db maximum rx gain third - order input intermodulation intercept point iip3 ?14 dbm maximum rx gain second - order input intermod ulation intercept point iip2 45 dbm maximum rx gain local oscillator (lo) leakage ?110 dbm at rx front - end input quadrature gain error 0.2 % phase error 0.2 degrees modulation accuracy (evm) ?34 db 40 mhz reference clock input return loss s11 ?10 db rx1 x_x to rx2 x_x isolation rx1a _x to rx2a _x , rx1c _x to rx2c _x 65 db rx1b _x to rx2b _x 50 db
ad9363 data sheet rev. d | page 4 of 32 parameter 1 symbol min typ max unit test conditions/comments rx2 x_x to rx1 x_x isolation rx2a _x to rx1a _x , rx2c _x to rx1c _x 65 db rx2b _x to rx1b _x 50 db receivers, 3.5 ghz noise figure nf 3.3 db maximum rx gain third - order input intermodulation intercept point iip3 ?15 dbm maximum rx gain second - order input intermod ulation intercept point iip2 44 dbm maximum rx gain local oscillator (lo) leakage ?100 dbm at rx front - end input quadrature gain error 0.2 % phase error 0.2 degrees modulation accuracy (evm) ?34 db 40 mhz reference clock input return loss s11 ?10 db rx1 x_x to rx2 x_x isolation rx1a _x to rx2a _x , rx1c _x to rx2c _x 60 db rx1b _x to rx2b _x 48 db rx2 x_x to rx1 x_x isolation rx2a _x to rx1a _x , rx2c _x to rx1c _x 60 db rx2b _x to rx1b _x 48 db transmitters, general center frequency 325 3800 mhz tx bandwidth 20 mhz power control range 90 db power control resolution 0.25 db transmitters, 800 mhz output return loss s22 ?10 db maximum output power 8 dbm 1 mhz tone into 50 load modulation accuracy (evm) ?34 db 19.2 mhz reference clock third - order output intermodulation intercept point oip3 23 dbm carrier leakage ?50 dbc 0 db attenuation ?32 dbc 40 db attenuation noise floor ?157 dbm/hz 90 mhz offset isolation tx1 x_x to tx2 x_x 50 db tx2 x_x to tx1 x_x 50 db transmitters, 2.4 ghz output return loss s22 ?10 db maximum output power 7.5 dbm 1 mhz tone into 50 load modulation accuracy (evm) ?34 db 40 mhz reference clock third - order output intermod ulation intercept point oip3 19 dbm carrier leakage ?50 dbc 0 db attenuation ?32 dbc 40 db attenuation noise floor ?156 dbm/hz 90 mhz offset isolation tx1 x_x to tx2 x_x 50 db tx2 x_x to tx1 x_x 50 db transmitters, 3.5 ghz output return loss s22 ?10 db maximum output power 7.0 dbm 1 mhz tone into 50 load modulation accuracy (evm) ?34 db 40 mhz reference clock
data sheet ad9363 rev. d | page 5 of 32 parameter 1 symbol min typ max unit test conditions/comments third-order output intermodulation intercept point oip3 18 dbm carrier leakage ?50 dbc 0 db attenuation ?31 dbc 40 db attenuation noise floor ?154 dbm/hz 90 mhz offset isolation tx1 to tx2 50 db tx2 to tx1 50 db 1 when referencing a single function of a multifunction pin in the parameters, only the portion of the pin name that is relevant to the specification is listed. for full pin names of multifunction pins, refer to the pin configuration and function descript ions section. table 2. parameter 1 symbol min typ max unit test conditions/comments tx monitor inputs (tx_mon1, tx_mon2) maximum input level 4 dbm dynamic range 66 db accuracy 1 db lo synthesizer lo frequency step 2.4 hz 2.4 ghz, 40 mhz reference clock integrated phase noise 0.3 rms 100 hz to 100 mhz reference clock (ref_clk) ref_clk is the input to the xtaln pin input frequency range 10 80 mhz external oscillator input signal level 1.3 v p-p ac-coupled external oscillator auxiliary adc resolution 12 bits input voltage minimum 0.05 v maximum vdda1p3_bb ? 0.05 v auxiliary dac resolution 10 bits output voltage minimum 0.5 v maximum vdd_gpo ? 0.3 v output current 10 ma digital specifications (cmos) logic inputs input voltage high vdd_interface 0.8 vdd_interface v input voltage low 0 vdd_interface 0.2 v input current high ?10 +10 a input current low ?10 +10 a logic outputs output voltage high vdd_interface 0.8 vdd_interface v output voltage low 0 vdd_interface 0.2 v digital specifications (lvds) logic inputs input voltage range 825 1575 mv each differential input in the pair input differential voltage threshold ?100 +100 mv
ad9363 data sheet rev. d | page 6 of 32 parameter 1 symbol min typ max unit test conditions/comments receiver differential input impedance 100 logic outputs output voltage high 1375 mv output voltage low 1025 mv output differential voltage 150 mv programmable in 75 mv steps output offset voltage 1200 mv general - purpose outputs output voltage high vdd_gpo 0.8 vdd_gpo v output voltage low 0 vdd_gpo 0.2 v output current 10 ma spi timing vdd_interface = 1.8 v spi_clk period t cp 20 ns pulse width t mp 9 ns spi_en setup to first spi_clk rising edge t sc 1 ns last spi_clk falling edge to spi_enb hold t hc 0 ns spi_di data input setup to spi_clk t s 2 ns data input hold to spi_clk t h 1 ns spi_clk rising edge to output data delay 4 - wire mode t co 3 8 ns 3 - wire mode t co 3 8 ns bus turnaround time, read (master) t hzm t h t co ( max ) ns after baseband processors (bbp) drives the last address bit bus turnaround time, read (slave) t hzs 0 t co ( max ) ns after ad9363 drives the last data bit digital data timing (cmos), vdd_interface = 1.8 v data_clk _x clock period t cp 16.276 ns 61.44 mhz data_clk _x and fb_clk _x pulse width t mp 45% of t cp 55% of t cp ns tx data tx_frame _x , p0_d x , and p1_d x setup to fb_clk _x t stx 1 ns hold to fb_clk _x t htx 0 ns data_clk _x to data bus output delay t ddrx 0 1.5 ns data_clk _x to rx_frame _x delay t dddv 0 1.0 ns pulse width enable t enpw t cp ns txnrx t txnrxpw t cp ns fdd independent enable state machine (ensm) mode txnrx setup to enable t txnrxsu 0 ns tdd ensm mode bus turnaround time tdd mode before rx t rpre 2 t cp ns after rx t rpst 2 t cp ns capacitive load 3 pf capacitive input 3 pf
data sheet ad9363 rev. d | page 7 of 32 parameter 1 symbol min typ max unit test conditions/comments digital data timing (cmos), vdd_interface = 2.5 v data_clk _x clock period t cp 16.276 ns 61.44 mhz data_clk _x and fb_clk _x pulse width t mp 45% of t cp 55% of t cp ns tx data tx_frame _x , p0_ dx , and p1_ dx setup to fb_clk _x t stx 1 ns hold to fb_clk _x t htx 0 ns data_clk _x to data bus output delay t ddrx 0.25 1.25 ns data_clk _x to rx_frame _x delay t dddv 0.25 1.25 ns pulse width enable t enpw t cp ns txnrx t txnrxpw t cp ns fdd independent ensm mode txnrx setup to enable t txnrxsu 0 ns tdd ensm mode bus turnaround time tdd mode before rx t rpre 2 t cp ns after rx t rpst 2 t cp ns capacitive load 3 pf capacitive input 3 pf digital data timing (lvds) data_clk _x clock period t cp 4.069 ns 245.76 mhz data_clk _x and fb_clk _x pulse width t mp 45% of t cp 55% of t cp ns tx data tx_frame _x and tx_ dx setup to fb_clk _x t stx 1 ns hold to fb_clk _x t htx 0 ns data_clk _x to data bus output delay t ddrx 0 1.5 ns data_clk _x to rx_frame _x delay t dddv 0 1.0 ns pulse width enable t enpw t cp ns txnrx t txnrxpw t cp ns fdd independent ensm mode txnrx setup to enable t txnrxsu 0 ns tdd ensm mode bus turnaround time before rx t rpre 2 t cp ns after rx t rpst 2 t cp ns capacitive load 3 pf capacitive input 3 pf supply characteristics 1.3 v main supply 1.267 1.3 1.33 v vdd_interface supply cmos 1.2 2.5 v lvds 1.8 2.5 v vdd_gpo supply 1.3 3.3 3.465 v when unused, must be set to 1.3 v current consumption vddx, sleep mode 180 a sum of all input currents vdd_gpo 50 a no load 1 when referencing a single function of a multifunction pin in the parameters, only the portion of the pin name that is relevan t to the specification is listed. for full pin names of multifunction pins, refer to the pin configuration and function descriptions section.
ad9363 data sheet rev. d | page 8 of 32 current consumption vdd_i nterface table 3 . vdd_interface = 1.2 v parameter min typ max unit test conditions/comments sleep mode 45 a power applied, device disabled one rx channel , one tx channel , double data rate (ddr) lte 1 0 single port 2.9 ma 30.72 mhz data clock, cmos dual port 2.7 ma 15.36 mhz data clock, cmos lte 2 0 dual port 5.2 ma 30.72 mhz data clock, cmos two r x channels , two t x channels , ddr lte 3 dual port 1.3 ma 7.68 mhz data clock, cmos lte 1 0 single port 4.6 ma 61.44 mhz data clock, cmos dual port 5.0 ma 30.72 mhz data clock, cmos lte 2 0 dual port 8.2 ma 61.44 mhz data clock, cmos gsm dual port 0.2 ma 1.08 mhz data clock, cmos wimax 8.75 mhz dual port 3.3 ma 20 mhz data clock, cmos wim ax 10 mhz single port tdd rx 0.5 ma 22.4 mhz data clock, cmos tdd tx 3.6 ma 22.4 mhz data clock, cmos fdd 3.8 ma 44.8 mhz data clock, cmos wimax 20 mhz dual port fdd 6.7 ma 44.8 mhz data clock, cmos
data sheet ad9363 rev. d | page 9 of 32 table 4 . vdd_interface = 1.8 v parameter min typ max unit test conditions/comments sleep mode 84 a power applied, device disabled one rx channel , one tx channel , ddr lte 1 0 single port 4.5 ma 30.72 mhz data clock, cmos dual port 4.1 ma 15.36 mhz data clock, cmos lte 2 0 dual port 8.0 ma 30.72 mhz data clock, cmos two rx channel s, two tx channel s, ddr lte 3 dual port 2.0 ma 7.68 mhz data clock, cmos lte 1 0 single port 8.0 ma 61.44 mhz data clock, cmos dual port 7.5 ma 30.72 mhz data clock, cmos lte 2 0 dual port 14.0 ma 61.44 mhz data clock, cmos gsm dual port 0.3 ma 1.08 mhz data clock, cmos wimax 8.75 mhz dual port 5.0 ma 20 mhz data clock, cmos wimax 10 mhz single port tdd rx 0.7 ma 22.4 mhz data clock, cmos tdd tx 5.6 ma 22.4 mhz data clock, cmos fdd 6.0 ma 44.8 mhz data clock, cmos wimax 20 mhz dual port fdd 10.7 ma 44.8 mhz data clock, cmos
ad9363 data sheet rev. d | page 10 of 32 table 5 . vdd_interface = 2.5 v parameter min typ max unit test conditions/comments sleep mode 150 a power applied, device disabled one rx channel , one tx channel , ddr lte 1 0 single port 6.5 ma 30.72 mhz data clock, cmos dual port 6.0 ma 15.36 mhz data clock, cmos lte 2 0 dual port 11.5 ma 30.72 mhz data clock, cmos two rx channel s, two tx channel s, ddr lte 3 dual port 3.0 ma 7.68 mhz data clock, cmos lte 1 0 single port 11.5 ma 61.44 mhz data clock, cmos dual port 10.0 ma 30.72 mhz data clock, cmos lte 2 0 dual port 20.0 ma 61.44 mhz data clock, cmos gsm dual port 0.5 ma 1.08 mhz data clock, cmos wimax 8.75 mhz dual port 7.3 ma 20 mhz data clock, cmos wimax 10 mhz single port tdd rx 1.3 ma 22.4 mhz data clock, cmos tdd tx 8.0 ma 22.4 mhz data clock, cmos fdd 8.7 ma 44.8 mhz data clock, cmos wimax 20 mhz dual port fdd 15.3 ma 44.8 mhz data clock, cmos
data sheet ad9363 rev. d | page 11 of 32 current consumption vdd x (c ombination of a ll 1.3 v supplies) table 6 . tdd mode, 800 mhz parameter min typ max unit test conditions/comments one rx channel continuous rx 5 mhz bw 180 ma 10 mhz bw 210 ma 20 mhz bw 260 ma two rx channels continuous rx 5 mhz bw 265 ma 10 mhz bw 315 ma 20 mhz bw 405 ma one tx channel continuous tx 5 mhz bw 7 dbm 340 ma ?27 dbm 190 ma 10 mhz bw 7 dbm 360 ma ?27 dbm 220 ma 20 mhz bw 7 dbm 400 ma ?27 dbm 250 ma two tx channels continuous tx 5 mhz bw 7 dbm 550 ma ?27 dbm 260 ma 10 mhz bw 7 dbm 600 ma ?27 dbm 310 ma 20 mhz bw 7 dbm 660 ma ?27 dbm 370 ma
ad9363 data sheet rev. d | page 12 of 32 table 7 . tdd mode, 2.4 ghz parameter min typ max unit test conditions/comments one rx channel continuous rx 5 mhz bw 175 ma 10 mhz bw 200 ma 20 mhz bw 240 ma two rx channels continuous rx 5 mhz bw 260 ma 10 mhz bw 305 ma 20 mhz bw 390 ma one tx channel continuous tx 5 mhz bw 7 dbm 350 ma ?27 dbm 160 ma 10 mhz bw 7 dbm 380 ma ?27 dbm 220 ma 20 mhz bw 7 dbm 410 ma ?27 dbm 260 ma two tx channels continuous tx 5 mhz bw 7 dbm 580 ma ?27 dbm 280 ma 10 mhz bw 7 dbm 635 ma ?27 dbm 330 ma 20 mhz bw 7 dbm 690 ma ?27 dbm 390 ma
data sheet ad9363 rev. d | page 13 of 32 table 8 . fdd mode, 800 mhz parameter min typ max unit test conditions/comments one rx channel , one tx channel continuous rx and tx 5 mhz bw 7 dbm 490 ma ?27 dbm 345 ma 10 mhz bw 7 dbm 540 ma ?27 dbm 395 ma 20 mhz bw 7 dbm 615 ma ?27 dbm 470 ma two rx channels , one tx channel continuous rx and tx 5 mhz bw 7 dbm 555 ma ?27 dbm 410 ma 10 mhz bw 7 dbm 625 ma ?27 dbm 480 ma 20 mhz bw 7 dbm 740 ma ?27 dbm 600 ma one rx channel , two tx channels continuous rx and tx 5 mhz bw 7 dbm 685 ma ?27 dbm 395 ma 10 mhz bw 7 dbm 755 ma ?27 dbm 465 ma 20 mhz bw 7 dbm 850 ma ?27 dbm 570 ma two rx channels , two tx channels 5 mhz bw 7 dbm 790 ma ?27 dbm 495 ma 10 mhz bw 7 dbm 885 ma ?27 dbm 590 ma 20 mhz bw 7 dbm 1020 ma ?27 dbm 730 ma
ad9363 data sheet rev. d | page 14 of 3 2 table 9 . fdd mode , 2.4 ghz parameter min typ max unit test conditions/comments one rx channel , one tx channel continuous rx and tx 5 mhz bw 7 dbm 500 ma ?27 dbm 350 ma 10 mhz bw 7 dbm 540 ma ?27 dbm 390 ma 20 mhz bw 7 dbm 620 ma ?27 dbm 475 ma two rx channels , one tx channel continuous rx and tx 5 mhz bw 7 dbm 590 ma ?27 dbm 435 ma 10 mhz bw 7 dbm 660 ma ?27 dbm 510 ma 20 mhz bw 7 dbm 770 ma ?27 dbm 620 ma one rx channel , two tx channels continuous rx and tx 5 mhz bw 7 dbm 730 ma ?27 dbm 425 ma 10 mhz bw 7 dbm 800 ma ?27 dbm 500 ma 20 mhz bw 7 dbm 900 ma ?27 dbm 600 ma two rx channels , two tx channels continuous rx and tx 5 mhz bw 7 dbm 820 ma ?27 dbm 515 ma 10 mhz bw 7 dbm 900 ma ?27 dbm 595 ma 20 mhz bw 7 dbm 1050 ma ?27 dbm 740 ma
data sheet ad9363 rev. d | page 15 of 32 absolute maximum rat ings table 10. parameter rating vddx to vss x ? 0.3 v to + 1. 4 v vdd_interface to vss x ? 0.3 v to +3.0 v vdd_gpo to vss x ? 0.3 v to +3.9 v logic inputs and outputs to vssx ?0.3 v to vdd_interface + 0.3 v input current to any pin except supplies 10 ma rf inputs (peak power) 2.5 dbm tx monitor input power (peak power) 9 dbm package power dissipation (t jmax ? t a )/ ja maximum junction temperature (t jmax ) 110c temperature range operating ?40c to +85c storage ? 65c to +150c reflow 260c stresses at or above those listed under absolute maximum ratings may cause permanent damage to the product. this is a stress rating only; functional operation of the product at these or any other conditions above those indicated in the operational section of this specification is not implied. operation beyond the maximum operating conditions for extended periods may affect product reliability. reflow profile the ad9363 reflow profile is in accordance with the jedec jesd 20 criteria for pb - free devices. the maximum reflow temperature is 260c. thermal resistance thermal performance is directly linked to printed circuit board ( pcb ) design and operating environment. careful attention to pcb th ermal design is required. ja is the natural convection junction to ambient thermal resistance measured in a one cubic foot sealed enclosure. jc is the junction to case thermal resistance. table 11 . thermal resistance package type airflow velocity (m/sec) ja 2 jc 3 unit bc - 144 -7 1 0 32.3 9.6 c/w 1.0 29.6 n/a 4 c/w 2.5 27.8 n/a 4 c/w 1 per jedec jesd 51- 7, plus jedec jesd 51- 5 2s2p test board. 2 per jedec jesd51 - 2 (still air) or jedec jesd51 - 6 (moving air) . 3 per mil - std - 883, method 1012.1. 4 n/a means not applicable. esd caution
ad9363 data sheet rev. d | page 16 of 32 pin configuration an d function descripti ons figure 2 . pin configuration, top view table 12 . pin function descriptions pin no. type 1 mnemonic description a1, a2 i rx2a_n, rx2a_p receive channel 2 differential a input s . alternatively, each pin can be used as a single - ended input. unused pins must be tied to ground. a3 , m3 , m11 nc d nc do no t connect. do not connect to these pins. a4, a6, a12, b1, b2, b12, c2, c7 to c12, f3, g1, h2, h3, h5, h6, j2, k2, l2, l3, l7 to l12, m4, m6 gnd vssa analog ground. tie these pins directly to the vssd digital ground on the pcb (one ground plane). a5 i tx_mon2 t ransmit channel 2 power monitor input. if this pin is unused, tie it to ground. a7, a8 o tx2a_n, tx2a_p transmit channel 2 differential a output s . unused pins must be tied to 1.3 v. a9, a10 o tx2b_n, tx2b_p transmit channel 2 differential b output s . unused pins must be tied to 1.3 v. a11 p vdda1p1_tx_vco t ransmit vco s upply input. connect to b11. b3 o auxdac1 auxiliary dac 1 output. if using the auxiliary dac, connect a 0.1 f capacitor from this pin to ground. b4 to b7 o gpo_3 to gpo_0 3.3 v capable general - purpose outputs. b8 i vdd_gpo 2.5 v to 3.3 v supply for the auxdac and general - purpose output pins. if the vdd_gpo supply is not used, t his supply must be set to 1.3 v . b9 i vdda1p3_tx_lo transmit local oscillator ( lo ) 1.3 v supply input. b10 i vdda1p3_tx_vco_ldo transmit vco ldo 1.3 v supply input. connect to b9. b11 o tx_vco_ldo_out transmit vco ldo output. connect to a11 and to a 1 f bypass capacitor in series with a 1 resistor to ground. c1, d1 i rx2c_p, rx2c_n receive channel 2 differential c input s . alternatively, use each pin as a single - ended input. unused pins must be tied to ground. c3 o auxdac2 auxiliary dac 2 output. if using the auxiliary dac, connect a 0.1 f capacitor from this pin to ground. c4 i test/enable test input. ground this pin for normal operation. c5, c6, d 5 , d 6 i ctrl_in0 to ctrl_in3 control inputs. use these pins for manual rx gain and tx attenuation control. rx2a_n rx2a_p dnc vssa tx_mon2 vssa tx2a_n tx2a_p tx2b_n tx2b_p vdda1p1_ tx_vco tx_vco_ ldo_out vssa 1 2 3 4 5 6 7 8 9 10 11 12 vssa vssa auxdac1 gpo_3 gpo_2 gpo_1 gpo_0 vdd_gpo vdda1p3_ tx_lo vdda1p3_ rx_synth vdda1p3_ tx_vco_ ldo vssa rx2c_p vssa auxdac2 test/ enable ctrl_in0 ctrl_in1 vssa vssa vssa vssa vssa vssa rx2c_n vdda1p3_ rx_rf vdda1p3_ rx_tx vdda1p3_ rx_lo vdda1p3_ rx_vco_ ldo vdda1p3_ tx_lo_ buffer ctrl_out0 ctrl_in3 ctrl_in2 p0_d9/ tx_d4_p p0_d7/ tx_d3_p p0_d5/ tx_d2_p p0_d3/ tx_d1_p p0_d1/ tx_d0_p p0_d8/ tx_d4_n p0_d6/ tx_d3_n p0_d4/ tx_d2_n p0_d10/ tx_d5_n fb_clk_p fb_clk_n p0_d2/ tx_d1_n vssd rx2b_p ctrl_out1 ctrl_out2 ctrl_out3 p0_d0/ tx_d0_n p0_d11/ tx_d5_p rx2b_n vssa ctrl_out6 ctrl_out5 ctrl_out4 vssd vssd vssd vddd1p3_ dig vssa rx_vco_ ldo_out vdda1p1_ rx_vco ctrl_out7 en_agc enable rx_ frame_p rx_ frame_n tx_ frame_p data_ clk_p vssd rx1b_p vssa vssa vssa txnrx vssa vssd p1_d11/ rx_d5_p tx_ frame_n vssd data_ clk_n vdd_ interface rx1b_n vssa spi_di spi_clk clk_out p1_d10/ rx_d5_n rx1c_p k vssa vdda1p3_ tx_synth vdda1p3_ bb reset spi_en p1_d8/ rx_d4_n p1_d9/ rx_d4_p p1_d6/ rx_d3_n p1_d7/ rx_d3_p p1_d4/ rx_d2_n p1_d5/ rx_d2_p p1_d2/ rx_d1_n p1_d3/ rx_d1_p p1_d0/ rx_d0_n p1_d1/ rx_d0_p vssd rx1c_n vssa vssa vssa rbias auxadc spi_do vssa vssa vssa vssa vssa rx1a_p a b c d e f g h j l m rx1a_n dnc tx1b_n vssa tx_mon1 vssa tx1a_p tx1a_n tx1b_p dnc xtaln analog i/o digital i/o do not connect dc power ground 10558-002
data sheet ad9363 rev. d | page 17 of 32 pin no. type 1 mnemonic description d2 i vdda1p3_rx_rf receiver 1.3 v supply input. connect to d3. d3 i vdda1p3_rx_tx receiver and transmitter 1.3 v supply input. d4, e4 to e6 , f4 to f6, g4 o ctrl_out0 , ctrl_out1 to ctrl_out3 , ctrl_out6 to ctrl_out4, ctrl_out7 control outputs. these pins are multipurpose outputs that have programmable functionality. d7 i/o p0_d 9/ tx_d 4_p digita l data port 0 , data bit 9 / transmit differential input bus , data bit 4 . this is a dual function pin. as p0_d9, it functions as part of the 12- bit bidirectional parallel cmos level data p ort 0. alternatively, as tx_d4_p, it function s as part of the lvds 6 - bit tx differential input bus with internal lvds termination. d8 i/o p0_d7/tx_d3_p digital data port 0 , data bit 7 /transmit differential input bus , data bit 3 . this is a dual function pin. as p0_d7, it functions as part of the 12 - bit bidirectional parallel cmos level data port 0. alternatively, as tx_d3_p , it function s as part of the lvds 6 - bit tx differential input bus with internal lvds termination. d9 i/o p0_d5/tx_d 2 _ p digital data port 0 , data bit 5 /transmit differential input bus , data bit 2 . this is a dual function pin. as p0_d5, it functions as part of the 12 - bit bidirectional parallel cmos level data port 0. alternatively, as tx_d 2 _ p , it function s as part of the lvds 6 - bit tx differential input bus with in ternal lvds termination. d10 i/o p0_d3/tx_d1_p digital data port 0 , data bit 3 /transmit differential input bus , data bit 1 . this is a dual function pin. as p0_d3, it functions as part of the 12- bit bidirectional parallel cmos level data port 0. alternatively, as tx_d1_p, it function s as part of the lvds 6 - bit tx differential input bus with internal lvds termination. d11 i/o p0_d1/tx_d0_p digital data port 0 , data bit 1 /transmit differential input bus , data bit 0 . this is a dual function pin. as p0_d1, it functions as part of the 12 - bit bidirectional parallel cmos lev el data port 0. alternatively, as tx_d0_p , it function s as part of the lvds 6 - bit tx differential input bus with internal lvds t ermination. d12, f7, f9, f11, g12, h7, h10, k12 gnd vssd digital ground. tie these pins directly to the vssa analog ground on the pcb (one ground plane). e1, f1 i rx2b_p, rx2b_n receive channel 2 differential b input s . alternatively, each pin can be used as a single - ended input. unused pins must be tied to ground. e2 i vdda1p3_rx_lo receive lo 1.3 v supply input. e3 i vdda1p3_tx_lo_buffer transmitter lo buffer 1. 3 v supply input . e7 i/o p0_d11/tx_d5_p digital da ta port 0 , data bit 11 /transmit differential input bus , data bit 5 . this is a dual function pin. as p0_d11, it functions as part of the 12 - bit bidirectional parallel cmos level data port 0. alternatively, as tx_d5_p, it function s as part of the lvds 6 - bit tx differential input bus with internal lvds termination. e8 i/o p0_d8/tx_d4_n digital data port 0 , data bit 8 /transmit differential input bus , data bit 4 . this is a dual function pin. as p0_d8, it functions as part of the 12 - bit bidirectional parallel cm os level data port 0. alternatively, as tx_d4_n , it function s as part of the lvds 6 - bit tx differential input bus with internal lvds termination. e9 i/o p0_d6/tx_d3_n digital data port 0 , data bit 6 /transmit differential input bus , data bit 3 . this is a dual function pin. as p0_d6, it functions as part of the 12- bit bidirectional parallel cmos level data port 0. alternatively, as tx_d3_n, it function s as part of the lvds 6 - bit tx differential input bus with internal lvds termination. e10 i/o p0_d4/tx_d2_ n digital data port 0 , data bit 4 /transmit differential input bus , data bit 2 . this is a dual function pin. as p0_d4, it functions as part of the 12 - bit bidirectional parallel cmos level data port 0. alternatively, as tx_d2_n , it function s as part of the l vds 6 - bit tx differential input bus with internal lvds termination. e11 i/o p0_d2/tx_d1_n digital data port 0 , data bit 2 /transmit differential input bus , data bit 1 . this is a dual function pin. as p0_d2, it functions as part of the 12 - bit bidirectional parallel cmos level data port 0. alternatively, as tx_d1_n , it function s as part of the lvds 6 - bit tx differential input bus with internal lvds termination. e12 i/o p0_d0/tx_d0_n digital data port 0 , data bit 0 /transmit differential input bus , data bit 0 . this is a dual function pin. as p0_d0, it functions as part of the 12 - bit bidirectional parallel cmos level data port 0. alternatively, as tx_d0_n , it function s as part of the lvds 6 - bit tx differential input bus with in ternal lvds termination. f2 i vdda1p3_rx_vco_ldo receive vco ldo 1.3 v supply input. connect to e2.
ad9363 data sheet rev. d | page 18 of 32 pin no. type 1 mnemonic description f8 i/ o p0_d10/tx_d5_n digital d ata port 0 , data bit 10 /transmit differential input bus , data bit 5 . this is a dual function pin. as p0_d10, it functions as part of the 12 - bit bidirectional parallel cmos level data port 0. alternatively, as tx_d5_n , it function s as part of the lvds 6 - bit tx differential input bus with internal lvds termination. f10, g10 i fb_clk_p, fb_clk_n feedback clock input s . these pin s receive the fb_clk signal th at clock s in tx data. in cmos mode, use fb_clk_p as the input and tie fb_clk_n to ground . f12 i vddd1p3_dig 1.3 v digital supply input . g2 o rx_vco_ldo_out receive vco ldo output. connect to g3 and to a 1 f bypass capacitor in series with a 1 resistor to ground. g3 i vdda1p1_rx_vco receive v co supply input. connect to g2. g5 i en_agc manual control input for automatic gain control (agc). g6 i enable control input. this pin move s the device through various operational states. g7, g8 o rx_frame_n, rx_frame_p r eceive digital data framing output s . th ese pin s transmit the rx_frame signal that ind icate s whether the rx output data is valid. in cmos mode, use rx_frame_p as the out put and leave rx _frame_n unconnected. g9, h9 i tx_frame_p, tx_frame_n t ransmit digital data framing input s . these pins receive the tx_frame signal that indicates when tx data is valid. in cmos mode, use tx_frame_p as the input and tie tx_frame_n to ground. g11, h11 o data_clk_p, data_clk_n receive data clock output s . these pins transmit the data_clk signal that the bbp uses to clock the rx data. in cmos mode, use data_clk_p as the output and leave data_clk_n unconnected. h1, j1 i rx1b_p, rx1b_n receive channel 1 differential b input s . alternatively, use each pin as a single - ended input. unused pins must be tied to ground. h4 i txnrx enable state machine control signal. this pin control s the data port bus direction. a l ogic low selects the rx direction ; a logic high selects the tx dir ection. h8 i/o p1_d11/rx_d5_p digital data port p1 , data bit 11 /receive differential output bus , data bit 5 . this is a dual function pin. as p1_d11, it functions as part of the 12 - bit bidirectional parallel cmos lev el data port 1. alternatively, as rx_d5_p , it function s as part of the lvds 6 - bit rx differential output bus with internal lvds termination. h12 i vdd_interface 1.2 v to 2.5 v supply for digital i/o pins (1.8 v to 2.5 v in lvds mode). j3 i vdda1p3_rx_synth receiver synthesizer 1 .3 v supply input. j4 i spi_di spi serial data input. j5 i spi_clk spi clock input. j6 o clk_out output clock. this pin can be configured to output either a buffered version of the external input clock (t h e digital controlled crystal oscillator (dcxo) ) or a divided - down version of the internal adc sample clock ( adc_clk ) . j7 i/o p1_d10/rx_d5_n digital data port 1 , data bit 10 /receive differential output bus , data bit 5 . this is a dual function pin. as p1_d10, it functions as part of the 12 - bit bidirecti onal parallel cmos level data port 1. alternatively, as rx_d5_n , it function s as part of the lvds 6 - bit rx differential output bus with internal lvds termination. j8 i/o p1_d9/rx_d4_p digital data port 1 , data bit 9 /receive differential output bus , data bit 4 . this is a dual function pin. as p1_d9, it functions as part of the 12 - bit bidirectional parallel cmos level data port 1. alternatively, as rx_d4_p , it function s as part of the lvds 6 - bit rx differential output bus with internal lvds termination. j9 i/o p1_d7/rx_d3_p digital data port 1 , data bit 7 /receive differential output bus , data bit 3 . this is a dual function pin. as p1_d7, it functions as part of the 12 - bit bidirectional parallel cmos level data port 1. alternatively, as rx_d3_p, it function s as part of the lvds 6 - bit rx differential output bus with internal lvds termination. j10 i/o p1_d5/rx_d2_p digital data port 1 , data bit 5 /receive differential output bus , data bit 2 . this is a dual function pin. as p1_d5, it functions as part of the 12 - bit bidirectional parallel cmos level data port 1. alternatively, as rx_d2_p , it function s as part of the lvds 6 - bit rx differential output bus with internal lvds termination. j11 i/o p1_d3/rx_d1_p digital data port 1 , data bit 3 /receive differential output bus , data bit 1 . this is a dual function pin. as p1_d3, it functions as part of the 12 - bit bidirectional parallel cmos level data port 1. alternatively, as rx_d1_p , it function s as part of the lvds 6 - bit rx differential output bus with internal lvds termination.
data sheet ad9363 rev. d | page 19 of 32 pin no. type 1 mnemonic description j12 i/o p1_d1/rx_d0_p digital data port 1 , data bit 1 /receive differential output bus , data bit 0 . this is a dual function pin. as p1_d1, it functions as part of the 12 - bit bidirectional parallel cmos level data port 1. alternatively, as rx_d0_p , it function s as part of the lvds 6 - bit rx differential output bus with internal lvds termination. k1, l1 i rx1c_p, rx1c_n receive channel 1 differential c input s . alternatively, use each pin a s a single - ended input. tie u nused pins to ground. k3 i vdda1p3_tx_synth transmitter synthesizer 1.3 v supply input . connect this pin to a 1.3 v regulator through a separate trace to a common supply point. k4 i vdda1p3_bb baseband 1.3 v supply input . connect this pin to a 1.3 v regulator through a separate trace to a common supply point. k5 i reset asynchronous reset input . a l ogic low resets the device. k6 i spi_en spi enable. set this pin to logic low to enable the spi bus. k7 i/o p1_d8/rx_d4_n digital data port 1 , data bit 8 /receive differential output bus , data bit 4 . this is a dual function pin. as p1_d8, it functions as part of the 12 - bit bidirectional parallel cmos level data port 1. alternatively, as rx_d4_n , it function s as part of the lvds 6 - bit rx differential output bus with internal lvds termination. k8 i/o p1_d6/rx_d3_n digital data port 1 , data bit 6 /receive differential output bus , data bit 3 . this is a dual function pin. as p1_d6, it functions as part of the 12 - bit bidirectional parallel cmos level data port 1. alternatively, as rx_d3_n , it function s as part of the lvds 6 - bit rx differential output bus with internal lvds termination. k9 i/o p1_d4/rx_d2_n digital data port 1 , data bit 4 /receive differential output bus , data bit 2 . this is a dual function pin. as p1_d4, it functions as part of the 12 - b it bidirectional parallel cmos level data port 1. alternatively, as rx_d2_n , it function s as part of the lvds 6 - bit rx differential output bus with internal lvds termination. k10 i/o p1_d2/rx_d1_n digital data port 1 , data bit 2 /receive differential output bus , data bit 1 . this is a dual function pin. as p1_d2, it functions as part of the 12 - bit bidirectional parallel cmos level data port 1. alternatively, as rx_d1_n , it function s as part of the lvds 6 - bit rx differential output bus with internal lvds termination. k11 i/o p1_d0/rx_d0_n digital data port 1 , data bit 0 /receive differential output bus , data bit 0 . this is a dual function pin. as p1_d0, it functions as part of the 12 - bit bidirectional parallel cmos level data port 1. alternatively, as rx_ d0_n , it function s as part of the lvds 6 - bit rx differential output bus with internal lvds termination. l4 i rbias bias input reference. connect this pin through a 14.3 k (1% tolerance) resistor to ground. l5 i auxadc auxiliary adc input. if this pin is unused, tie it to ground. l6 o spi_do spi serial data output in 4 - wire mode, high - z in 3- wire mode. m1, m2 i rx1a_p, rx1a_n receive channel 1 differential a input s . alternatively, use each pin a s a single - ended input. tie u nused pins to ground. m5 i tx_mon1 t ransmit channel 1 power monitor input. if this pin is unused, tie it to ground. m7, m8 o tx1a_p, tx1a_n transmit channel 1 differential a output s . tie u nused pins to 1.3 v. m9, m10 o tx1b_p, tx1b_n transmit channel 1 differential b output s . tie u nused pins to 1.3 v. m12 i xtaln reference frequency connection. connect the external clock source to xtaln. 1 i is input, nc is not connected , gnd is ground, o is output, p is power, and i/o is input/output .
ad9363 data sheet rev. d | page 20 of 32 typical performance characteristics atten is the attenuation setting. f lo_rx and f lo_tx are the r eceive and transmit local oscillator frequencies , respectively. 800 mhz frequency ba nd figure 3. rx noise figure vs. rf frequency figure 4. rssi error vs. rx input power, lte 10 mhz modulation (referenced to ? 50 dbm input power at 800 mhz) figure 5. rx evm vs. interferer power level , lte 10 mhz signal of interest with p in = ? 82 dbm, 5 mh z orthogonal frequency division multiplexing (ofdm) blocker at 7.5 mhz offset figure 6. rx evm vs. interferer power level , lte 10 mhz signal of interest with p in = ?90 dbm, 5 mhz ofdm blocker at 17.5 mhz offset figure 7. rx noise figure vs. interferer power level , enhanced data rates for gsm evolution ( edge ) signal of interest with p in = ?90 dbm, continuous wave ( cw ) blocke r at 3 mhz offset , gain index = 64 figure 8. rx gain vs. rx lo frequency, gain index = 76 (maximum setting) 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 700 750 800 850 900 rx noise figure (db) rf frequenc y (mhz) ?40c +25c +85c 10558-003 ?3 ?2 ?1 0 1 2 3 4 5 ?100 ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 rssi error (db) rx input power (dbm) ?40c +25c +85c 10558-004 ?30 ?25 ?20 ?15 ?10 ?5 0 ? 72 ? 68 ? 64 ? 60 ? 56 ? 52 ? 48 ? 44 ? 40 ? 36 ? 32 rx evm (db) interferer power leve l (dbm) ?40c +25c +85c 10558-006 ?16 ?12 ?8 ?4 0 ?56 ?54 ?52 ?50 ?48 ?46 ?44 ?42 ?40 ?38 ?36 rx evm (db) interferer power leve l (dbm) ?40c +25c +85c 10558-007 0 2 4 6 8 10 12 14 ?47 ?43 ?39 ?35 ?31 ?27 ?23 rx noise figure (db) interferer power leve l (dbm) ?40c +25c +85c 10558-008 66 68 70 72 74 76 78 80 700 750 800 850 900 rx gain (db) rx lo frequenc y (mhz) ?40c +25c +85c 10558-009
data sheet ad9363 rev. d | page 21 of 32 figure 9 . third - order input intercept point (iip3) vs. rx gain index, f1 = 1.45 mhz, f2 = 2.89 mhz, gsm mode figure 10 . second - order input intercept point (iip2) vs. rx gain index, f1 = 2.00 mhz, f2 = 2.01 mhz, gsm mode figure 11 . rx lo leakage vs. rx lo frequency figure 12 . rx emission at l na input vs. frequency , dc to 12 ghz, f lo_rx = 800 mhz, lte 10 mhz, f lo_tx = 860 mhz figure 13 . tx output power vs. tx lo frequency, attenuation setting = 0 db, single - tone output figure 14 . tx power control step linearity err or vs. attenuation setting ?25 ?20 ?15 ?10 ?5 0 5 10 15 20 20 28 36 44 52 60 68 76 iip3 (dbm) ?40c +25c +85c rx gain index 10558-010 0 10 20 30 40 50 60 70 80 90 100 20 28 36 44 52 60 68 76 iip2 (dbm) rx gain index ?40c +25c +85c 10558-0 1 1 ?130 ?125 ?120 ? 1 15 ? 1 10 ?105 ?100 700 750 800 850 900 rx lo leakage (dbm) rx lo frequenc y (mhz) ?40c +25c +85c 10558-012 ?120 ?100 ?80 ?60 ?40 ?20 0 0 2000 4000 6000 8000 10000 12000 rx emission a t ln a input (dbm/750khz) frequenc y (mhz) 10558-013 6.0 6.5 7.0 7.5 8.0 8.5 9.0 9.5 10.0 700 750 800 850 900 tx output power (dbm) tx lo frequenc y (mhz) ?40c +25c +85c 10558-014 ?0.5 ?0.4 ?0.3 ?0.2 ?0.1 0 0.1 0.2 0.3 0.4 0.5 0 10 20 30 40 50 tx power contro l ste p linearit y error (db) a ttenu a tion setting (db) ?40c +25c +85c 10558-015
ad9363 data sheet rev. d | page 22 of 32 figure 15 . tx output power vs . frequency o ffset from carrier frequency, f lo_tx = 800 mhz, lte 10 mhz downlink (digital attenuation variations shown) figure 16 . integrated tx lo phase noise vs. frequency, 19.2 mhz ref_clk figure 17 . tx c arrier rejection v s. frequency figure 18 . tx second - order harmonic disto r tion (hd2) vs. frequency figure 19 . tx third - order harmonic disto r tion (hd3) vs. frequency figure 20 . tx third - order output intercept point (oip3) vs. tx attenuation setting ?100 ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 0 ?15 ?10 ?5 0 5 10 15 tx output power (dbm/100khz) frequenc y offset from carrier frequenc y (mhz) att 0db att 3db att 6db 10558-016 0 0.1 0.2 0.3 0.4 0.5 700 750 800 850 900 integr a ted tx lo phase noise (rms) frequenc y (mhz) ?40c +25c +85c 10558-019 ?70 ?65 ?60 ?55 ?50 ?45 ?40 ?35 ?30 700 750 800 850 900 tx carrier rejection (dbc) frequenc y (mhz) att 0, ?40c att 25, ?40c att 50, ?40c att 0, +25c att 25, +25c att 50, +25c att 0, +85c att 25, +85c att 50, +85c 10558-020 ?80 ?75 ?70 ?65 ?60 ?55 ?50 700 750 800 850 900 tx second- order harmonic dis t ortion (dbc) frequenc y (mhz) att 0, ?40c att 25, ?40c att 50, ?40c att 0, +25c att 25, +25c att 50, +25c att 0, +85c att 25, +85c att 50, +85c 10558-021 ?60 ?55 ?50 ?45 ?40 ?35 ?30 ?25 ?20 700 750 800 850 900 tx third-order harmonic dis t ortion (dbc) frequenc y (mhz) att 0, ?40c att 25, ?40c att 50, ?40c att 0, +25c att 25, +25c att 50, +25c att 0, +85c att 25, +85c att 50, +85c 10558-022 0 5 10 15 20 25 30 0 4 8 12 16 20 tx oip3 (dbm) tx a ttenu a tion setting (db) ?40c +25c +85c 10558-023
data sheet ad9363 rev. d | page 23 of 32 figure 21 . tx s ignal - to - noise ratio (snr) vs. tx attenuation setting, lte 10 mhz signal of interest with noise measured at 90 mhz offset figure 22 . tx single sideban d rejection vs. frequency, 1.5375 mhz offset 140 145 150 155 160 165 170 0 3 6 9 12 15 tx snr (db/hz) tx a ttenu a tion setting (db) ?40c +25c +85c 10558-024 ?70 ?65 ?60 ?55 ?50 ?45 ?40 ?35 ?30 700 750 800 850 900 tx single sideband rejection (dbc) frequenc y (mhz) att 0, ?40c att 25, ?40c att 50, ?40c att 0, +25c att 25, +25c att 50, +25c att 0, +85c att 25, +85c att 50, +85c 10558-026
ad9363 data sheet rev. d | page 24 of 32 2.4 ghz frequency band figure 23 . rx noise figure vs. rf frequency figure 24 . rssi error vs. input power (referenced to ? 50 dbm input power at 2. 4 ghz) figure 25 . rx evm vs. interferer power level , lte 20 mhz signal of interest with p in = ?75 dbm, lte 20 mhz blocker at 20 mhz offset figure 26 . rx evm vs. interferer power level , lte 20 mhz signal of interest with p in = ?75 dbm, lte 20 mhz blocker at 40 mhz offset figure 27 . rx gain vs. rx lo frequency, gain index = 76 (maximum setting) figure 28 . third - order input intercept point (iip3) vs. rx gain index, f1 = 30 mhz, f2 = 61 mhz 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 1800 1900 2000 2100 2200 2300 2400 2500 2600 2700 rx noise figure (db) rf frequenc y (mhz) ?40c +25c +85c 10558-027 ?3 ?2 ?1 0 1 2 3 4 5 ? 100 ? 90 ? 80 ? 70 ? 60 ? 50 ? 40 ? 30 ? 20 ? 10 rssi error (db) input power (dbm) ?40c +25c +85c 10558-028 ?30 ?25 ?20 ?15 ?10 ?5 0 ?72 ?68 ?64 ?60 ?56 ?52 ?48 ?44 ?40 ?36 ?32 ?28 rx evm (db) interferer power leve l (dbm) ?40c +25c +85c 10558-042 ?30 ?25 ?20 ?15 ?10 ?5 0 ?60 ?55 ?50 ?45 ?40 ?35 ?30 ?25 ?20 rx evm (db) interferer power leve l (dbm) ?40c +25c +85c 10558-043 66 68 70 72 74 76 78 80 1800 1900 2000 2100 2200 2300 2400 2500 2600 2700 rx gain (db) rx lo frequenc y (mhz) ?40c +25c +85c 10558-029 ?25 ?20 ?15 ?10 ?5 0 5 10 15 20 20 28 36 44 52 60 68 76 iip3 (dbm) rx gain index ?40c +25c +85c 10558-030
data sheet ad9363 rev. d | page 25 of 32 figure 29 . second - order input intercept point (iip2) vs. rx gain index, f1 = 60 mhz, f2 = 61 mhz figure 30 . rx local oscillator (lo) leakage vs. rx lo frequency figure 31 . rx emission at lna input vs. frequency , dc to 12 ghz, f lo_rx = 2.4 ghz, lte 20 mhz, f lo_tx = 2.46 ghz figure 32 . tx output power vs. tx lo frequency, attenuation setting = 0 d b, single - tone output figur e 33 . tx power control step linearity error vs. attenuation setting figure 34 . t x output power vs . frequency offset from carrier frequency, f lo_tx = 2.3 ghz, lte 20 mhz downlink (digital attenuation variations shown) 20 30 40 50 60 70 80 20 28 36 44 52 60 68 76 iip2 (dbm) rx gain index ?40c +25c +85c 10558-031 ?130 ?125 ?120 ?1 15 ?1 10 ?105 ?100 1800 1900 2000 2100 2200 2300 2400 2500 2600 2700 rx lo leakage (dbm) rx lo frequenc y (mhz) ?40c +25c +85c 10558-032 ?120 ?100 ?80 ?60 ?40 ?20 0 0 2000 4000 6000 8000 10000 12000 rx emission at lna input (dbm/750khz) frequenc y (mhz) 10558-044 6.0 6.5 7.0 7.5 8.0 8.5 9.0 9.5 10.0 1800 1900 2000 2100 2200 2300 2400 2500 2600 2700 tx output power (dbm) tx lo frequenc y (mhz) ?40c +25c +85c 10558-033 ?0.5 ?0.4 ?0.3 ?0.2 ?0.1 0 0.1 0.2 0.3 0.4 0.5 0 10 20 30 40 50 tx power contro l ste p linearit y error (db) a ttenu a tion setting (db) ?40c +25c +85c 10558-034 ?120 ?100 ?80 ?60 ?40 ?20 0 ?25 ?20 ?15 ?10 ?5 0 5 10 15 20 25 tx output power (dbm/100khz) frequenc y offset from carrier frequenc y (mhz) att 0db att 3db att6db 10558-045
ad9363 data sheet rev. d | page 26 of 32 figure 35 . integrated tx lo phase noise vs. frequency, 40 mhz ref_clk figure 36 . tx carrier rejection vs . frequency figure 37 . tx second - order harmonic disto r tion (hd2) vs. frequency figure 38 . tx third - order harmonic disto r tion (hd3) vs. frequency 0 0.1 0.2 0.3 0.4 0.5 1800 1900 2000 2100 2200 2300 2400 2500 2600 2700 integr a ted tx lo phase noise (rms) frequenc y (mhz) ?40c +25c +85c 10558-035 ?70 ?65 ?60 ?55 ?50 ?45 ?40 ?35 ?30 1800 1900 2000 2100 2200 2300 2400 2500 2600 2700 tx carrier rejection (dbc) frequenc y (mhz) att 0, ?40c att 25, ?40c att 50, ?40c att 0, +25c att 25, +25c att 50, +25c att 0, +85c att 25, +85c att 50, +85c 10558-036 ?80 ?75 ?70 ?65 ?60 ?55 ?50 1800 1900 2000 2100 2200 2300 2400 2500 2600 2700 tx second-order harmonic dis t ortion (dbc) frequenc y (mhz) att 0, ?40c att 25, ?40c att 50, ?40c att 0, +25c att 25, +25c att 50, +25c att 0, +85c att 25, +85c att 50, +85c 10558-037 ?60 ?55 ?50 ?45 ?40 ?35 ?30 ?25 ?20 1800 1900 2000 2100 2200 2300 2400 2500 2600 2700 tx third-order harmonic dis t ortion (dbc) frequenc y (mhz) att 0, ?40c att 25, ?40c att 50, ?40c att 0, +25c att 25, +25c att 50, +25c att 0, +85c att 25, +85c att 50, +85c 10558-038
data sheet ad9363 rev. d | page 27 of 32 figure 39 . tx third - order output intercept point (oip3) vs. tx attenuation setting figure 40 . tx signal - to - noise ratio (snr) vs. tx attenuation setting, lte 20 mhz signal of interest with noise measured at 90 mhz offset figure 41 . tx single sid eband rejection vs. frequency, 3.075 mhz offset 0 5 10 15 20 25 30 0 4 8 12 16 20 tx oip3 (dbm) tx a ttenu a tion setting (db) ?40c +25c +85c 10558-039 140 142 144 146 148 150 152 154 156 158 160 0 3 6 9 12 15 tx snr (db/hz) tx a ttenu a tion setting (db) ?40c +25c +85c 10558-040 ?70 ?65 ?60 ?55 ?50 ?45 ?40 ?35 ?30 1800 1900 2000 2100 2200 2300 2400 2500 2600 2700 tx single sideband rejection (dbc) frequenc y (mhz) att 0, ?40c att 25, ?40c att 50, ?40c att 0, +25c att 25, +25c att 50, +25c att 0, +85c att 25, +85c att 50, +85c 10558-041
ad9363 data sheet rev. d | page 28 of 32 theory of operation general the ad9363 is a highly integrated radio frequency (rf) transceiver capable of being configured for a wide range of applications. the device integrates all rf, mixed - signal, and digital blocks necessary to provide all transceiver functions in a single device. programmability allows this broadband transceiver to be adapted for use with multiple communication standards, including fdd and t dd systems. this programmability also allows the device to interface to various bbps using a single 12 - bit parallel data port, dual 12 - bit parallel data ports, or a 12 - bit low voltage differential signaling (lvds) interface. the ad9363 also provides self calibratio n and agc systems to maintain a high performance level under varying temperatures and input signal conditions. in addi tion, the device includes several test modes that allow system designers to insert test tones and create internal loopback modes to debug their designs during prototyping and optimize their radio configuration for a specific application. receiver the receiver section contains all blocks necessary to receive rf signals and convert them to digital data that is usable by a bbp. two independentl y controlled channels can receive signals from different sources, allowing the device to be used in multi ple input, multi ple output (mimo) systems while sharing a common frequency synthesizer. each channel has three inputs that can be multiplexed to the si gnal chain, making the ad9363 suitable for use in diversity systems with multiple antenna inputs. the receiver is a direct conversion system that conta ins a low noise amplifier (lna) followed by matched in - phase (i) and quadrature (q) amplifiers, mixers, and band shaping filters that downconvert received signals to baseband for digitization. external lnas can also be interfaced to the device, allowing designers the flexibility to customize the re ceiver front end for their specific application. gain control is achieved by following a preprogrammed gain index map that distributes gain among the blocks for optim al performance at each lev el. this gain control ca n be achieved by enabling the internal a gc in either fast or slow mode or by using manual gain control, allowing the bbp to make the gain adjustments as needed. additionally, each channel contains independent rssi measurement capability, dc offset tracking, and all circuitry necessary for self c alibration . the receivers include 12 - bit , sigma - delta ( - ) adcs and adjust - able sample rates that produce data streams from the received signals. the digitized signals can be conditioned further by a series of decimation filters and a fully programmable 128 - tap fir filter with additional decimation settings. the sample rate of ea ch digital filter block can also be adjusted by changing the decimation factors to produce the desired output data rate. transmitter the transmitter section consists of two identical and indepen - dently controlled channels that provide all digital processin g, mixed - signal, and rf blocks necessary to implement a direct conversion system while sharing a common frequency synthe - sizer. the digital data received from the bbp passes through a fully programmable 128 - tap fir filter with interpolation options. the fi r output is sent to a series of interpolation filters that provide additional filtering and data rate interpolation prior to reaching the dac. each 12 - bit dac has an adjustable sampling rate. both the i and q channels are fed to the rf block for upconversi on. after being converted to baseband analog signals, the i and q signals are filtered to remove sampling artifacts and provide band shaping, and then they are passed to the upconversion mixers. at this point, the i and q signals are recombined and modulat ed on the carrier frequency for transmission to the output stage. the output stage provides attenuation control that provides a range of output levels while keeping the output impedance at 50 ?. a wide range of attenuation adjustment with fine granularity is included to help designers optimize snr . self calibration circuitry is included in the transmit channel to provide internal adjustment capability . the transmitter also provides a tx monitor block that receives the transmitter output and routes it back through an unused receiver channel to the bbp for signal monitoring. the tx monitor blocks are available only in tdd mode operation while the receiver is idle . clock input options the ad9363 uses a reference clock provided by an external oscillator or clock distribution devic e (such as the ad9548 ) connected to the xtaln pin . the frequency of this reference clock can vary from 10 mhz to 80 mhz. this reference clock s uppl ies the synthesizer blocks that generate all data clocks, sample clocks, and local oscillators inside the device. synthesizers rf pll s th e ad9363 contains two identical synthesizers to generate the required lo signals for the rf signal paths one for the receiver and one for the transmitter. pll synthesizers are fractional n designs that incorporate completely integrated vcos and loop filters. in td d mode , the synthesizers turn on and off as appropri - ate for the rx and tx frames. in fdd mode, the tx pll and the rx pll can be activated at the same time. these plls require no external components.
data sheet ad9363 rev. d | page 29 of 32 bb pll the ad9363 also contains a baseband pll (bb pll) synthesizer that generate s all baseband related clock signals. these signals include the adc and dac sampling clocks, the data_clk signal (see the digital data interface section), and all data framing signals. th e bb pll is programmed from 700 mhz to 1400 mhz based on the data rate and sample rate requirements of t he system. digital data interfa ce the ad9363 data interface uses parallel data ports (p0 and p1) to transfer data between the device and the bbp. the data ports can be configured in either single - ended cmos format or dif - ferential lvds format. both formats can be configured in multiple arrangements to match system requirements for data ordering and data port connections. these arrangements include single port data bus, dual port data bus, single da ta rate, double data rate, and various combinations of data ordering to transmit data from different channels across the bus at appropriate times. bus transfers are controlled using simple hardware handshake signaling. the two por ts can be operated in eith er bi directional (tdd) mode or in full duplex (fdd) mode , where half the bits are used for transmitting data and half are used for receiving data. the interface can also be configured to use only one of the data ports for applications that do not require h igh data rates and require fewer interface pins. data_clk signal the ad9363 outputs the data_clk signal that the bbp uses to sample receiver data. the signal is synchronized with the receiver data such that data transitions occur out of phase with data_clk. the data_clk can be set to a rate that provides single data rate (sdr) ti ming, where data is sampled on each rising clock edge, or it can be set to provide double data rate (ddr) timing, where data is captured on both rising and falling clock edges. sdr or ddr timing applies to operation using either a single port or both ports . fb_clk signal for transmit data, the interface uses the fb_clk signal as the timing reference. the fb_clk signal allows source synchro - nous timing with rising edge capture for burst control signals and either rising edge capture (sdr mode) or both edge c apture (ddr mode) for transmit signal bursts. the fb_clk signal must have the same frequency and duty cycle as data_clk. rx_frame and tx_frame signals the device generates an rx_frame output signal whenever the receiver outputs valid data. this signal has two modes: level mode ( the rx_frame signal stays high as long as the data is valid) and pulse mode ( the rx_frame signal pulses with a 50% duty cycle). similarly, the bbp must provide a tx_frame signal that indicates the beginning of a valid data transmission with a rising edge. like the rx_frame signal , the tx_frame signal stay s high throughout the burst or it pulse s with a 50% duty cycle. enable state machine the ad9363 transceiver includes an ensm that allows real - time control over the current state of the device. the device can be placed in several different states dur ing normal operation, including ? wait power save, synthesizers disabled ? s leep w ait with all clocks and the bb pll disabled ? tx tx signal chain enabled ? rx rx signal chain enabled ? fdd tx and rx signal chains enabled ? alert synthesizers enabled the ensm has two control m ode s: spi control and pin control. spi control mode in spi control mode, the ensm is controlled asynchronously by writing to spi registers to advance the current state to the next state. s pi control is considered asynchronous to the data_clk signal because the spi clock can b e derived from a different clock reference and can still function properly. the spi control ensm m ode is recommended when real - time control of the synthe sizers is not necessary. spi control can be used for real - time control as long as the bb p can perform t imed spi writes accurately. pin control mode in pin control mode , the enable function s of the enable pin and the txnrx pin allow real - time control of the current state. the ensm allows tdd or fdd operation , depending on the configuration of the corresponding spi register. the enable and txnrx pin control mode is recommended if the bb p has extra control outputs that can be controlled in real time, allow - ing a simple 2 - wire interface to control the state of th e device. to advance the current state of the ensm to the next state, drive the enable function of the enable pin by either a pulse (edge detected internally) or a level. when a pulse is used, it must have a minimum pulse width of one cycle of the fb_clk s ignal . in level mode, the enable and txnrx pins are also edge detected by th e ad9363 and must meet the same minimum pulse width requirement of one cycle of the fb_clk signal . in fdd mode, the enable and txnrx pins can be remapped to serve as real - time rx and tx data transfer control signals. in this mode, the enable pin assumes the receive on ( rxon ) function (controls when the rx path is enabled and disabled), and the txnrx pin assumes the tran smit on ( txon ) f u nction (controls when the tx path is enabled and disabled ) . t he ensm must be controlled by spi writes in this mode while the enable and txnrx pins control all data flow . for more information about rxon and txon, see the ad9363 reference manual, available from integrated wideband rf transceiver design resources .
ad9363 data sheet rev. d | page 30 of 32 spi interface the ad9363 uses a serial peripheral inte rface (spi) to communi - cate with the bbp. the spi can be configured as a 4 - wire interface with dedicated receive and transmit ports, or it can be configured as a 3 - wire interface with a bi direction al data communication port. this bus allows the bbp to set all device control parameters using a simple address data serial bus protocol. write commands follow a 24 - bit format. the first six bits set the bus direction and number of bytes to transfer. the next 10 bits set the address where data is to be written. the final eight bits are the data to be transferred to the specified register address (msb to lsb). the ad9363 also supports an lsb first format that allows the commands to be written in lsb to msb format. in this mode, the register addr esses are incremented for multi byte writes. read commands follow a similar format with the except ion that the first 16 bits are transferred on the spi_di pin , and the final eight bits are read from the ad9363 , either on the spi_do pin in 4 - wire mode or on the s pi_di pin in 3 - wire mode. control pins control outputs (ctrl_out 7 to ctrl_out 0 ) the ad9363 provides eight simultaneous real - time output signals for use as interrupts to the bbp. these outputs can be configured to output a number of internal settings and measurements that the bbp use s when monitoring trans - ceiver performance in different situations. the control output pointer register selects the information that is output to these pins, and the co ntrol output enable register determines which signals are activated for monitoring by the bbp. signals used for manual gain mode, calibration flags, state machine states, and the adc output are among the outputs that can be monitored on these pins. control inputs (ctrl_in 3 to ctrl_in 0) the ad9363 provides four edge detected control input pins . in manual gain mode, the bbp use s these pins to change the gain table index in real time. gpo pins (gpo _3 to gpo_ 0 ) the ad9363 provides four 3.3 v capable general - purpose logic output pins: gpo_3, gpo_2, gpo_1, and gpo_0. these pins control other peripheral devices such as regulators and switches via the ad9363 spi bus , or they function as slaves for the internal ad9363 state machine. a uxiliary converters auxadc the ad9363 contains an auxiliary adc that monitor s system functions such as temperature or power output. the converter is 12 bits wide and has an input range of 0 .05 v to vdda1p3_bb ? 0.05 v . when enabled, the adc is free running. spi reads provide the las t value latched at the adc output. a multiplexer in front of the adc allows the user to select between the auxadc input pin and a built - in temperature sensor. auxdac1 and auxdac2 the ad9363 contains two identical auxiliary dacs that can provide power amplifier (pa) bias or other system functionality. the auxiliary dacs are 10 bits wide, have an ou tput voltage range of 0.5 v to vdd_gpo ? 0.3 v and a current drive of 10 ma, and can be directly controlled by t he internal ensm . powering the ad9363 t he ad9363 must be powered by the following three supplies : the analog supply ( vdd x = 1.3 v), the interface supply (vdd_ interface = 1.8 v), and the gpo supply (vdd_gpo = 3.3 v). for applications requiring optimal noise performance, split and source the 1.3 v analog supply from low noise, low dropout (ldo) regulators. figure 42 shows th e recommended method. figure 42 . lo w n oise power solution for the ad9363 for applications where board space is at a premium, and optimal noise performance is not an absolute requirement, provide the 1.3 v analog rail directly from a switcher , and adopt a more integrated power management unit ( pmu ) approach. figure 43 shows this approach. figure 43 . space optimized power solution for the ad9363 3.3v 1.8v 1.3v_a 1.3v_b adp2164 adp1755 adp1755 10558-074 adp1755 ldo adp5040 1.2a buck 300ma ldo 300ma ldo ad9363 1.3v vddx 1.8v vdd_interface 3.3v vdd_gpo 10558-075
data sheet ad9363 rev. d | page 31 of 32 applications informa tion for a dditional information about how to program the ad9363 device, see the ad9363 reference manual , and for a dditional information about the ad9363 r egister s, see the ad9363 register map reference manual , b oth of which are available by registering at the integrated wideband rf transceiver design resources web page and clicking download the ad9363 design file package . the register map is provided as a conveni ent and informational resource about low level operation of the device; however, it is not recommended for creating user software. analog devices , inc., provides complete drivers for the ad9363 for both bare metal/ no operating system (no os ) a nd linux operating systems. the ad9361 , ad9363 , and ad9364 share the same application program interface ( api ) . for t he ad9361 drivers , visit the following online locations: ? linux wiki page ? no os w iki page for s upport for these drivers , visit the following online locations: ? linux engineer zone? page ? no os engin eer zone page
ad9363 data sheet rev. d | page 32 of 32 packaging and ordering information outline dimensions figure 44. 144-ball chip scale package ball grid array [csp_bga] (bc-144-7) dimensions shown in millimeters ordering guide model 1 temperature range package description package option ad9363abcz ?40c to +85c 144-ball chip scale package ball grid array [csp_bga] bc-144-7 ad9363abcz-reel ?40c to +85c 144-ball chip scal e package ball grid array [csp_bga] bc-144-7 adrv9363-w/pcbz evaluation board, 325 mhz to 3800 mhz matching circuits 1 z = rohs compliant part. compliant to jedec standards mo-275-eeab-1. 11-18-2011-a 0.80 0.60 ref a b c d e f g 9 10 8 1112 7 5 642 31 bottom view 8.80 sq h j k l m detail a top view detail a coplanarity 0.12 0.50 0.45 0.40 1.70 max ball diameter seating plane 10.10 10.00 sq 9.90 a1 ball corner a1 ball corner 0.32 min 1.00 min ?2016 analog devices, inc. all rights reserved. trademarks and registered trademarks are the prop erty of their respective owners. d10558-0-11/16(d)

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