 |
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
| Datasheet File OCR Text: |
| ? semiconductor components industries, llc, 2014 november, 2014 ? rev. 4 1 publication order number: amis?42770/d amis-42770 dual high speed can transceiver general description controller area network (can) is a serial communication protocol, which supports distributed real?time control and multiplexing with high safety level. typical applications of can?based networks can be found in automotive and industrial environments. the amis?42770 dual?can transceiver is the interface between up to two physical bus lines and the protocol controller and will be used for serial data interchange between different electronic units at more than one bus line. it can be used for both 12 v and 24 v systems. the circuit consists of following blocks: ? two differential line transmitters ? two differential line receivers ? interface to the can protocol handler ? interface to expand the number of can busses ? logic block including repeater function and the feedback suppression ? thermal shutdown circuit (tsd) due to the wide common?mode voltage range of the receiver inputs, the amis?42770 is able to reach outstanding levels of electromagnetic susceptibility (ems). similarly, extremely low electromagnetic emission (eme) is achieved by the excellent matching of the output signals. key features ? fully compatible with the iso 11898?2 standard ? certified ?authentication on can transceiver conformance (d1.1)? ? wide range of bus communication speed (up to 1 mbit/s in function of the bus topology) ? allows low transmit data rate in networks exceeding 1 km ? ideally suited for 12 v and 24 v industrial and automotive applications ? low eme: common?mode?choke is no longer required ? differential receiver with w ide common?mode range ( 35 v) for high ems ? no disturbance of the bus lines with an un?powered node ? prolonged dominant time?out function allowing communication speeds down to 1 kbit/s ? thermal protection ? bus pins protected against transients ? short circuit proof to supply voltage and ground ? this is a pb?free device* *for additional information on our pb?free strategy and soldering details, please download the on semiconductor soldering and mounting techniques reference manual, solderrm/d. soic 20 ic suffix case 751aq http://onsemi.com see detailed ordering and shipping information in the package dimensions section on page 2 of this data sheet. ordering information a = assembly location wl = wafer lot yy = year ww = work week g = pb?free package 1 20 amis42770 icaw?n awlyywwg
amis?42770 http://onsemi.com 2 ordering information part number package shipping configuration temperature range amis42770icaw1g soic?20 300 (pb?free, green) 38 / tube ?40 c to 125 c amis42770icaw1rg soic?20 300 (pb?free, green) 1500 / tape & reel ?40 c to 125 c table 1. technical characteristics symbol parameter conditions min. max. unit v canhx dc voltage at pin canh1/2 0 < v cc < 5.25 v; no time limit ?45 +45 v v canlx dc voltage at pin canl1/2 0 < v cc < 5.25 v; no time limit ?45 +45 v v o(dif)(bus_dom) differential bus output voltage in dominant state 42.5 < r lt < 60 1.5 3 v cm?range input common?mode range for comparator guaranteed differential receiver threshold and leakage current ?35 +35 v v cm?peak common?mode peak see figures 10 and 11 (note 1) ?1000 +1000 mv v cm?step common?mode step see figures 10 and 11 (note 1) ?250 +250 mv 1. the parameters v cm?peak and v cm?step guarantee low eme. amis?42770 gnd rx0 2 x timer clock logic unit por 3792 5 6 15 16 17 12 feedback suppression rint tx0 text vcc 4 canh1 canl1 8 driver control thermal shutdown comp + 10 13 14 enb1 ? timer canh2 canl2 driver control comp + 19 18 enb2 ? timer figure 1. block diagram v ref v cc r i(cm) r i(cm) v cc/2 v cc v cc v cc feedback suppression r i(cm) r i(cm) v cc/2 amis?42770 http://onsemi.com 3 typical application application description amis?42770 is especially designed to provide the link between a can controller (protocol ic) and two physical busses. it is able to operate in three different modes: ? dual can ? a can?bus extender ? a can?bus repeater application schematics amis?42770 text rx0 tx0 7 9 2 3 10 rint 4 canh2 canl1 gnd vref vcc 18 13 12 19 14 8 5 6 15 16 17 canl2 canh1 can bus 2 can bus 1 100 nf vbat 5 v?reg figure 2. application diagram can?bus repeater r lt 60 r lt 60 c d en1 en2 amis?42770 text rx0 tx0 7 9 2 3 10 rint 4 vbat canh2 canl1 gnd vcc vref vcc 18 13 12 19 14 8 gnd can controller 5 v?reg 5 6 15 16 17 canl2 canh1 can bus 2 can bus 1 100 nf 100 nf figure 3. application diagram dual?can c c d c d en1 en2 r lt 60 r lt 60 amis?42770 http://onsemi.com 4 amis?42770 text rx0 tx0 7 9 2 3 10 rint 4 vbat canh2 canl1 gnd vcc vref vcc 18 13 12 19 14 8 gnd can controller 5 v?reg 5 6 15 16 17 canl2 canh1 can bus 2 can bus 1 100 nf 100 nf amis?42770 text rx0 tx0 7 9 2 3 10 rint 4 canh2 canl1 gnd vref vcc 18 13 12 19 14 8 5 6 15 16 17 canl2 canh1 can bus 4 can bus 3 100 nf isolated +5 dual optocoupler figure 4. application diagram can?bus extender r lt 60 r lt 60 r lt 60 r lt 60 en1 en2 en1 en2 c d c d c c d tx0 gnd gnd 14 15 16 17 18 19 20 1 2 3 4 5 6 7 nc rx0 vref1 rint nc gnd canl1 canh1 vcc 8 9 10 13 12 11 nc gnd gnd canl2 canh2 text figure 5. pin out (top view) amis?42770 en1 en2 amis?42770 http://onsemi.com 5 table 2. pin description pin name description 1 nc not connected 2 enb2 enable input, bus system 2; internal pull?up 3 text multi?system transmitter input; internal pull?up 4 tx0 transmitter input; internal pull?up 5 gnd ground connection (note 2) 6 gnd ground connection (note 2) 7 rx0 receiver output 8 v ref1 reference voltage 9 rint multi?system receiver output 10 enb1 enable input, bus system 1; internal pull?up 11 nc not connected 12 vcc positive supply voltage 13 canh1 canh transceiver i/o bus system 1 14 canl1 canl transceiver i/o bus system 1 15 gnd ground connection (note 2) 16 gnd ground connection (note 2) 17 gnd ground connection (note 2) 18 canl2 canl transceiver i/o bus system 2 19 canh2 canh transceiver i/o bus system 2 20 nc not connected 2. in order to ensure the chip performance, all these pins need to be connected to gnd on the pcb. functional description overall functional description amis?42770 is specially designed to provide the link between the protocol ic (can controller) and two physical bus lines. data interchange between those two bus lines is realized via the logic unit inside the chip. to provide an independent switch?off of the transceiver units for both bus systems by a third device (e.g. the c), enable?inputs for the corresponding driving and receiving sections are provided. as long as both lines are enabled, they appear as one logical bus to all nodes connected to either of them. the bus lines can have two logical states, dominant or recessive. a bus is in the recessive state when the driving sections of all transceivers connected to the bus are passive. the differential voltage between the two wires is approximately zero. if at least one driver is active, the bus changes into the dominant state. this state is represented by a differential voltage greater than a minimum threshold and therefore by a current flow through the terminating resistors of the bus line. the recessive state is overwritten by the dominant state. in case a fault (like short circuit) is present on one of the bus lines, it remains limited to that bus line where it occurs. data interchange from the protocol ic to the other bus system and on this bus system itself can be continued. amis?42770 can be also used for only one bus system. if the connections for the second bus system are simply left open it serves as a single transceiver for an electronic unit. for correct operation, it is necessary to terminate the open bus by the proper termination resistor. logic unit and can controller interface the logic unit inside amis?42770 provides data transfer from/to the digital interface to/from the two busses and from one bus to the other bus. the detailed function of the logic unit is described in table 3. all digital input pins, including enbx, have an internal pull?up resistor to ensure a recessive state when the input is not connected or is accidentally interrupted. a dominant state on the bus line is represented by a low?level at the digital interface; a recessive state is represented by a high?level. dominant state received on any bus (if enabled) causes a dominant state on both busses, pin rint and pin rx0. dominant signal on any of the input pins tx0 and text causes transmission of dominant on both bus lines (if enabled). digital inputs tx0 and text are used for connecting the internal logic? s of several ic?s to obtain versions with more than two bus outputs (see figure 4). they have also a direct logical link to pins rx0 and rint independently on the en1x pins ? dominant on tx0 is directly transferred to both rx0 and rint pins, dominant on text is only transferred to rx0. amis?42770 http://onsemi.com 6 transmitters the transceiver includes two transmitters, one for each bus line, and a driver control circuit. each transmitter is implemented as a push and a pull driver. the drivers will be active if the transmission of a dominant bit is required. during the transmission of a recessive bit all drivers are passive. the transmitters have a built?in current limiting circuit that protects the driver stages from damage caused by accidental short circuit to either positive supply voltage or to ground. additionally a thermal protection circuit is integrated. the driver control circuit ensures that the drivers are switched on and off with a controlled slope to limit eme. the driver control circuit will control itself by the thermal protection circuit, the timer circuit and the logic unit. the enable signal enbx allows the transmitter to be switched off by a third device (e.g. the c). in the disabled state (enbx = high) the corresponding transmitter behaves as in the recessive state. table 3. function of the logic unit ( bold letters describe input signals) en1b en2b tx0 text bus 1 state bus 2 state rx0 rint 0 0 0 0 dominant dominant 0 0 0 0 0 1 dominant dominant 0 0 0 0 1 0 dominant dominant 0 1 0 0 1 1 recessive recessive 1 1 0 0 1 1 dominant (note 3) dominant 0 0 0 0 1 1 dominant dominant (note 3) 0 0 0 1 0 0 dominant recessive 0 0 0 1 0 1 dominant recessive 0 0 0 1 1 0 dominant recessive 0 1 0 1 1 1 recessive recessive 1 1 0 1 1 1 dominant (note 3) recessive 0 0 0 1 1 1 recessive dominant (note 3) 1 1 1 0 0 0 recessive dominant 0 0 1 0 0 1 recessive dominant 0 0 1 0 1 0 recessive dominant 0 1 1 0 1 1 recessive recessive 1 1 1 0 1 1 dominant (note 3) recessive 1 1 1 0 1 1 recessive dominant (note 3) 0 0 1 1 0 0 recessive recessive 0 0 1 1 0 1 recessive recessive 0 0 1 1 1 0 recessive recessive 0 1 1 1 1 1 recessive recessive 1 1 1 1 1 1 dominant (note 3) recessive 1 1 1 1 1 1 recessive dominant (note 3) 1 1 3. dominant detected by the corresponding receiver. receivers two bus receiving sections sense the states of the bus lines. each receiver section consists of an input filter and a fast and accurate comparator. the aim of the input filter is to improve the immunity against high?frequency disturbances and also to convert the voltage at the bus lines canhx and canlx, which can vary from ?12 v to +12 v, to voltages in the range 0 to 5 v, which can be applied to the comparators. the output signal of the comparators is gated by the enbx signal. in the disabled state (enbx = high), the output signal of the comparator will be replaced by a permanently recessive state and does not depend on the bus voltage. in the enabled state the receiver signal sent to the logic unit is identical to the comparator output signal. time?out counter to avoid that the transceiver drives a permanent dominant state on either of the bus lines (blocking all communication), time?out function is implemented. signals on pins tx0 and text as well as both bus receivers are connected to the logic unit through independent timers. if the input of the timer stays dominant for longer than 25 ms (see parameter t dom ), it is replaced by a recessive signal on the timer output. amis?42770 http://onsemi.com 7 feedback suppression the logic unit described in table 3 constantly ensures that dominant symbols on one bus line are transmitted to the other bus line without imposing any priority on either of the lines. this feature would lead to an ?interlock? state with permanent dominant signal transmitted to both bus lines, if no extra measure is taken. therefore feedback suppression is included inside the logic unit of the transceiver. this block masks?out reception on that bus line, on which a dominant is actively transmitted. the reception becomes active again only with certain delay after the dominant transmission on this line is finished. power?on?reset (por) while vcc voltage is below the por level, the por circuit makes sure that: ? the counters are kept in the reset mode and stable state without current consumption ? inputs are disabled (don?t care) ? outputs are high impedant; only rx0 = high?level ? analog blocks are in power down ? oscillator not running and in power down ? canhx and canlx are recessive ? vref output high impedant for por not released over temperature detection a thermal protection circuit is integrated to prevent the transceiver from damage if the junction temperature exceeds thermal shutdown level. because the transmitters dissipate most of the total power, the transmitters will be switched off only to reduce power dissipation and ic temperature. all other ic functions continue to operate. fault behavior a fault like a short circuit is limited to that bus line where it occurs; hence data interchange from the protocol ic to the other bus system is not affected. when the voltage at the bus lines is going out of the normal operating range (?12 v to +12 v), the receiver is not allowed to erroneously detect a dominant state. short circuits a current?limiting circuit protects the transmitter output stage from damage caused by an accidental short?circuit to either positive or negative supply voltage, although power dissipation increases during this fault condition. the pins canhx and canlx are protected from automotive electrical transients (according to ?iso 7637?). electrical characteristics definitions all voltages are referenced to gnd. positive currents flow into the ic. sinking current means that the current is flowing into the pin. sourcing current means that the current is flowing out of the pin. table 4. absolute maximum ratings symbol parameter conditions min. max. unit v cc supply voltage ?0.3 +7 v v canhx dc voltage at pin canh1/2 0 < v cc < 5.25 v; no time limit ?45 +45 v v canlx dc voltage at pin canl1/2 0 < v cc < 5.25 v; no time limit ?45 +45 v v digio dc voltage at digital io pins (en1b, en2b, rint, rx0, text, tx0) ?0.3 v cc + 0.3 v v ref dc voltage at pin v ref ?0.3 v cc + 0.3 v v tran(canhx) transient voltage at pin canh1/2 (note 4) ?150 +150 v v tran(canlx) transient voltage at pin canl1/2 (note 4) ?150 +150 v v esd(canlx/canhx) esd voltage at canh1/2 and canl1/2 pins (note 5) (note 7) ?4 ?500 +4 +500 kv v v esd esd voltage at all other pins (note 5) (note 7) ?2 ?250 +2 +250 kv v latch?up static latch?up at all pins (note 6) 100 ma t stg storage temperature ?55 +155 c t amb ambient temperature ?40 +125 c t junc maximum junction temperature ?40 +150 c stresses exceeding those listed in the maximum ratings table may damage the device. if any of these limits are exceeded, device function ality should not be assumed, damage may occur and reliability may be affected. 4. applied transient waveforms in accordance with ?iso 7637 part 3?, test pulses 1, 2, 3a, and 3b (see figure 6) 5. standardized human body model (hbm) esd pulses in accordance to mil883 method 3015. supply pin 8 is 2 kv. 6. static latch?up immunity: static latch?up protection level when tested according to eia/jesd78. 7. standardized charged device model esd pulses when tested according to eos/esd ds5.3?1993. amis?42770 http://onsemi.com 8 table 5. thermal characteristics symbol parameter conditions value unit r th(vj?a) thermal resistance from junction to ambient in so20 package in free air 85 k/w r th(vj?s) thermal resistance from junction to substrate of bare die in free air 45 k/w dc characteristics table 6. dc and timing characteristics ( v cc = 4.75 to 5.25 v; t junc = ?40 to +150 c; r lt = 60 w unless specified otherwise.) symbol parameter conditions min. typ. max. unit supply (pin v cc ) i cc supply current, no loads on di- gital outputs, both busses en- abled dominant transmitted recessive transmitted 45 137.5 19.5 ma porl_vcc power?on?reset level on v cc 2.2 4.7 v digital inputs (tx0, text, en1b, en2b) v ih high?level input voltage 0.7 x v cc ? v cc v v il low?level input voltage ?0.3 ? 0.3 x v cc v i ih high?level input current v in = v cc ?5 0 +5 a i il low?level input current v in = 0 v ?75 ?200 ?350 a c i input capacitance not tested ? 5 10 pf digital outputs (pin rx0, rint) i oh high?level output current v o = 0.7 x v cc ?5 ?10 ?15 ma i ol low?level output current v o = 0.3 x v cc 5 10 15 ma reference voltage output (pin v ref1 ) v ref reference output voltage ?50 a < i vref < +50 a 0.45 x v cc 0.50 x v cc 0.55 x v cc v v ref_cm reference output voltage for full common mode range ?35 v amis?42770 http://onsemi.com 10 measurement set?ups and definitions schematics are given for single can transceiver. amis?42770 text rx0 tx0 7 9 2 3 10 rint 4 canh2 canl1 gnd vref vcc 18 13 12 19 14 8 canl2 canh1 100 nf +5v 5 6 15 16 17 1 nf 1 nf transient generator figure 6. test circuit for automotive transients en1 en2 high low 0,5 0,9 hysteresis figure 7. hysteresis of the receiver v rxd v i(dif)(hys) amis?42770 text rx0 tx0 7 9 2 3 10 rint 4 canh2 canl1 gnd vref vcc 18 13 12 19 14 8 canl2 canh1 100 nf +5 v 5 6 15 16 17 100 pf 100 pf figure 8. test circuit for timing characteristics en1 en2 c lt c lt r lt r lt 60 60 amis?42770 http://onsemi.com 11 tx0 0,9 v 0 v 5 v 0,5 v recessive dominant rx0 text rint 0,5 v 0,9 v figure 9. timing diagram for ac characteristics 0,7 v cc 0,3 v cc t d(busoff?rx) t pd(h) t d(buson?rx) 0,7 v cc 0,3 v cc 0,7 v cc 0,3 v cc v canhx v canlx v canhx?bus t d(tx?rx) t d(tx?busoff) t d(tx?rx) t d(tx?buson) v diff = v canhx ? v canlx 10 nf active probe 47 nf spectrum anayzer amis?42770 text rx0 tx0 7 9 2 3 10 rint 4 canh2 canl1 gnd vref vcc 18 13 12 19 14 8 canl2 canh1 100 nf +5 v 5 6 15 16 17 gen figure 10. basic test set?up for electromagnetic measurement en1 en2 6.2 k 6.2 k 30 30 amis?42770 http://onsemi.com 12 v cm = 0.5* (v canhx + v canlx ) canhx canlx recessive figure 11. common?mode voltage peaks (see measurement set?up figure 10) v cm?peak v cm?peak v cm?peak company or product inquiries for more information about on semiconductor?s products or services visit our web site at http://www.onsemi.com . amis?42770 http://onsemi.com 13 package dimensions soic 20 w case 751aq issue o p ublication ordering information n. american technical support : 800?282?9855 toll free usa/canada europe, middle east and africa technical support: phone: 421 33 790 2910 japan customer focus center phone: 81?3?5817?1050 amis?42770/d literature fulfillment : literature distribution center for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone : 303?675?2175 or 800?344?3860 toll free usa/canada fax : 303?675?2176 or 800?344?3867 toll free usa/canada email : orderlit@onsemi.com on semiconductor website : www.onsemi.com order literature : http://www.onsemi.com/orderlit for additional information, please contact your loc al sales representative on semiconductor and the are registered trademarks of semiconductor components industries, llc (scillc) or its subsidia ries in the united states and/or other countries. scillc owns the rights to a number of pa tents, trademarks, copyrights, trade secret s, and other intellectual property. a listin g of scillc?s product/patent coverage may be accessed at www.onsemi.com/site/pdf/patent?marking.pdf. scillc reserves the right to make changes without further notice to any product s herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for any part icular purpose, nor does sci llc assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. ?typi cal? parameters which may be provided in scillc data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. all operating param eters, including ?typicals? must be validated for each customer application by customer?s technical experts. scillc does not convey any license under its patent rights nor the right s of others. scillc products are not designed, intended, or authorized for use as components in systems intended for surgic al implant into the body, or other applications intended to s upport or sustain life, or for any other application in which the failure of the scillc product could create a situation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer s hall indemnify and hold scillc and its officers , employees, subsidiaries, affiliates, and dist ributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that scillc was negligent regarding the design or manufac ture of the part. scillc is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyright laws and is not for resale in any manner. |
Price & Availability of AMIS-42770-14
 |
|
|
|
|
All Rights Reserved © IC-ON-LINE 2003 - 2022 |
| [Add Bookmark] [Contact Us] [Link exchange] [Privacy policy] |
|
Mirror Sites : [www.datasheet.hk]
[www.maxim4u.com] [www.ic-on-line.cn]
[www.ic-on-line.com] [www.ic-on-line.net]
[www.alldatasheet.com.cn]
[www.gdcy.com]
[www.gdcy.net] |