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ltc6603 1 6603fa typical application features applications description dual adjustable lowpass filter the ltc ? 6603 is a dual, matched, programmable lowpass ? lter for communications receivers and transmitters. the selectivity of the ltc6603, combined with its linear phase, phase matching and dynamic range, make it suitable for ? ltering in many communications systems. with 1.5 phase matching between channels, the ltc6603 can be used in applications requiring pairs of matched ? lters, such as transceiver i and q channels. furthermore, the differential inputs and outputs provide a simple interface for most communications systems. the sampled data ? lter does not require an external clock yet its cutoff frequency can be set with a single external resistor with an accuracy of 3.5% or better. the external resistor programs an internal oscillator whose frequency is divided prior to being applied to the ? lter networks. this allows up to three cutoff frequencies that can be obtained for each external resistor value, allowing the cutoff frequency to be programmed over a range of more than six octaves. alternatively, the cutoff frequency can be set with an external clock. the ? lter gain can also be programmed to 1, 2, 4 or 16. the ltc6603 features a low power shutdown mode that can be programmed through the serial interface and is available in a 24-pin 4mm 4mm qfn package. 2.5mhz i and q lowpass filter and dual adc n guaranteed phase and gain matching specs n programmable bw up to 2.5mhz n programmable gain (0db/6db/12db/24db) n 9th order linear phase response n differential, rail-to-rail inputs and outputs n low noise: C145dbm/hz (input referred) n low distortion: C75dbc at 200khz n simple pin programming or spi interface n set the max speed/power with an external r n operates from 2.7v to 3.6v n input range from 0v to 5.5v n 4mm 4mm qfn package n small/low cost basestations: iden, phs, td-scdma, cdma2000, wcdma, umts n low cost repeaters, radio links, and modems n 802.11x receivers n jtrs 6603 ta01a +ina v+ in v+ a v+ d Cina +inb Cinb cap gain1 gain0 gnd gnd r bias v ocm +outa Couta +outb Coutb clkcntl sdo sdi lpfo lpf1 clkio ser ltc6603 0.1f 0.1f 180pf 180pf 10pf 10pf 180pf 180pf 10pf 10pf 49.9 100nh* *coilcraft 0603hp 49.9 100nh* 49.9 100nh* 49.9 100nh* 5v 3v 3v 3v 0.1f 0.1f 30.9k 2.2f baseband gain control ltc2297 14-bit adc 14-bit adc v cm i in q in i output q output mismatch (deg) units (%) 6603 ta01b 60 50 20 10 30 40 0 C2.5 2.5 C2 C1.5 C1 C0.5 0 0.5 1 1.5 2 v s = 3v, bw = 156.25khz f = 125khz, t a = 25c 1000 units phase matching l , lt, ltc, ltm, linear technology and the linear logo are registered trademarks of linear technology corporation. all other trademarks are the property of their respective owners.
ltc6603 2 6603fa pin configuration absolute maximum ratings v+ in to gnd ................................................................6v v+ a , v+ d to gnd .........................................................4v v+ a to v+ d .............................................. ?0.3v to +0.3v filter inputs to gnd ....................... ?0.3v to v+ in + 0.3v pins 3, 4 to gnd ............................. ?0.3v to v+ a + 0.3v pins 5, 6, 9-11, 15, 17, 21, 22 to gnd ..................... ?0.3v to v+ d + 0.3v output short-circuit duration .......................... inde? nite operating temperature range (note 2) ltc6603cuf .......................................?40c to 85c ltc6603iuf ........................................?40c to 85c speci? ed temperature range (note 3) ltc6603cuf ...........................................0c to 70c ltc6603iuf ........................................?40c to 85c storage temperature range ................... ?65c to 150c (note 1) 24 23 22 21 20 19 7 8 9 top view uf package 24-lead (4mm 4mm) plastic qfn 10 11 12 6 5 4 3 2 1 13 14 15 16 17 18 v+ in v+ a v ocm r bias clkcntl lpf1( cs) ?outa ser v+ d clkio gnd +outb +ina ?ina gain1 gain0(d0) cap +outa +inb ?inb lpfo(sclk) sdi sdo ?outb 25 t jmax = 150c, ja = 37c/w, jc = 4.3c/w exposed pad (pin 25) is gnd. must be soldered to the pcb. parameter conditions min typ max units filter gain either channel external clock = 80mhz, filter cutoff (f c )= 156.25khz, v in = 3.6v p-p, pin 3 open dc gain, gain set = 0db f in = 62.5khz (0.4 ? f c ), relative to dc gain f in = 125khz (0.8 ? f c ), relative to dc gain f in = 156.25khz (f c ), relative to dc gain f in = 234.375khz (1.5 ? f c ), relative to dc gain l l l l l 0.25 ?0.5 0.4 ?0.6 0.4 ?0.3 0.6 ?0.4 ?32 0.55 ?0.1 0.8 ?0.2 ?29.5 db db db db db matching of filter gain external clock = 80mhz, filter cutoff (f c )= 156.25khz, v in = 3.6v p-p, pin 3 open dc gain, gain set = 0db f in = 62.5khz (0.4 ? f c ) f in = 125khz (0.8 ? f c ) f in = 156.25khz (f c ) l l l l 0.03 0.03 0.03 0.03 0.1 0.1 0.1 0.15 db db db db order information lead free finish tape and reel part marking * package description specified temperature range ltc6603cuf#pbf ltc6603cuf#trpbf 6603 24-lead (4mm 4mm) plastic qfn 0c to 70c ltc6603iuf#pbf ltc6603iuf#trpbf 6603 24-lead (4mm 4mm) plastic qfn ?40c to 85c consult ltc marketing for parts speci? ed with wider operating temperature ranges. *the temperature grade is identi? ed by a label on the shipping container. consult ltc marketing for information on non-standard lead based ? nish parts. for more information on lead free part marking, go to: http://www.linear.com/leadfree/ for more information on tape and reel speci? cations, go to: http://www.linear.com/tapeandreel/ electrical characteristics the l denotes the speci? cations which apply over the full operating temperature range, otherwise speci? cations are at t a = 25c. v+ a = v+ d = v+ in = 3v, v icm = v ocm = 1.5v, gain = 0db, lowpass cutoff = 2.5mhz, internal clocking with r bias = 30.9k unless otherwise noted.
ltc6603 3 6603fa electrical characteristics the l denotes the speci? cations which apply over the full operating temperature range, otherwise speci? cations are at t a = 25c. v+ a = v+ d = v+ in = 3v, v icm = v ocm = 1.5v, gain = 0db, lowpass cutoff = 2.5mhz, internal clocking with r bias = 30.9k unless otherwise noted. parameter conditions min typ max units filter phase either channel external clock = 80mhz, filter cutoff (f c ) = 156.25khz, v in = 3.6v p-p, pin 3 open f in = 62.5khz (0.4 ? f c ) f in = 125khz (0.8 ? f c ) f in = 156.25khz (f c ) l l l 158 C44 C152 161 C39 C146 163 C36 C142 deg deg deg matching of filter phase external clock = 80mhz, filter cutoff (f c ) = 156.25khz, v in = 3.6v p-p, pin 3 open f in = 62.5khz (0.4 ? f c ) f in = 125khz (0.8 ? f c ) f in = 156.25khz (f c ) l l l 0.2 0.4 0.5 1.5 3 4 deg deg deg filter gain either channel external clock = 80mhz, filter cutoff (f c ) = 2.5mhz, v in = 3.6v p-p, pin 3 open dc gain, gain set = 0db f in = 1mhz (0.4 ? f c ), relative to dc gain f in = 2mhz (0.8 ? f c ), relative to dc gain f in = 2.5mhz (f c ), relative to dc gain f in = 4mhz (1.5 ? f c ), relative to dc gain l l l l l 0 C2 C0.7 C1.1 0.5 C0.8 0.4 0.1 C43 1.2 C0.1 1.5 1 C32.6 db db db db db matching of filter gain external clock = 80mhz, filter cutoff (f c ) = 2.5mhz, v in = 3.6v p-p, pin 3 open f in = 2mhz (0.8 ? f c ) f in = 2.5mhz (f c ) l l 0.05 0.2 0.2 0.4 db db filter phase either channel external clock = 80mhz, filter cutoff (f c ) = 2.5mhz, v in = 3.6v p-p, pin 3 open f in = 1mhz (0.4 ? f c ) f in = 2mhz (0.8 ? f c ) f in = 2.5mhz (f c ) l l l 150 C45 C152 155 C39 C141 159 C28 C126 deg deg deg matching of filter phase external clock = 80mhz, filter cutoff (f c ) = 2.5mhz, v in = 3.6v p-p, pin 3 open f in = 1mhz (0.4 ? f c ) f in = 2mhz (0.8 ? f c ) f in = 2.5mhz (f c ) l l l 2.5 4 4 deg deg deg filter cutoff accuracy when self clocked clkcntl = 3v (note 4) r bias = 200k r bias = 54.9k r bias = 30.9k l l l 3 3 3.5 % % % dc gain filter cutoff (f c ) = 2.5mhz, 0.6v to 2.4v each output, pin 3 open gain setting = 0db gain setting = 6db gain setting = 12db gain setting = 24db l l l l 0 5.6 11.2 22.5 0.5 6 11.8 23.2 1.2 6.6 12.5 24 db db db db dc gain matching filter cutoff (f c ) = 2.5mhz, 0.6v to 2.4v each output, pin 3 open gain setting = 0db gain setting = 6db gain setting = 12db gain setting = 24db l l l l 0.1 0.05 0.05 0.1 0.2 0.1 0.15 0.2 db db db db noise at 200khz voltage noise referred to the input gain = 0db gain = 6db gain = 12db gain = 24db C124 C129 C135 C145 dbm/hz dbm/hz dbm/hz dbm/hz integrated noise noise bandwidth = 5mhz, referred to the input gain = 0db gain = 6db gain = 12db gain = 24db C53 C59 C65 C76 dbm dbm dbm dbm thd v in = 2v p-p , f in = 200khz, gain setting = 24db C75 db input impedance gain = 24db, r bias = 30.9k, filter cutoff (f c ) = 2.5mhz differential common mode 1.6 5 k k
ltc6603 4 6603fa electrical characteristics the l denotes the speci? cations which apply over the full operating temperature range, otherwise speci? cations are at t a = 25c. v+ a = v+ d = v+ in = 3v, v icm = v ocm = 1.5v, gain = 0db, lowpass cutoff = 2.5mhz, internal clocking with r bias = 30.9k unless otherwise noted. parameter conditions min typ max units v os differential input referred differential offset voltage at either output lowest cutoff frequency, gain setting = 24db highest cutoff frequency, gain setting = 24db lowest cutoff frequency, gain setting = 0db highest cutoff frequency, gain setting = 0db l l l l 8 14 40 60 mv mv mv mv cmrr differential f c = 625khz common mode input from 0v to 3v, v+ in = 3v common mode input from 0v to 5v, v+ in = 5v l l 60 60 90 90 db db v ocm pin voltage v+ a = v+ d = 3v, pin 3 open, f c = 156.25khz l 1.3 1.45 1.5 v v ocm pin input impedance v+ a = v+ d = 3v, pin 3 open, f c = 156.25khz l 2.5 3.4 4.5 k v oscm common mode offset voltage, v ocm = 1.5v, supplies = 3v v oscm = v out-cm C v ocm l 100 185 mv output swing f c = 156.25khz source 1ma, relative to v+ a sink 1ma, relative to gnd l l 200 150 500 400 mv mv short-circuit current f c = 156.25khz sourcing sinking l l 7 11 25 30 ma ma supply current internal clock (r bias = 30.9k); sum of the currents into v+ d , v+ a , and v+ in all supplies set to 3v f c = 156.25khz f c = 625khz f c = 2.5mhz l l l 88 121 162 96 130 175 ma ma ma supply current, shutdown mode sum of the currents into v+ d , v+ a , and v+ in ; all supplies set to 3v shutdown via serial interface l 170 235 a supply voltage v+ d , v+ a relative to gnd v+ in relative to gnd l l 2.7 2.7 3.6 5.5 v v psrr v+ d = v+ a = v+ in , all from 2.7v to 3.6v v+ d = v+ a = 3v, v+ in from 4.5v to 5.5v l l 40 65 50 85 db db r bias resistor range clkcntl = 3v clock frequency error < 3.5% clock frequency error < 3% l l 30.9 54.9 54.9 200 k k r bias pin voltage 30.9k < r bias < 200k 1.17 v clock frequency drift over temperature r bias = 30.9k clkcntl pin open 40 ppm/oc clock frequency drift over supply v+ a , v+ d from 2.7v to 3.6v, r bias = 30.9k clkcntl pin open l 0.2 0.5 %/v output clock duty cycle r bias = 30.9k l 45 50 55 % clkio pin high level input voltage clkcntl = 0v (note 5) l v+ d C 0.3 v clkio pin low level input voltage clkcntl = 0v (note 5) l 0.3 v clkio pin input current clkcntl = 0v clkio = 0v (note 6) clkio = v+ d l l C1 10 a a clkio pin high level output voltage v+ a = v+ d = 3v, clkcntl = 3v i oh = C1ma i oh = C4ma 2.95 2.9 v v
ltc6603 5 6603fa electrical characteristics the l denotes the speci? cations which apply over the full operating temperature range, otherwise speci? cations are at t a = 25c. v+ a = v+ d = v+ in = 3v, v icm = v ocm = 1.5v, gain = 0db, lowpass cutoff = 2.5mhz, internal clocking with r bias = 30.9k unless otherwise noted. parameter conditions min typ max units clkio pin low level output voltage v+ a = v+ d = 3v, clkcntl = 3v i ol = 1ma i ol = 4ma 0.05 0.1 v v clkio pin rise time v+ a = v+ d = clkcntl = 3v, c load = 5pf 0.3 ns clkio pin fall time v+ a = v+ d = clkcntl = 3v, c load = 5pf 0.3 ns ser high level input voltage pin 17 l v+ d C 0.3 v ser low level input voltage pin 17 l 0.3 v ser input current pin 17 = 0v (note 6) pin 17 = v+ d l l C10 2 a a clkcntl high level input voltage pin 5 l v+ d C 0.5 v clkcntl low level input voltage pin 5 0.5 v clkcntl input current clkcntl = 0v (note 6) clkcntl = v+ d l l C25 C15 15 25 a a pin programmable control mode speci? cations. speci? cations apply to pins 6, 9, 21 and 22 in pin programmable control mode. symbol parameter conditions min typ max units v+ d = 2.7v to 3.6v v ih digital input high voltage pins 6, 9, 21, 22 l 2v v il digital input low voltage pins 6, 9, 21, 22 l 0.8 v i in digital input current pins 6, 9, 21, 22 (note 6) l C1 1 a serial port dc and timing speci? cations. speci? cations apply to pins 6, 9-11, and 21 in serial programming mode. symbol parameter conditions min typ max units v+ d = 2.7v to 3.6v v ih digital input high voltage pins 6, 9, 10 l 2v v il digital input low voltage pins 6, 9, 10 l 0.8 v i in digital input current pins 6, 9, 10 (note 6) l C1 1 a v oh digital output high voltage pins 11, 21 sourcing 500a l v supply C 0.3 v v ol digital output low voltage pins 11, 21 sinking 500a l 0.3 v t 1 (note 5) sdi valid to sclk setup l 60 ns t 2 (note 5) sdi valid to sclk hold l 0ns t 3 sclk low l 100 ns t 4 sclk high l 100 ns t 5 cs pulse width l 60 ns t 6 (note 5) lsb sclk to cs l 60 ns t 7 (note 5) cs low to sclk l 30 ns t 8 sdo output delay c l = 15pf l 125 ns t 9 (note 5) sclk low to cs low l 0ns
ltc6603 6 6603fa electrical characteristics note 1: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. exposure to any absolute maximum rating condition for extended periods may affect device reliability and lifetime. note 2: ltc6603c and ltc6603i are guaranteed functional over the operating temperature range of C40c to 85c. note 3: ltc6603c is guaranteed to meet speci? ed performance from 0c to 70c. the ltc6603c is designed, characterized and expected to meet speci? ed performance from C40c to 85c but is not tested or qa sampled at these temperatures. the ltc6603i is guaranteed to meet the speci? ed performance limits from C40c to 85c. typical performance characteristics dc gain matching dc gain matching phase matching phase matching gain and group delay vs frequency note 4: this test measures the internal oscillator accuracy (deviation from the f clk equation). variations in the internal oscillator cause variations in the ? lter cutoff frequency. see the applications information section. note 5: guaranteed by design, not subject to test. note 6: to conform to the logic ic standard, current out of a pin is arbitrarily given a negative value. mismatch (db) units (%) 6603 g01 70 60 20 10 30 40 50 0 C0.2 0.2 C0.15 C0.1 C0.05 0 0.05 0.1 0.15 v s = 3v, bw = 2.5mhz gain setting = 0db, t a = 25c 1000 units mismatch (db) units (%) 6603 g02 70 60 20 10 30 40 50 0 C0.06 0.1 C0.04 C0.02 0 0.02 0.04 0.06 0.08 v s = 3v, bw = 156.25khz gain setting = 0db, t a = 25c 1000 units mismatch (deg) units (%) 6603 g03 30 25 5 10 15 20 0 C2.5 4 C2C1.5C1C0.5 0 0.5 1 1.5 2 2.5 3 3.5 v s = 3v, bw = 2.5mhz f = 2mhz, t a = 25c 1000 units mismatch (deg) units (%) 6603 g04 60 50 20 10 30 35 40 0 C2.5 2.5 C2 C1.5 C1 C0.5 0 0.5 1 1.5 2 v s = 3v, bw = 156.25khz f = 125khz, t a = 25c 1000 units frequency (hz) gain (db) 6603 g05 30 10 0 20 C60 C40 C50 C30 C20 C10 C70 group delay (ns) 800 720 680 760 440 520 480 560 600 640 400 10k 1m 10m 100k r bias = 30.9k, v s = 3v lpf1 = 1, bw = 2.5mhz t a = 25c gain = 24db gain = 12db gain = 6db gain = 0db group delay
ltc6603 7 6603fa typical performance characteristics gain and group delay vs frequency distortion vs input frequency distortion vs input frequency gain and group delay vs frequency distortion vs input frequency distortion vs input frequency distortion vs output voltage filter cutoff accuracy vs supply voltage filter cutoff accuracy vs temperature frequency (hz) gain (db) 6603 g06 30 10 0 20 C60 C40 C50 C30 C20 C10 C70 group delay (ns) 3.5 3.1 2.9 3.3 1.7 2.1 1.9 2.3 2.5 2.7 1.5 10k 1m 10m 100k r bias = 30.9k, v s = 3v lpf1 = 0, lpf0 = 1, bw = 625khz t a = 25c gain = 24db gain = 0db group delay gain = 6db gain = 12db frequency (hz) gain (db) 6603 g07 30 10 0 20 C60 C40 C50 C30 C20 C10 C70 group delay (s) 12.0 11.0 10.5 11.5 7.5 8.5 8.0 9.0 9.5 10.0 7.0 1k 100k 1m 10k r bias = 30.9k, v s = 3v lpf1 = lpf0 = 0, bw = 156.25khz t a = 25c gain = 24db gain = 0db group delay gain = 6db gain = 12db input frequency (khz) 100 distortion (dbc) C50 C60 C80 C70 C90 900 1700 500 1300 6603 g08 r bias = 30.9k, v s = 3v lpf1 = 1, bw = 2.5mhz v out = 2v p-p , t a = 25c hd2, gain = 24db hd3, gain = 24db hd3, gain = 0db hd2, gain = 0db input frequency (khz) 100 distortion (dbc) C60 C65 C80 C85 C70 C75 C90 900 500 6603 g09 700 300 1100 r bias = 54.9k, v s = 3v lpf1 = 1, bw = 1.41mhz t a = 25c hd2, gain = 24db hd3, gain = 24db hd3, gain = 0db hd2, gain = 0db input frequency (khz) 20 distortion (dbc) C60 C65 C80 C85 C70 C75 C90 420 220 6603 g10 320 120 520 r bias = 30.9k, v s = 3v lpf1 = 0, lpf0 = 1, bw = 625khz v out = 2v p-p , t a = 25c hd2, gain = 24db hd3, gain = 0db hd2, gain = 0db hd3, gain = 24db input frequency (khz) 10 distortion (dbc) C70 C75 C90 C95 C80 C85 C100 90 50 6603 g11 70 30 110 130 150 r bias = 30.9k, v s = 3v lpf1 = lpf0 = 0, bw = 156.25khz v out = 2v p-p , t a = 25c hd2, gain = 24db hd3, gain = 0db hd2, gain = 0db hd3, gain = 24db output voltage (v p-p ) 1.0 distortion (dbc) C60 C70 C90 C80 C100 1.8 1.4 6603 g11 1.6 1.2 2.0 2.2 2.4 2.6 2.8 3.0 r bias = 30.9k, v s = 3v, lpf1 = 0, lpf0 = 1, bw = 2.5mhz, gain = 24db, t a = 25c hd2, f = 1mhz hd2, f = 200khz hd3, f = 1mhz hd3, f = 200khz supply voltage (v) 2.7 filter cutoff frequency deviation (%) 0.2 C0.6 C0.4 C0.5 C0.3 C0.2 C0.1 0.0 0.1 C0.8 C0.7 C0.9 3.1 2.9 6603 g13 3.0 2.8 3.2 3.3 3.4 3.5 3.6 r bias = 30.9k t a = 25c lpf1 = lpf0 = 0, bw = 156.25khz lpf1 = 0, lpf0 = 1, bw = 625khz lpf1 = 1, bw = 2.5mhz temperature (c) C50 filter cutoff frequency deviation (%) 1.0 C0.6 C0.2 C0.4 0.0 0.2 0.4 0.6 0.8 C0.8 30 C10 6603 g14 10 C30 50 70 90 v s = 3v r bias = 30.9k bw = 2.5mhz bw = 156.25khz bw = 625khz
ltc6603 8 6603fa typical performance characteristics common mode rejection common mode rejection oip3 vs average signal frequency oip3 vs average signal frequency oip3 vs average signal frequency common mode rejection ratio common mode rejection ratio common mode rejection frequency (hz) cmrr (db) 6603 g16 110 100 90 80 70 60 50 30 40 20 10k 1m 10m 100k v s = 3v, r bias = 30.9k lpf1 = 0, lpf0 = 1, bw = 625khz, t a = 25c gain = 0db gain = 24db gain = 12db gain = 6db frequency (hz) cmrr (db) 6603 g17 120 110 100 90 80 70 60 40 50 30 1k 100k 1m 10k v s = 3v, r bias = 30.9k lpf1 = lpf0 = 0, bw = 156.25khz, t a = 25c gain = 0db gain = 24db gain = 12db gain = 6db frequency (hz) common mode rejection (db) 6603 g18 100 90 80 70 60 50 40 30 10k 1m 10m 100k v s = 3v, r bias = 30.9k lpf1 = 1, bw = 2.5mhz, t a = 25c gain = 0db gain = 24db cmr = v in-cm / v out-diff gain = 12db gain = 6db frequency (hz) common mode rejection (db) 6603 g19 110 100 90 80 70 60 50 10k 1m 10m 100k v s = 3v, r bias = 30.9k lpf1 = 0, lpf1 = 1, bw = 625khz, t a = 25c gain = 0db gain = 24db cmr = v in-cm / v out-diff gain = 12db gain = 6db frequency (hz) common mode rejection (db) 6603 g20 100 90 80 70 60 50 1k 100k 1m 10k cmr = v in-cm / v out-diff v s = 3v, r bias = 30.9k lpf1 = lpf0 = 0, bw = 156.25khz, t a = 25c gain = 0db gain = 24db gain = 12db gain = 6db average frequency of two tones (khz) oip3 (dbm) 6603 g21 41 40 39 38 37 36 35 34 100 2500 500 900 1300 1700 2100 v s = 3v, r bias = 30.9k, t a = 25c lpf1 = 0, lpf0 = 1, bw = 625khz v out = 6dbm per tone for 2-tone test f = 10khz gain = 0db gain = 24db gain = 12db gain = 6db average frequency of two tones (khz) oip3 (dbm) 6603 g22 46 44 42 40 38 36 0 500 600 100 200 300 400 v s = 3v, r bias = 30.9k, t a = 25c lpf1 = 0, lpf0 = 1, bw = 625khz v out = 6dbm per tone for 2-tone test f = 10khz gain = 0db gain = 24db gain = 12db gain = 6db average frequency of two tones (khz) oip3 (dbm) 6603 g23 43 42 41 40 39 38 36 37 35 20 140 160 60 40 80 100 120 v s = 3v, r bias = 30.9k, t a = 25c lpf1 = 0, lpf0 = 1, bw = 156.25khz v out = 6dbm per tone for 2-tone test f = 10khz gain = 0db gain = 24db gain = 12db gain = 6db common mode rejection ratio frequency (hz) cmrr (db) 6603 g15 100 90 80 70 60 50 30 40 20 10k 1m 10m 100k v s = 3v, r bias = 30.9k lpf1 = 1, bw = 2.5mhz t a = 25c gain = 0db gain = 6db gain = 24db gain = 12db
ltc6603 9 6603fa typical performance characteristics clock output operating at 80mhz r bias pin voltage vs i rbias input referred noise density input referred noise density input referred noise density output impedance vs frequency supply current vs supply voltage supply current vs temperature oip3 vs temperature temperature (c) oip3 (dbm) 6603 g23 42 41 40 39 38 36 37 35 C50 70 90 C10 C30 10 30 50 v s = 3v, r bias = 30.9k passband gain = 24db v out = 6dbm per tone for 2-tone test f = 10khz bw = 625khz, frequency = 200khz bw = 156.25khz, frequency = 60khz bw = 2.5mhz, frequency = 1mhz frequency (hz) output impedance () 6603 g25 10 1 0.1 0.01 0.001 1k 1m 10m 100k 10k lpf1 = 0, lpf0 = 1, bw = 625khz lpf1 = 1, bw = 2.5mhz lpf1 = lpf0 = 0, bw = 156.25khz v s = 3v, r bias = 30.9k, t a = 25c supply voltage (v) 2.7 supply current (ma) 200 80 100 120 140 160 180 60 3.1 3.2 3.3 2.9 6603 g26 3.0 2.8 3.4 3.5 3.6 t a = 25c r bias = 30.9k bw = 2.5mhz bw = 156.25khz bw = 625khz temperature (c) C50 supply current (ma) 180 80 100 120 140 160 60 30 50 70 C10 6603 g27 10 C30 90 t a = 25c r bias = 30.9k bw = 2.5mhz bw = 156.25khz bw = 625khz time (ns) C14 voltage (v) 5 0 1 2 3 4 C2 C1 C6 C4 C2 0 C10 6603 g28 C8 C12 2 r bias = 30.9k, v s = 3v t a = 25c i rbias (a) 0 r bias pin voltage (v) 1.25 1.15 1.20 1.10 10 15 20 5 6603 g29 25 t a = 25c v s = 3v frequency (hz) voltage noise density (nv/ hz ) 6603 g30 1000 100 1 10 0.1 10k 1m 10m 100k v s = 3v, r bias = 30.9k lpf1 = 1, bw = 2.5mhz t a = 25c gain = 0db gain = 6db gain = 12db gain = 24db frequency (hz) voltage noise density (nv/ hz ) 6603 g31 1000 100 10 1 10k 1m 10m 100k v s = 3v, r bias = 30.9k lpf1 = 0, lpf0 = 1, bw = 625khz t a = 25c gain = 0db gain = 6db gain = 12db gain = 24db frequency (hz) voltage noise density (nv/ hz ) 6603 g32 1000 100 10 1 1k 100k 1m 10k v s = 3v, r bias = 30.9k lpf1 = 0, lpf0 = 0, bw = 156.25khz t a = 25c gain = 0db gain = 6db gain = 12db gain = 24db
ltc6603 10 6603fa v+ in (pin 1): input voltage supply (2.7v v 5.5v). this supply must be kept free from noise and ripple. it should be bypassed directly to a ground plane with a 0.1f ca- pacitor unless it is tied to v+ a (pin 2). the bypass should be as close as possible to the ic, but is not as critical as the bypassing of v+ a and v+ d (pin16). v+ a (pin 2): analog voltage supply (2.7v v 3.6v). this supply must be kept free from noise and ripple. it should be bypassed directly to a ground plane with a 0.1f capacitor. the bypass should be as close as possible to the ic. v ocm (pin 3): output common mode voltage reference. if ? oated, an internal resistive divider sets the voltage on this pin to half the supply voltage (typically 1.5v), maximizing the dynamic range of the ? lter. if this pin is ? oated, it must be bypassed with a quality 1f capacitor to ground. this pin has a typical input impedance of 3.4k and may be overdriven. driving this pin to a voltage other than the default value will reduce the signal range the ? lter can handle before clipping. r bias (pin 4): oscillator frequency-setting resistor input. the value of the resistor connected between this pin and ground determines the frequency of the master oscillator, and sets the bias currents for the ? lter networks. the voltage on this pin is held by the ltc6603 to approximately 1.17v. for best performance, use a precision metal ? lm resis- tor with a value between 30.9k and 200k and limit the capacitance on this pin to less than 10pf. this resistor is necessary even if an external clock is used. clkcntl (pin 5): clock control input. this three-state input selects the function of clkio (pin 15). tying the clkcntl pin to ground allows the clkio pin to be driven by an external clock (clkio is the master clock input). if the clkcntl pin is ? oated, the internal oscillator is enabled, but the master clock is not present at the clkio pin (clkio is a no-connect). if the clkcntl pin is tied to v+ d (pin 16), the internal oscillator is enabled and the master clock is present at the clkio pin (clkio is the master clock output). to detect a ? oating clkcntl pin, the ltc6603 attempts to pull the pin toward mid-supply. this is realized with two internal 15a current sources, one tied to v+ d and clkcntl and the other one tied to ground and clkcntl. therefore, driving the clkcntl pin high requires sourcing approximately 15a. likewise, driving the clkcntl pin low requires sinking 15a. when the clkcntl pin is ? oated, it should be bypassed by a 1nf capacitor to ground or be surrounded by a ground shield to prevent excessive coupling from other pcb traces. typical performance characteristics integral input referred noise integral input referred noise pin functions integration bw (hz) voltage noise (v) 6603 g34 1000 100 10 1 10k 1m 10m 100k v s = 3v, r bias = 30.9k lpf1 = 0, lpf0 = 1, bw = 625khz t a = 25c gain = 0db gain = 6db gain = 12db gain = 24db integration bw (hz) voltage noise (v) 6603 g35 1000 100 10 1 10k 100k 1m v s = 3v, r bias = 30.9k lpf1 = lpf0 = 0, bw = 156.25khz t a = 25c gain = 24db gain = 12db gain = 0db gain = 6db integral input referred noise integration bw (hz) voltage noise (v) 6603 g33 1000 100 10 1 10k 1m 10m 100k v s = 3v, r bias = 30.9k lpf1 = 1,bw = 2.5mhz t a = 25c gain = 0db gain = 6db gain = 12db gain = 24db
ltc6603 11 6603fa pin functions lpf1( cs ) (pin 6): ttl level input. when in pin program- mable control mode, this pin is the msb of the lowpass cutoff frequency control code; in serial control mode, this pin is the chip select input (active low). +inb, Cinb (pins 7, 8): channel b differential inputs. the input range and input resistance are described in the applications information section. input voltages which exceed v+ in (pin 1) should be avoided. lpf0 (sclk) (pin 9): ttl level input. when in pin pro- grammable control mode, this pin is the lsb of the lowpass cutoff frequency control code; in serial control mode, this pin is the clock of the serial interface. sdi (pin 10): ttl level input. when in pin programmable control mode, this pin is left ? oating; in serial control mode, this pin is the serial data input. sdo (pin 11): ttl level input. when in pin programmable control mode, this pin is left ? oating; in serial control mode, this pin is the serial data output. Coutb, +outb (pins 12, 13): channel b differential filter outputs. these pins can drive 1k and/or 50pf loads. for larger capacitive loads, an external 100 series resistor is recommended for each output. the common mode voltage of the ? lter outputs is the same as the voltage at v ocm (pin 3). gnd (pin 14): ground. should be tied to a ground plane for best performance. clkio (pin 15): when clkcntl (pin 5) is tied to ground, clkio is the master clock input. when clkcntl is ? oated, clkio is pulled to ground by a weak pulldown. when clkcntl is tied to v+ d (pin 16), clkio is the master clock output. when con? gured as a clock output, this pin can drive 1k and/or 5pf loads (heavier loads will cause inaccuracies). v+ d (pin 16): digital voltage supply (2.7v v 3.6v). this supply must be kept free from noise and ripple. it should be bypassed directly to a ground plane with a 0.1f capacitor. the bypass should be as close as possible to the ic. ser (pin 17): interface selection input. when tied to v+ d (pin 16) or ? oated, the interface is in pin programmable control mode, i.e. the ? lter gain and cutoff frequencies are programmed by the gain1, gain0, lpf1 and lpf0 pins. when ser is tied to ground, the ? lter gain, the ? lter cutoff frequency and shutdown mode are programmed by the serial interface. Couta, +outa (pins 18, 19): channel a differential filter outputs. these pins can drive 1k and/or 50pf loads. for larger capacitive loads, an external 100 series resistor is recommended for each output. the common mode voltage of the ? lter outputs is the same as the voltage at v ocm (pin 3). cap (pin 20): connect a 0.1f bypass capacitor to this pin. pin 20 is a buffered version of pin 3. gain0(d0) (pin 21): ttl level input. when in pin pro- grammable control mode, this pin is the lsb of the gain control code; in serial control mode, this pin is the lsb of the serial control register, an output. gain1 (pin 22): ttl level input. when in pin programmable control mode, this pin is the msb of the gain control code; in serial control mode, this pin is a no-connect. Cina, +ina (pins 23, 24): channel a differential inputs. the input range and input resistance are described in the applications information section. input voltages which exceed v+ in (pin 1) should be avoided. exposed pad (pin 25): ground. the exposed pad must be soldered to pcb.
ltc6603 12 6603fa block diagram timing diagram of the serial interface 2 v+ a gnd v+ a 1 v+ in r bias 4 v ocm 3 clkcntl lpf1( cs ) 5 6 17 18 15 16 14 13 6603 bd 20 19 22 21 23 24 11 12 9 10 8 7 Cinb +inb sdi lpf0(sclk) sdo Coutb Cina +ina gain0(d0) gain1 cap +outa ser Couta clkio v+ d gnd +outb gain lpf gain lpf control bias clk control bias clk bias/osc clock generator control logic channel a channel b to pin 20 d3 d3 d2 d1 d0 d7 ? ? ? ? d4 d3 d3 d4 d2 d1 d0 d7 ? ? ? ? d4 t 6 t 9 t 7 t 3 t 5 t 4 t 1 t 8 t 2 previous byte current byte sclk sdi cs sdo 6603 td timing diagram
ltc6603 13 6603fa applications information theory of operation (refer to block diagram) the ltc6603 features two matched ? lter channels, each containing gain control and lowpass ? lter networks that are controlled by a single control block and clocked by a single clock generator. the gain and cutoff frequency can be separately programmed. the two channels are not independent, i.e. if the gain is set to 24db then both channels have a gain of 24db. the ? lter can be clocked with an external clock source, or using the internal oscil- lator. a resistor connected to the r bias pin sets the bias currents for the ? lter networks and the internal oscillator frequency (unless driven by an external clock). altering the clock frequency changes the ? lter bandwidth. this allows the ? lters to be tuned to many different bandwidths. pin programmable interface as shown in figure 1, connecting ser to v+ d allows the ? lter to be directly controlled through the pin program- mable control lines gain1, gain0, lpf1 and lpf0. the gain0(d0) pin is bidirectional (input in pin programmable control mode, output in serial mode). in pin programmable control mode, the voltage at gain0(d0) cannot exceed v+ d ; otherwise, large currents can be injected to v+ d through the parasitic diodes (see figure 2). connecting a 10k resistor at the gain0(d0) pin (see figure 1) is recommended for current limiting, to less than 10ma. ser has an internal figure 1. filter in pin programmable control mode pull-up to v+ d . none of the logic inputs have an internal pull-up or pull-down. serial interface connecting ser to ground allows the ? lter to be controlled through the spi serial interface. when cs is low, the serial data on sdi is shifted into an 8-bit shift register on the rising edge of the clock (sclk), with the msb transferred ? rst (see figure 3). serial data on sdo is shifted out on the clocks falling edge. a high cs will load the 8 bits of the shift register into an 8-bit d-latch, which is the serial control register. the clock is disabled internally when cs is pulled high. note: sclk must be low before cs is pulled low to avoid an extra internal clock pulse. sdo is always active in serial mode (never tri-stated) and cannot be wire-ored to other spi outputs. in addition, sdo is not forced to zero when cs is pulled high. an ltc6603 may be daisy-chained with other ltc6603s or other devices having serial interfaces. daisy chain- ing is accomplished by connecting the sdo of the lead chip to the sdi of the next chip, while sclk and cs remain common to all chips in the daisy chain. the se- rial data is clocked to all the chips then the cs signal is pulled high to update all of them simultaneously. figure 4 shows an example of two ltc6603s in a daisy- chained spi con? guration. v + in v + a v + d +ina Cina ser lpf1( cs ) lpf0(sclk) gain1 gain0(d0) gnd ltc6603 v out v in 0.1f lowpass cutoff = 2.5mhz (f clk = 80mhz) gain = 4 gain, bandwidths are set by microprocessor. 10k resistors on gain0(out) protects the device when v gain0 > v+ d p + C + C + C + C 10k 6603 f01 +outa Couta v + in v + a v + d +ina Cina ser lpf1( cs ) lpf0(sclk) gain1 gain0(d0) gnd v out v in +outa Couta 3.3v 0.1f 3.3v ltc6603 lpf1 lpf0 gain1 gain0
ltc6603 14 6603fa applications information figure 2. bidirectional design of gain0(out) pin figure 3. diagram of serial interface (msb first out) figure 4. two devices in a daisy chain v+ d gain0(d0) 6603 f02 (internal node) 4-bit gain, bw control code no function 8-bit latch q0 q1 q2 q3 q4 q5 q6 q7 8-bit shift-register sdo sclk sdi cs 6603 f03 out shutdown p 6603 f04 csx sclk sdi sclk sdi cs d15 d11 d10 d9 d8 d7 d3 d2 d1 d0 gain, bw control word for #2 gain, bw control word for #1 shutdown for #1 shutdown for #2 v + in v + a v + d +ina Cina ser lpf1( cs ) lpf0(sclk) sdi gnd ltc6603 #1 v out1 v in1 0.1f + C + C + C + C v in2 3.3v +outa Couta out1 v + in v + a v + d +ina Cina ser lpf1( cs ) lpf0(sclk) sdi gnd ltc6603 #2 v out2 0.1f 3.3v +outa Couta out2 gain0(d0) sdo gain0(d0) sdo sdo serial control register de? nition d7 d6 d5 d4 d3 d2 d1 d0 gain0 gain1 lpf0 lpf1 no function no function shdn out
ltc6603 15 6603fa applications information gain1 and gain0 are the gain control bits (register bits d6 and d7 when in serial mode). their function is shown in table 1. in serial mode, register bit d1 can be set to 1 to put the device into a low power shutdown mode. reg- ister bit d0 is a general purpose output (pin 21) when in serial mode. table 1. gain control gain 1 gain 0 passband gain (db) 000 016 1012 1124 self-clocking operation the ltc6603 features a unique internal oscillator which sets the ? lter cutoff frequency using a single external resistor connected to the r bias pin. the clock frequency is deter- mined by the following simple formula (see figure 5): f clk = 247.2mhz ? 10k/r bias note: r bias 200k the design is optimized for v+ a , v+ d = 3v, f clk = 45mhz, where the ? lter cutoff frequency error is typically <3% when a 0.1% external 54.9k resistor is used (any resis- tor (r bias ) tolerance, will shift the clock frequency). with different resistor values and cutoff frequency control set- tings (lpf1 and lpf0), the lowpass cutoff frequency can figure 5. r bias vs desired clock frequency be accurately varied from 24.14khz to 2.5mhz. table 2 summarizes the cutoff frequencies that can be obtained with an external resistor (r bias ) value of 30.9k. note that the cutoff frequencies scale with the clock frequency. for example, if lpf1 and lpf0 are both equal to zero, and r bias is increased from 30.9k to 200k, f clk will decrease from 80mhz to 12.36mhz and the cutoff frequency will be reduced from 156.25khz to 24.14khz. the cutoff frequencies that can be obtained with external resistor values of 54.9k and 200k are shown in table 3 and table 4, respectively. when the ltc6603 is programmed for the cutoff frequencies lower than the maximum, the power is automatically reduced. the power savings at the middle bandwidth setting (lpf1 = 0, lpf0 = 1), is about 23%, while the power savings at the lowest bandwidth setting (lpf1 = 0, lpf0 = 0) is about 60%. table 2. cutoff frequency control, r bias = 30.9k, f clk = 80mhz lpf1 lpf0 lowpass bw(khz) 0 0 156.25 0 1 625 1 0 2500 1 1 2500 table 3. cutoff frequency control, r bias = 54.9k, f clk = 45mhz lpf1 lpf0 lowpass bw(khz) 0 0 87.94 0 1 351.78 1 0 1407 1 1 1407 table 4. cutoff frequency control, r bias = 200k, f clk = 12.36mhz lpf1 lpf0 lowpass bw(khz) 0 0 24.14 0 1 96.56 1 0 386.25 1 1 386.25 desired clock frequency (mhz) r bias (k) 6603 f05 200 175 75 50 100 125 150 25 10 80 20 30 40 50 60 70
ltc6603 16 6603fa applications information the following graphs show a few of the possible lowpass ? lters. gain and group delay vs frequency (2.5mhz lowpass response) gain and group delay vs frequency (650khz lowpass response) the oscillator is sensitive to transients on the positive supply. the ic should be soldered to the pc board and the pcb layout should include a 0.1f ceramic capacitor between v+ a (pin 2) and ground, as close as possible to the ic to minimize inductance. the pcb layout should also include an additional 0.1f ceramic capacitor between v+ d (pin 16) and ground. avoid parasitic capacitance on r bias (pin 4) and avoid routing noisy signals near r bias . use a ground plane connected to pin 14 and the exposed pad (pin 25). frequency (hz) gain (db) group delay (s) 6603 g17 0 C20 C100 C80 C60 C40 C120 1.2 1.0 0.2 0.4 0.6 0.8 0 100k 10m 1m gain group delay frequency (hz) gain (db) group delay (s) 6603 g18 0 C60 C40 C20 C80 1 2 3 4 0 100k 1m gain group delay alternative methods of setting the clock frequency of the ltc6603 the oscillator may be programmed by any method that sinks a current out of the r bias pin. the circuit in figure 6 sets the clock frequency by using a programmable current source and in the expression for f clk , the resistor r bias is replaced by the ratio of 1.17v/i control . because the voltage of the r bias pin is approximately 1.17v 5%, the figure 6 circuit is less accurate than if a resistor controls the clock frequency. in this circuit, the ltc2621 (a 12-bit dac) is daisy-chained with the ltc6603. because the sinking current from the r bias pin is: v rbias ?k 2 n ?r1 the equivalent r bias is: 2 n ?r1 k , where k is the binary dac input code and n is the resolu- tion. figure 7 shows some of the frequency responses that can be obtained using this circuit. figure 8 shows the ltc6603s oscillator con? gured as a vco. a voltage source is connected in series with the r bias resistor. the clock frequency, f clk , will vary with v control . again, this circuit decouples the relationship between the current out of the r bias pin and the voltage of the r bias pin; the frequency accuracy will be degraded. the clock frequency, however, will increase monotonically with decreasing v control . operation using an external clock the ltc6603 may be clocked by an external oscillator for tighter bandwidth control by pulling clkcntl (pin 5) to ground and driving a clock into clkio (pin 15). if an external clock is used, the r bias resistor is still necessary. the value of r bias must be no larger than the value that would be required for using the internal oscillator. for example, a 100k resistor would program the internal oscil- lator for 24.705mhz, so an external oscillator frequency of 24.705mhz would require an r bias resistance of no more
ltc6603 17 6603fa applications information figure 6. current controlled clock frequency figure 8. voltage controlled clock frequency 6603 f06 v+ in v+ a v ocm r bias clkcntl lpf1( cs ) +inb Cinb lpf0(sclk) sdi sdo Coutb +ina Cina gain1 gain0(d0) v ocm cap +outa Couta ser v+ d clk io gnd +outb ltc6603 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 c1 100nf c2 2.2f c4 100nf c3 2.2f c19 50pf c18 50pf c15 10nf +outa Couta +outb Coutb r23 50k r24 50k Cinb +inb r25 50k r26 50k +ina Cina c17 50pf c16 50pf Cin +in 5v 7 out Cin +in out r1 30.5k 5v c7 100nf v+ vC 2 3 sdo sdi sck clr cs /ld ldac 5v c8 100nf r4 100k 5v 7 1 2 3 4 5 10 c9 1f v out v ref v cc gnd ltc2621-1 sdi sclk cs 5v 3v i range = 6a to 38.4a use narrow short traces for minimum capacitance. q1 rk7002at116ct 2 1 ltc6078 ltc6078 clr low will set dac to mid-scale (with a ltc6603-1 version). has ~100ms tc at start-up to reset to zero-scale. data format data is shifted from mosi (master out, slave in) thru ltc6603 into the ltc2621. the total packet is 32 bits. it starts with a control byte (0011 xxxx) then msb of the dac, with dummy bits at the end, 16 bits (24 bits total). then 8 bits to the filter. d6 and d7 = gain, d4 and d5 = lpf, d1 = shdn. d0 = gen. purpose output. spi interface v ocm v+ vC v+ v+ in r bias 6603 f08 v control f clk = 247.2mhz ? (10k/r bias ) ? (1 C v control /1.17v) r bias + C frequency (hz) gain (db) 6603 f07 10 0 C10 C20 C30 C40 C50 C60 C70 C80 1k 1m 10m 100k 10k v s = 3v t a = 25c figure 7. frequency response controlled by ltc2621-1
ltc6603 18 6603fa applications information than 100k. if the value of r bias is too large, the ? lters will not receive a large enough bias current, possibly causing errors due to insuf? cient settling. be sure to obey the absolute maximum speci? cations when driving a clock into clkio (pin 15). input common mode and differential voltage range the input signal range extends from zero to the v+ in supply voltage. this input supply can be tied to v+ a and v+ d , or driven up to 5.5v for increased input signal range. figure 9 shows the distortion of the ? lter versus common mode input voltage with a 2v p-p differential input signal (v+ in = 5v). control bits lpf1 and lpf0. the differential input imped- ance is a function of the clock frequency and the control bits lpf1, lpf0, gain1 and gain0. table 5 shows the typical input impedances for a clock frequency of 80mhz. these input impedances are all proportional to 1/f clk , so if the clock frequency were reduced by half to 40mhz, the impedances would be doubled. the typical variation in dynamic input impedance for a given clock frequency is C20% to +35%. table 5. differential, common mode input impedances, f clk = 80mhz gain1 gain0 lpf1 lpf0 differential input impedance (k ) common mode input impedance (k ) 0000 38 40 0001 16 20 0010 2.5 5 0011 2.5 5 0100 20 40 0101 9.5 20 0 1 1 0 2.5 5 0 1 1 1 2.5 5 1 0 0 0 10 40 1 0 0 1 5.4 20 1010 1.9 5 1011 1.9 5 1 1 0 0 5.2 40 1 1 0 1 2.8 20 1110 1.6 5 1111 1.6 5 output common mode and differential voltage range the output voltage is a fully differential signal with a common mode level equal to the voltage at v ocm . any of the ? lter outputs may be used as single-ended outputs, although this will degrade the performance. the output voltage range is typically 0.5v to v+ a C 0.5v (v+ a = 2.7v to 3.6v). the common mode output voltage can be adjusted by overdriving the voltage present on v ocm . to maximize the undistorted peak-to-peak signal swing of the ? lter, the v ocm voltage should be set to v+ a /2. note that the output common mode voltages of the two channels are figure 9. distortion vs common mode input voltage (5v) common mode input voltage (v) 1.0 distortion (dbc) C60 C70 C80 C90 3.0 2.0 4.0 6603 f09 5.0 2.5 4.5 1.5 3.5 r bias = 30.9k, v s = 3v, v+ in = 5.5v lpf1 = 1, bw = 2.5mhz, gain = 24db v out = v p-p , t a = 25c hd3, f = 1mhz hd3, f = 200khz for best performance, the inputs should be driven dif- ferentially. for single-ended signals, connect the unused input to v ocm (pin 3) or to a quiet dc reference voltage. to achieve the best distortion performance, the input signal should be centered around the dc voltage of the unused input. refer to the typical performance characteristics section to estimate the distortion for a given input level. dynamic input impedance the unique input sampling structure of the ltc6603 has a dynamic input impedance which depends on the con? guration and the clock frequency. this dynamic input impedance has both a differential component and a common mode component. the common mode input impedance is a function of the clock frequency and the
ltc6603 19 6603fa applications information not independent as they are both set by the v ocm pin. figure 10 illustrates the distortion versus output common mode voltage for a 2v p-p differential input voltage and a common mode input voltage that is equal to mid-supply. figure 10. distortion vs common mode output voltage connecting resistors between each input and v+ in will pull the input common mode voltage up, increasing the input signal swing. the resistance, r pull-up , necessary to set the input common mode voltage, v icm , to any desired level can be calculated by r pull up = r cm v supply v ic m 1 where r cm = 40k?80mhz/f clk for lpf1=0, lpf0=0 r cm = 20k?80mhz/f clk for lpf1=0, lpf0=1 r cm = 5k?80mhz/f clk for lpf1=1 for example, if the lowpass cutoff frequency is set to 2.5mhz, 5k resistors connected between each input and v+ in will set the input common mode voltage to mid- supply. circuit a of figure 12 is for a ? xed clk and lpf0, lpf1 setting. if the clock varies or the lpf0, lpf1 setting changes then circuit b of figure 12 should be used. due to the sampled data nature of the ? lter, an anti-aliasing ? lter at the inputs is recommended. the output common mode voltage is equal to the voltage of the v ocm pin. the v ocm pin is biased to one-half of the supply voltage by an internal resistive divider (see block diagram). to alter the common mode output volt- age, v ocm can be driven with an external voltage source or resistor network. if external resistors are used, it is important to note that the internal 2k resistors can vary 30% (their ratio varies only 1%). the ? lter outputs can also be ac-coupled. the ltc6603 can be interfaced to an a/d converter by pull- ing clkcntl (pin 5) to v+ d . this con? gures clkio (pin 15) as a clock output, which can be used to drive the clock input of the a/d converter. this allows the a/d converter to be synchronized with the ? lter sampling clock, avoiding beat frequencies and simplifying the board layout. any routing attached to the clkio pin should be as short as possible, in order to minimize re? ections. similarly, the ltc6603 can be interfaced to another ltc6603 in a master/slave con? guration as shown in figure 13. this common mode output voltage (v) 0.8 distortion (dbc) C60 C70 C65 C75 C80 1.0 1.4 6603 f10 1.8 1.6 1.2 r bias = 30.9k, v s = 3v, gain = 24db, t a = 25c signal frequency = 200khz hd3, lpf1 = 0, lpf0 = 1 hd3, lpf1 = 1 hd2, lpf1 = 0, lpf0 = 1 hd2, lpf1 = 1 interfacing to the ltc6603 the input and output common mode voltages of the ltc6603 are independent. the input common mode voltage is set by the signal source if dc-coupled, as shown in figure 11. if the inputs are ac-coupled, as shown in figure 12 (circuit a), the input common mode voltage will be pulled to ground by an equivalent resistance of r cm , shown in table 5. this does not affect the ? lters performance as long as the input amplitude is less than 0.5v p-p . at low ? lter gain settings, a larger input voltage swing may be desired. figure 11. dc-coupled inputs v + in v + a v + d +ina Cina v ocm gnd ltc6603 0.1f dc-coupled input v in (common mode) = (v in + + v in C)/2 v out (common mode) = (v out + + v out C)/2 = v supply /2 6603 f11 +outa Couta v supply + C + C 1f v out + v out C v in + v in C
ltc6603 20 6603fa applications information figure 12. ac-coupled inputs figure 13. two devices in a master/slave clocking con? guration ac-coupled input v in (common mode) = v out (common mode) = v supply /2 6603 f12 v supply + C + C 0.1f 0.1f r pull-up r pull-up v + in v + a v + d +ina Cina v ocm gnd ltc6603 v out + v out C 0.1f +outa Couta v supply 1f v in + v in C ac-coupled input v in (common mode) = v supply + C + C 0.1f 0.1f 1.87k 1.87k 1.87k 1.87k v + in v + a v + d +ina Cina v ocm gnd ltc6603 v out + v out C 0.1f +outa Couta v+ a 1f v in + v in C circuit a circuit b 0.1f v+ in r cm ?v in 2?r cm 1.87k v + in v + a v + d +ina Cina clkcntl clkio gnd ltc6603 master v out1 v in1 0.1f + C + C + C + C 6603 f13 +outa Couta 3.3v ltc6603 slave v out2 v in2 0.1f +outa Couta 3.3v v + in v + a v + d +ina Cina clkcntl clkio gnd
ltc6603 21 6603fa applications information results in four matched ? lter channels, all synchronized to the same clock. the master has its clkcntl pin pulled to v+ d , con? guring its clkio pin as an output, while the slave has its clkcntl pin pulled to ground, con? guring its clkio pin as an input. note that in order to synchronize the two ? lters, the clock frequency must not be buffered. this requires that the ? lters be close together on the pc board. if the clock is buffered, the ? lters would have matching bandwidths, but would not be synchronized. output drive the ? lter outputs can drive 1k and/or 50pf loads connected to ac ground with a 0.5v to 2.5v signal (corresponding to a 4v p-p differential signal). for differential loads (loads connected between +outa and Couta or +outb and Coutb) the outputs can produce a 4v p-p signal across 2k and/or 25pf. for smaller signal amplitudes, the outputs can drive correspondingly larger loads. for larger capacitive loads, an external 50 series resistor is recommended for each output. clock feedthrough clock feedthrough is de? ned as the rms value of the clock frequency and its harmonics that are present at the ? lters output. the clock feedthrough is measured with +ina and Cina (or +inb, Cinb) tied to v ocm and depends on the pc board layout and the power supply decoupling. the clock feedthrough can be reduced with a simple rc post ? lter. decoupling capacitors the ltc6603 uses sampling techniques, therefore its performance is sensitive to supply noise. 0.1f ceramic decoupling capacitors must be connected from v+ a (pin 2) and v+ d (pin 16) to ground with leads as short as possible. a ground plane should be used. noisy signals should be isolated from the ? lters input pins. in addition, a 0.1f decoupling capacitor at pin 20 is recommended since this pin receives clocked current injection. aliasing aliasing is an inherent phenomenon of sampled data ? lters. signi? cant aliasing only occurs when the frequency of the input signal approaches the sampling frequency or multiples of the sampling frequency. the ratio of the ltc6603 input sampling frequency to the clock frequency, f clk , is determined by the state of control bits lpf1 and lpf0. table 6 shows the possible input sampling frequen- cies for a clock frequency of 80mhz. the input sampling frequency is proportional to the clock frequency. for example, if the clock frequency is lowered from 80mhz to 40mhz, the input sampling frequency will be lowered by half. input signals with frequencies near the input sampling frequency will be aliased to the passband of the ? lter and appear at the output unattenuated. table 6. input sampling frequency (f clk = 80mhz) lpf1 lpf0 input sampling frequency (mhz) 00 20 01 40 1 0 160 1 1 160 a simple lc anti-aliasing ? lter is recommended at the ? lter inputs to attenuate frequencies near the input sam- pling frequency that will be aliased to the passband. for example, if the clock frequency is set to 80mhz and the cutoff frequency of the ? lter is set to its maximum (lpf1 = 1), the lowest frequency that would be aliased to the passband would be f clk C f cutoff , i.e., 160mhz C 2.5mhz = 157.5mhz. the ltc6603 ? lter inputs should be driven by a low impedance output (<100). wideband noise the wideband noise of the ? lter is the rms value of the devices output noise spectral density. the wideband noise is nearly independent of the value of the clock frequency and excludes the clock feedthrough. most of the wideband noise is concentrated in the ? lter passband and cannot be removed with post ? ltering. power supply current the power supply current depends on the state of the lowpass cutoff frequency controls (lpf1, lpf0) and the value of r bias . when the ltc6603 is programmed for the middle cutoff frequency (lpf1 = 0, lpf0 = 1), the supply current is reduced by about 23% relative to the supply current for the higher bandwidth setting. programming
ltc6603 22 6603fa applications information the ltc6603 for the lowest cutoff frequency (lpf1 = 0, lfp0 = 0) reduces the supply current by about 60%. power supply current vs. cutoff frequency for various bandwidth settings is shown in the typical performance characteris- ticst section. the ltc6603 can be programmed through the serial interface to enter into a low power shutdown mode. the power supply current during shutdown is less than 235a. supply current vs noise trade-off the passband of the ltc6603 is determined by the master clock frequency (which is set by r bias when the internal oscillator is used), lpf1 and lpf0. the ltc6603 is op- timized for use with r bias having a value between 200k and 30.9k to set the internal oscillation frequency from 12.36mhz to 80mhz. the lowpass corner frequency is proportional to the clock frequency (internal or external). figure 14. f clk vs filter cutoff frequencies figure 15. supply current vs filter cutoff frequency table 7. total input referred integrated noise voltage (passband gain = 24db) lpf1 lpf0 noise voltage 0 0 C81dbm 0 1 C80dbm 1 x C76dbm to extend the ? lters operational frequency range, the master clock is divided down before reaching the ? lter. lpf1 and lpf0 set the division ratio of the lowpass clock. figure 14 shows the possible cutoff frequencies versus f clk , lpf1 and lpf0. overlapping frequency ranges allow more than one possible choice of bandwidth settings for some cutoff frequencies. figure 15 shows supply current as a function of the ? lter cutoff frequency, lpf1 and lpf0. note that the higher bandwidth setting always gives the minimum supply current for a given cutoff frequency. the input referred integrated noise voltage for a passband gain of 24db is shown in table 7. note that the noise is higher for the higher bandwidth settings. this creates a tradeoff between supply current and noise. for a given cutoff frequency, using the highest possible bandwidth setting gives the minimum supply current at the expense of higher noise. filter cutoff frequency (hz) f clk (mhz) 6603 f14 100 10 10k 1m 10m 100k lpf1 = 1 lpf1 = 0 lpf0 = 1 lpf1 = 0 lpf0 = 0 filter cutoff frequency (hz) supply current (ma) 6603 f15 180 160 140 120 100 80 60 40 20 0 10k 1m 10m 100k lpf1 = 1 lpf1 = 0 lpf0 = 1 lpf1 = 0 lpf0 = 0 t a = 25c v s = 3v clkcntl pin floating gain = 0db
ltc6603 23 6603fa information furnished by linear technology corporation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no representa- tion that the interconnection of its circuits as described herein will not infringe on existing patent rights. typical applications uf package 24-lead plastic qfn (4mm 4mm) (reference ltc dwg # 05-08-1697) ltc6603 parallel clock control ltc6603 spi clock control 4.00 0.10 (4 sides) note: 1. drawing proposed to be made a jedec package outline mo-220 variation (wggd-x)to be approved 2. drawing not to scale 3. all dimensions are in millimeters 4. dimensions of exposed pad on bottom of package do not include mold flash. mold flash, if present, shall not exceed 0.15mm on any side, if present 5. exposed pad shall be solder plated 6. shaded area is only a reference for pin 1 location on the top and bottom of package pin 1 top mark (note 6) 0.40 0.10 24 23 1 2 bottom viewexposed pad 2.45 0.10 (4-sides) 0.75 0.05 r = 0.115 typ 0.25 0.05 0.50 bsc 0.200 ref 0.00 C 0.05 (uf24) qfn 0105 recommended solder pad pitch and dimensions 0.70 0.05 0.25 0.05 0.50 bsc 2.45 0.05 (4 sides) 3.10 0.05 4.50 0.05 package outline pin 1 notch r = 0.20 typ or 0.35 45 chamfer 6603 ta02 +ina v+ in v+ a v+ d Cina +inb Cinb cap gain1 gain0(d0) gnd gnd r bias v ocm +outa Couta +outb Coutb clkcntl sdo sdi lpf0(sclk) lpf1( cs ) clkio ser ltc6603 0. 1 3v 1216 3v 0.1f 0.1f 24 23 20 22 21 25 14 7 8 4 3 19 18 5 11 10 6 9 13 12 15 17 r3 r1 v ocm r2 diodes inc dmn2004dwk clk1 clk1 clk0 0 0 r bias1 f clk1 0 1 r bias2 f clk2 1 0 r bias3 f clk3 1 1 r bias4 f clk4 r bias1 > r bias2 or r bias3 r bias = r bias in k f clk in mhz r1 = r bias1 r2 = r3 = r bias4 = clk0 lpf1 lpf0 gain1 gain0 2472 f clk design procedure 1. choose f clk1 , f clk2 and f clk3 2. calculate r bias1 , r bias2 and r bias3 3. calculate r2, r3 and r bias4 r bias1 ? r bias2 r bias1 C r bias2 r bias1 ? r bias3 r bias1 C r bias3 r1 ? r2 ? r3 r1 ? (r2 + r3) + r2 ? r3 6603 ta03 +ina v+ in v+ a v+ d Cina +inb Cinb cap gain1 gain0(d0) gnd gnd r bias v ocm +outa Couta +outb Coutb clkcntl sdo sdi lpf0(sclk) lpf1( cs ) clkio ser ltc6603 0.1f 3v 1216 3v 0.1f 0.1f 24 23 20 22 21 25 14 7 8 4 3 19 18 5 11 10 6 9 13 12 15 17 cs sclk sdi v out gnd v+ 0.1f 3v 4 5 6 3 2 1 r1 v b v c r2 cs1 cs2 sck sdi ltc2630 8-bit dac if r1 = 51.1k and r2 = 78.7k then the f clk range is 12.36mhz to 80mhz dac v out range 0v to 2.5v (using the ltc2630 internal reference) r1 = v c range 0v to 2.5v, v b = 1.17v if v c = 0v then f clk = f clkhi if v c = 2.5v then f clk = f clklo 5.282 ? 10 12 1.137f clkhi + f clklo , r2 = 5.282 ? 10 12 f clkhi C f clklo f clk = 2.472 ? 10 12 r1 + r2 r1? r2 v c v b ?r2 package description
ltc6603 24 6603fa linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7417 (408) 432-1900 fax: (408) 434-0507 www.linear.com ? linear technology corporation 2008 lt 0709 rev a ? printed in usa related parts typical application part number description comments lt c ? 1565-31 650khz linear phase lowpass filter continuous time, so8 package, fully differential ltc1566-1 low noise, 2.3mhz lowpass filter continuous time, so8 package ltc1567 very low noise, high frequency filter building block 1.4nv/ hz op amp, msop package, differential outputs ltc1568 very low noise, 4th order building block lowpass and bandpass filter designs up to 10mhz, differential outputs ltc1569-6 low power 10-pole delay equalized elliptic lowpass f c 64khz, one resistor sets f c , so-8 differential inputs ltc1569-7 10-pole delay equalized elliptic lowpass f c 256khz, one resistor sets f c , so-8 differential inputs lt1994 low distortion, low noise differential ampli? er/adc driver adjustable, low power, v s = 2.375v to 12.6v ltc6406 3ghz low noise, rail-to-rail input differential adc driver low noise: 1.6nv/ hz , low power: 18a lt6600-2.5 very low noise, fully differential ampli? er and 2.5mhz filter 86db s/n with 3v supply, so-8 package lt6600-5 very low noise, fully differential ampli? er and 5mhz filter 82db s/n with 3v supply, so-8 package lt6600-10 very low noise, fully differential ampli? er and 10mhz filter 82db s/n with 3v supply, so-8 package lt6600-15 very low noise, fully differential ampli? er and 15mhz filter 76db s/n with 3v supply, so-8 package lt6600-20 very low noise, fully differential ampli? er and 20mhz filter 76db s/n with 3v supply, so-8 package ltc6601 pin-con? gurable second order filter/driver f c 7mhz to 27mhz fully differential 4mm 4mm qfn package ltc6602 dual baseband bandpass filter for uhf rfid fully differential 4mm 4mm qfn package ltc6604-2.5 dual very low noise, differential amp and 2.5mhz filter 86db s/n with 3v supply, 4mm 7mm qfn package ltc6604-5 dual very low noise, differential amp and 5mhz filter 82db s/n with 3v supply, 4mm 7mm qfn package ltc6604-10 dual very low noise, differential amp and 10mhz filter 82db s/n with 3v supply, 4mm 7mm qfn package ltc6604-15 dual very low noise, differential amp and 15mhz filter 76db s/n with 3v supply, 4mm 7mm qfn package direct conversion demodulator and i and q baseband filter, f cutoff =1.92mhz (utms wcdma) 6603 ta04 +ina v+ in v+ a v+ d Cina +inb Cinb cap gain1 gain0(d0) gnd gnd r bias v ocm +outa Couta +outb Coutb clkcntl sdo sdi lpfo(sclk) lpf1( cs ) clkio ser ltc6603 0.1f 0.1f 100pf 10pf 10pf 100pf 10pf 10pf 49.9 56nh* 49.9 56nh* 49.9 56nh* 49.9 56nh* 5v 3v 1216 3v 3v 0.1f 0.1f 24 23 20 22 21 25 14 7 8 4 3 19 18 5 11 10 6 9 13 12 15 17 40.2k baseband gain control i out q out ltc5575 en v cc v cc v cc i out + i out C q out + q out C gnd gnd gnd rf gnd lo v cc gnd 10pf 10pf 10pf 100pf 10pf 10pf 56nh* 56nh* *coilcraft 0603hp 10pf 100pf 56nh* 56nh* rf in lo in 1000pf 0.1f 1f 5v 4321 9101112 5 6 7 8 16 15 14 13 1000pf gain1 gain0 3.9pf 5.6pf

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