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an important notice at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. production data. DAC8551-Q1 , dac6551-q1 slaseb8c ? february 2016 ? revised november 2016 dacx551-q1 automotive 16-, 12-bit, ultralow-glitch, voltage-output dac 1 1 features 1 ? qualified for automotive applications ? aec-q100 qualified with the following results: ? device temperature grade 1: ? 40 c to 125 c ambient operating temperature range ? device hbm esd classification level 2 ? device cdm esd classification level c4b ? relative accuracy: ? DAC8551-Q1 (16-bit): 4 lsb inl ? dac6551-q1 (12-bit): 0.3 lsb inl ? ultralow glitch impulse: 0.1 nv-s ? settling time: 8 s to 0.003% fsr ? power supply: 3 v to 5.5 v ? power-on reset to zero scale ? micro power operation: 160 a at 5 v ? low-power serial interface with schmitt- triggered inputs ? on-chip output buffer amplifier with rail-to-rail operation ? power-down capability ? binary input ? sync interrupt facility ? available in a tiny vssop-8 package 2 applications ? automotive radar ? automotive sensors 3 description the DAC8551-Q1 and dac6551-q1 are small, low- power, voltage-output, 16- and 12-bit digital-to-analog converters (dacs) qualified for automotive applications. the dacx551-q1 devices provide good linearity and minimize undesired code-to-code transient voltages. the devices use a versatile 3-wire serial interface that operates at clock rates to 30 mhz and is compatible with standard spi, qspi, microwire, and digital signal-processor (dsp) interfaces. the dacx551-q1 devices require an external reference voltage to set the output range. the devices incorporate a power-on-reset circuit that ensures the dac output powers up at 0 v and remains there until a valid write to the device takes place. the devices contain a power-down feature, accessed over the serial interface, that reduces the current consumption to 800 na at 5 v. the dacx551-q1 devices power consumption is only 800 w at 5 v, reducing to less than 4 w in power- down mode. the dacx551-q1 devices are available in a vssop-8 package. device information (1) part number package body size (nom) DAC8551-Q1 dac6551-q1 vssop (8) 3.00 mm 3.00 mm (1) for all available packages, see the orderable addendum at the end of the data sheet. functional block diagram dac v dd v out shift register gnd sync sclk d in v ref dac register ref (+) pwd control resistornetwork v fb copyright ? 2016, texas instruments incorporated productfolder sample &buy technical documents tools & software support &community referencedesign
2 DAC8551-Q1 , dac6551-q1 slaseb8c ? february 2016 ? revised november 2016 www.ti.com product folder links: DAC8551-Q1 dac6551-q1 submit documentation feedback copyright ? 2016, texas instruments incorporated table of contents 1 features .................................................................. 1 2 applications ........................................................... 1 3 description ............................................................. 1 4 revision history ..................................................... 2 5 pin configuration and functions ......................... 4 6 specifications ......................................................... 4 6.1 absolute maximum ratings ...................................... 4 6.2 esd ratings ............................................................ 5 6.3 recommended operating conditions ....................... 5 6.4 thermal information .................................................. 5 6.5 electrical characteristics ........................................... 5 6.6 timing requirements ............................................... 7 6.7 switching characteristics .......................................... 7 6.8 typical characteristics .............................................. 8 7 detailed description ............................................ 13 7.1 overview ................................................................. 13 7.2 functional block diagram ....................................... 13 7.3 feature description ................................................. 13 7.4 device functional modes ........................................ 15 7.5 programming .......................................................... 16 8 application and implementation ........................ 17 8.1 application information ............................................ 17 8.2 typical applications ................................................ 17 8.3 system examples .................................................. 20 9 power supply recommendations ...................... 21 10 layout ................................................................... 21 10.1 layout guidelines ................................................. 21 10.2 layout example .................................................... 21 11 device and documentation support ................. 22 11.1 documentation support ........................................ 22 11.2 receiving notification of documentation updates 22 11.3 community resources .......................................... 22 11.4 trademarks ........................................................... 22 11.5 electrostatic discharge caution ............................ 22 11.6 glossary ................................................................ 22 12 mechanical, packaging, and orderable information ........................................................... 22 4 revision history changes from revision b (november 2016) to revision c page ? added device dac6551-q1 to the data sheet ....................................................................................................................... 1 ? changed the data sheet title from: DAC8551-Q1 automotive 16-bit... to: dacx551-q1 automotive 16-, 12-bit... ........... 1 ? changed relative accuracy in the features section ............................................................................................................. 1 ? updated the description to include the dac6551-q1 device ............................................................................................... 1 ? added dac6551-q1 to the thermal table ........................................................................................................................... 5 ? added separate lines for the dac6551-q1 and DAC8551-Q1 devices for resolution, relative accuracy, and differential nonlinearity in the electrical characteristics table ................................................................................................ 5 ? changed note 1 of the electrical characteristics table .......................................................................................................... 6 ? updated the overview section to include the dac6551-q1 device .................................................................................... 13 ? changed equation 1 ............................................................................................................................................................. 13 ? changed the definitions of in the " where: " statement for equation 1 ................................................................................... 14 ? deleted a sentence from the resistor string section: " monotonicity is ennsured because of the string resistor archietecture. " ....................................................................................................................................................................... 14 ? added figure 31 .................................................................................................................................................................. 16 ? updated the application information section to include the dac6551-q1 device .............................................................. 17 ? updated the using the ref02 as a power supply for the dacx551-q1 device section to include the dac6551-q1 device .................................................................................................................................................................................. 19 ? updated the system examples section to include the dac6551-q1 device ...................................................................... 20 ? updated the power supply recommendations section to include the dac6551-q1 device ............................................. 21 ? updated the layout guidelines section to include the dac6551-q1 device ...................................................................... 21
3 DAC8551-Q1 , dac6551-q1 www.ti.com slaseb8c ? february 2016 ? revised november 2016 product folder links: DAC8551-Q1 dac6551-q1 submit documentation feedback copyright ? 2016, texas instruments incorporated changes from revision a (march 2016) to revision b page ? changed relative accuracy in the features section ............................................................................................................. 1 ? changed power supply voltage in the features section ....................................................................................................... 1 ? changed voltage for v dd in the pin functions table ............................................................................................................. 4 ? changed supply voltage in the recommended operating conditions table ......................................................................... 5 ? changed values in the thermal information table .................................................................................................................. 5 ? changed supply voltage in the conditions statement of the electrical characteristics table ................................................ 5 ? removed two rows and all test conditions in the logic inputs section of the electrical characteristics table ................. 6 ? changed supply voltage in the power requirements section of the electrical characteristics table ......................... 6 ? changed test conditions for supply current in the power requirements section of the electrical characteristics table ....................................................................................................................................................................................... 6 ? changed v dd in the condition statement and test conditions of the timing requirements (1) (2) section ................................ 7 ? changed min value for sclk low time in the timing requirements (1) (2) section ................................................................ 7 ? added text in the application information section ................................................................................................................ 17 ? changed supply voltage in the power supply recommendations section .......................................................................... 21 ? added new receiving notification of documentation updates section ................................................................................ 22 changes from original (february 2016) to revision a page ? changed data sheet from product preview to producton data .......................................................................... 1
4 DAC8551-Q1 , dac6551-q1 slaseb8c ? february 2016 ? revised november 2016 www.ti.com product folder links: DAC8551-Q1 dac6551-q1 submit documentation feedback copyright ? 2016, texas instruments incorporated 5 pin configuration and functions dgk package 8-pin vssop top view pin functions pin type description name no. d in 7 i serial data input. data is clocked into the 24-bit input shift register on each falling edge of the serial clock input. schmitt-trigger logic input. gnd 8 gnd ground reference point for all circuitry on the device sclk 6 i serial clock input. data can be transferred at rates up to 30 mhz. schmitt-trigger logic input. sync 5 i level-triggered control input (active-low). this is the frame synchronization signal for the input data. sync going low enables the input shift register, and data is transferred in on the falling edges of the following clocks. the dac is updated following the 24th clock (unless sync is taken high before this edge, in which case the rising edge of sync acts as an interrupt, and the write sequence is ignored by the device). schmitt-trigger logic input. v dd 1 pwr power supply input, 3 v to 5.5 v v fb 3 i feedback connection for the output amplifier. for voltage output operation, tie to v out externally. v out 4 o analog output voltage from dac. the output amplifier has rail-to-rail operation. v ref 2 i reference voltage input (1) stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. these are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions . exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. 6 specifications 6.1 absolute maximum ratings over operating ambient temperature range (unless otherwise noted) (1) min max unit v dd to gnd ? 0.3 6 v digital input voltage to gnd d in , sclk and sync ? 0.3 v dd + 0.3 v v out to gnd ? 0.3 v dd + 0.3 v v ref to gnd ? 0.3 v dd + 0.3 v v fb to gnd ? 0.3 v dd + 0.3 v junction temperature range, t j max ? 65 150 c storage temperature, t stg ? 65 150 c 1 v dd 8 gnd 2 v ref 7 d in 3 v fb 6 sclk 4 v out 5 sync
5 DAC8551-Q1 , dac6551-q1 www.ti.com slaseb8c ? february 2016 ? revised november 2016 product folder links: DAC8551-Q1 dac6551-q1 submit documentation feedback copyright ? 2016, texas instruments incorporated (1) aec q100-002 indicates that hbm stressing shall be in accordance with the ansi/esda/jedec js-001 specification. 6.2 esd ratings value unit v (esd) electrostatic discharge human-body model (hbm), per aec q100-002 (1) 2000 v charged-device model (cdm), per aec q100-011 all pins 500 corner pins (1, 4, 5, and 8) 750 6.3 recommended operating conditions over operating ambient temperature range (unless otherwise noted) min nom max unit power supply supply voltage v dd to gnd 3 5.5 v digital inputs digital input voltage d in , sclk and sync 0 v dd v reference input v ref reference input voltage 0 v dd v amplifier feedback input v fb output amplifier feedback input v out v temperature range t a operating ambient temperature ? 40 125 c (1) for more information about traditional and new thermal metrics, see the semiconductor and ic package thermal metrics application report. 6.4 thermal information thermal metric (1) DAC8551-Q1 dac6551-q1 unit dgk (vssop) 8 pins r ja junction-to-ambient thermal resistance 173.7 c/w r jc(top) junction-to-case (top) thermal resistance 65.4 c/w r jb junction-to-board thermal resistance 94.2 c/w jt junction-to-top characterization parameter 10.2 c/w jb junction-to-board characterization parameter 92.7 c/w (1) linearity calculated using a reduced code range of 485 to 64,741 (16-bit); 30 to 4,046 (12-bit); output unloaded. 6.5 electrical characteristics v dd = 3 v to 5.5 v, v ref = v dd and t a = ? 40 c to 125 c, unless otherwise noted. parameter test conditions min typ max unit static performance (1) resolution DAC8551-Q1 16 bits dac6551-q1 12 relative accuracy DAC8551-Q1 4 16 lsb dac6551-q1 0.3 1 differential nonlinearity DAC8551-Q1 0.35 2 lsb dac6551-q1 0.02 1 offset error 1 15 mv full-scale error 0.05 0.5 % of fsr gain error 0.02 0.2 % of fsr offset error drift 5 v/ c gain temperature coefficient 1 ppm of fsr/ c
6 DAC8551-Q1 , dac6551-q1 slaseb8c ? february 2016 ? revised november 2016 www.ti.com product folder links: DAC8551-Q1 dac6551-q1 submit documentation feedback copyright ? 2016, texas instruments incorporated electrical characteristics (continued) v dd = 3 v to 5.5 v, v ref = v dd and t a = ? 40 c to 125 c, unless otherwise noted. parameter test conditions min typ max unit (2) specified by design and characterization; not production tested. psrr power-supply rejection ratio r l = 2 k ? , c l = 200 pf 0.75 mv/v output characteristics (2) output voltage range 0 v ref v output voltage settling time to 0.003% fsr, 0200h to fd00h r l = 2 k ? , 0 pf < c l < 200 pf 8 s slew rate 1.4 v/ s capacitive load stability r l = 470 pf r l = 2 k ? 1000 pf code change glitch impulse 1 lsb change around major carry 0.1 nv-s digital feedthrough 50 k ? series resistance on digital lines 0.1 nv-s dc output impedance at mid-code input 1 ? short-circuit current v dd = 3 v to 5.5 v 35 ma ac performance snr signal-to-noise ratio bw = 20 khz, v dd = 5 v, v ref = 4.5 v, f out = 1 khz first 19 harmonics removed for snr calculation 84 db thd total harmonic distortion ? 80 db sfdr spurious-free dynamic range 84 db sinad signal to noise and distortion 76 db reference input reference current v ref = v dd = 5.5 v 50 a v ref = v dd = 3.6 v 25 reference input range 0 v dd v reference input impedance 125 k ? logic inputs (2) input current 1 a v in l input low voltage 0.3 v dd v v in h input high voltage 0.7 v dd v pin capacitance 3 pf power requirements v dd supply voltage 3 5.5 v i dd supply current normal mode, midscale code, no load, does not include reference current. v ih = v dd and v il = gnd, v dd = 3.6 v to 5.5 v 160 250 a normal mode, midscale code, no load, does not include reference current. v ih = v dd and v il = gnd, v dd = 3 v to 3.6 v 110 240 all power-down modes, v ih = v dd and v il = gnd, v dd = 3.6 v to 5.5 v 0.8 3 all power-down modes, v ih = v dd and v il = gnd, v dd = 3 v to 3.6 v 0.5 3 power efficiency i out / i dd i load = 2 ma, v dd = 5 v 89% temperature range t a ambient temperature ? 40 125 c
7 DAC8551-Q1 , dac6551-q1 www.ti.com slaseb8c ? february 2016 ? revised november 2016 product folder links: DAC8551-Q1 dac6551-q1 submit documentation feedback copyright ? 2016, texas instruments incorporated (1) all input signals are specified with t r = t f = 5 ns (10% to 90% of v dd ) and timed from a voltage level of (v il + v ih ) / 2. (2) see the serial-write-operation timing diagram . 6.6 timing requirements (1) (2) v dd = 3 v to 5.5 v and t a = ? 40 c to 125 c, unless otherwise noted. parameter test conditions min nom max unit f sclk serial clock frequency v dd = 3 v to 3.6 v 25 mhz v dd = 3.6 v to 5.5 v 30 t 1 sclk cycle time v dd = 3 v to 3.6 v 40 ns v dd = 3.6 v to 5.5 v 34 t 2 sclk high time v dd = 3 v to 3.6 v 13 ns v dd = 3.6 v to 5.5 v 13 t 3 sclk low time v dd = 3 v to 3.6 v 13 ns v dd = 3.6 v to 5.5 v 13 t 4 sync to sclk rising edge setup time v dd = 3 v to 3.6 v 0 ns v dd = 3.6 v to 5.5 v 0 t 5 data setup time v dd = 3 v to 3.6 v 5 ns v dd = 3.6 v to 5.5 v 5 t 6 data hold time v dd = 3 v to 3.6 v 5 ns v dd = 3.6 v to 5.5 v 5 t 7 24th sclk falling edge to sync rising edge v dd = 3 v to 3.6 v 0 ns v dd = 3.6 v to 5.5 v 0 t 8 minimum sync high time v dd = 3 v to 3.6 v 50 ns v dd = 3.6 v to 5.5 v 34 t 9 24th sclk falling edge to sync falling edge v dd = 3 v to 5.5 v 50 ns 6.7 switching characteristics over operating ambient temperature range (unless otherwise noted) parameter test conditions min typ max unit power-up time coming out of power-down mode, v dd = 5 v 2.5 s coming out of power-down mode, v dd = 3.3 v 5 figure 1. serial-write-operation timing diagram sclk 1 24 sync d in db23 db0 db23 t 8 t 6 t 3 t 2 t 1 t 7 t 9 t 5 t 4
8 DAC8551-Q1 , dac6551-q1 slaseb8c ? february 2016 ? revised november 2016 www.ti.com product folder links: DAC8551-Q1 dac6551-q1 submit documentation feedback copyright ? 2016, texas instruments incorporated 6.8 typical characteristics at t a = 25 c, v dd = 5 v unless otherwise noted. figure 2. linearity error and differential linearity error vs digital input code ( ? 40 c) figure 3. linearity error and differential linearity error vs digital input code (25 c) figure 4. linearity error and differential linearity error vs digital input code (125 c) figure 5. offset error vs temperature figure 6. full-scale error vs temperature figure 7. source and sink current capability 0 - 5 - 10 temperature ( c) error (mv) v = 5 v dd v = 4.99 v ref - 50 125 0 50 100 25 75 25 - 25 64 2 0 - 2 - 4 - 6 le (lsb) 0 8192 16384 24576 32768 digital input code 40960 49152 57344 65536 1.00.5 0 - 0.5 - 1.0 dle (lsb) v = 5v, v = 4.99v dd ref 10 50 - 5 - 50 125 0 50 100 temperature ( c) error (mv) v = 5 v dd v = 4.99 v ref 25 75 25 - 25 64 2 0 - 2 - 4 - 6 le (lsb) 0 8192 16384 24576 32768 digital input code 40960 49152 57344 65536 1.00.5 0 - 0.5 - 1.0 dle (lsb) v = 5v, v = 4.99v dd ref 64 2 0 - 2 - 4 - 6 le (lsb) 0 8192 16384 24576 32768 digital input code 40960 49152 57344 65536 1.00.5 0 - 0.5 - 1.0 dle (lsb) v = 5v, v = 4.99v dd ref 65 4 3 2 1 0 0 10 2 4 6 8 i (ma) (source/sink) v out (mv) dac loaded with ffffh dac loaded with 0000h v = 5.5v dd v ref dd = v - 10mv
9 DAC8551-Q1 , dac6551-q1 www.ti.com slaseb8c ? february 2016 ? revised november 2016 product folder links: DAC8551-Q1 dac6551-q1 submit documentation feedback copyright ? 2016, texas instruments incorporated typical characteristics (continued) at t a = 25 c, v dd = 5 v unless otherwise noted. figure 8. supply current vs digital input code figure 9. power-supply current vs temperature figure 10. supply current vs supply voltage figure 11. power-down current vs supply voltage figure 12. supply current vs logic input voltage figure 13. full-scale settling time: 5-v rising edge 18001600 1400 1200 1000 800600 400 200 0 0 1 2 3 4 5 v (v) logic i dd ( m a) t a = 25 c, scl input (all other inputs = gnd) v dd ref = v = 5.5v time (2 s/div) m v = 5v v = 4.096v from code: d000 to code: ffff dd ref trigger pulse 5v/div zoomed rising edge1mv/div rising edge1v/div v dd (v) power-down current ( p a) 3 3.5 4 4.5 5 5.5 0 0.2 0.4 0.6 0.8 1 d010 v ref = v dd 300280 260 240 220 200 180 160 140 120 100 3 3.5 4 5 4.5 5.5 v (v) dd i ( a) m dd v v reference current included, no load ref dd = 300250 200 150 100 50 0 0 8192 24576 40960 57344 65536 16384 32768 49152 digital input code i dd ( m a) v dd ref = v = 5v reference current included 250200 150 100 50 0 i ( a) m dd v = v = 5 v ref dd temperature ( c) - 50 125 0 50 100 25 75 - 25
10 DAC8551-Q1 , dac6551-q1 slaseb8c ? february 2016 ? revised november 2016 www.ti.com product folder links: DAC8551-Q1 dac6551-q1 submit documentation feedback copyright ? 2016, texas instruments incorporated typical characteristics (continued) at t a = 25 c, v dd = 5 v unless otherwise noted. figure 14. full-scale settling time: 5-v falling edge figure 15. half-scale settling time: 5-v rising edge figure 16. half-scale settling time: 5-v falling edge figure 17. glitch impulse: 5 v, 1-lsb step, rising edge figure 18. glitch impulse: 5 v, 1-lsb step, falling edge figure 19. glitch impulse: 5 v, 16-lsb step, rising edge time (400ns/div) v = 5v v = 4.096v from code: 8000 to code: 7fff glitch: 0.16nv-s measured worst case dd ref v (500 v/div) m out time (400ns/div) v = 5v v = 4.096v from code: 8000 to code: 8010 glitch: 0.04nv-s dd ref v (500 v/div) m out time (2 s/div) m v = 5v v = 4.096v from code: cfff to code: 4000 dd ref trigger pulse 5v/div zoomed falling edge 1mv/div falling edge 1v/div time (400ns/div) v = 5v v = 4.096v from code: 7fff to code: 8000 glitch: 0.08nv-s dd ref v (500 v/div) m out time (2 s/div) m v = 5v v = 4.096v from code: ffff to code: 0000 dd ref trigger pulse 5v/div zoomed falling edge 1mv/div falling edge 1v/div time (2 s/div) m v = 5v v = 4.096v from code: 4000 to code: cfff dd ref trigger pulse 5v/div zoomed rising edge1mv/div risingedge 1v/div
11 DAC8551-Q1 , dac6551-q1 www.ti.com slaseb8c ? february 2016 ? revised november 2016 product folder links: DAC8551-Q1 dac6551-q1 submit documentation feedback copyright ? 2016, texas instruments incorporated typical characteristics (continued) at t a = 25 c, v dd = 5 v unless otherwise noted. figure 20. glitch impulse: 5 v, 16-lsb step, falling edge figure 21. glitch impulse: 5 v, 256-lsb step, rising edge figure 22. glitch impulse: 5 v, 256-lsb step, falling edge figure 23. total harmonic distortion vs output frequency figure 24. signal-to-noise ratio vs output frequency figure 25. power spectral density time (400ns/div) v = 5v v = 4.096v from code: 8000 to code: 80ff glitch: not detected theoretical worst case dd ref v (5mv/div) out 9896 94 92 90 88 86 84 0 0.5 1.0 1.5 2.0 3.0 3.5 4.5 2.5 4.0 5.5 f (khz) out snr (db) v ref dd = v = 5v -1db fsr digital input f = 1msps s measurement bandwidth = 20khz - 10 - 30 - 50 - 70 - 90 - 110 - 130 0 20 5 10 15 frequency (khz) gain (db) v = 5v dd v = 4.096v ref f = 1khz out f = 1msps clk - 40 - 50 - 60 - 70 - 80 - 90 - 100 0 5 1 2 3 4 f (khz) out thd (db) thd 2nd harmonic 3rd harmonic v = 5v dd v = 4.9v ref -1db fsr digital input f = 1msps s measurement bandwidth = 20khz time (400ns/div) v = 5v v = 4.096v from code: 80ff to code: 8000 glitch: not detected theoretical worst case dd ref v (5mv/div) out time (400ns/div) v = 5v v = 4.096v from code: 8010 to code: 8000 glitch: 0.08nv-s dd ref v (500 v/div) m out
12 DAC8551-Q1 , dac6551-q1 slaseb8c ? february 2016 ? revised november 2016 www.ti.com product folder links: DAC8551-Q1 dac6551-q1 submit documentation feedback copyright ? 2016, texas instruments incorporated typical characteristics (continued) at t a = 25 c, v dd = 5 v unless otherwise noted. figure 26. output noise density 350300 250 200 150 100 100 100k 1k 10k frequency (hz) voltage noise (nv/ ) ? hz v dd = 5v v ref = 4.99v code = 7fffhno load
13 DAC8551-Q1 , dac6551-q1 www.ti.com slaseb8c ? february 2016 ? revised november 2016 product folder links: DAC8551-Q1 dac6551-q1 submit documentation feedback copyright ? 2016, texas instruments incorporated 7 detailed description 7.1 overview the DAC8551-Q1 and dac6551-q1 are small, low-power, voltage-output, 16- and 12-bit digital-to-analog converters (dacs) qualified for automotive applications. the dacx551-q1 devices provide good linearity and minimize undesired code-to-code transient voltages. the devices use a versatile 3-wire serial interface that operates at clock rates to 30 mhz and is compatible with standard spi, qspi, microwire, and digital signal processor (dsp) interfaces. the dacx551-q1 devices require an external reference voltage to set the output range. the devices incorporate a power-on-reset circuit that ensures the dac output powers up at 0 v and remains there until a valid write to the device takes place. the devices contain a power-down feature, accessed over the serial interface, that reduces the current consumption to 800 na at 5 v. the dacx551-q1 devices power consumption is only 800 w at 5 v, reducing to less than 4 w in power-down mode. the dacx551-q1 devices are available in a vssop-8 package. 7.2 functional block diagram 7.3 feature description 7.3.1 dac section the dacx551-q1 architecture consists of a string dac followed by an output buffer amplifier. figure 27 shows a block diagram of the dac architecture. figure 27. dacx551-q1 architecture the input coding to the dacx551-q1 is straight binary, so the ideal output voltage is given by: (1) in out ref n 1 d v v 2 - = gnd dac register v ref v out 50k w 62k w 50k w ref (+) register string ref ( ) - v fb copyright ? 2016, texas instruments incorporated dac v dd v out shift register gnd sync sclk d in v ref dac register ref (+) pwd control resistornetwork v fb copyright ? 2016, texas instruments incorporated
14 DAC8551-Q1 , dac6551-q1 slaseb8c ? february 2016 ? revised november 2016 www.ti.com product folder links: DAC8551-Q1 dac6551-q1 submit documentation feedback copyright ? 2016, texas instruments incorporated feature description (continued) where: ? n = resolution in bits; 12 (dac6551-q1) or 16 (DAC8551-Q1) ? d in = decimal equivalent of the binary code that is loaded to the dac register; it can range from 0 to 2 n-1 . 7.3.1.1 resistor string the resistor string section is shown in figure 28 . it is simply a string of resistors, each of value r. the code loaded into the dac register determines at which node on the string the voltage is tapped off to be fed into the output amplifier by closing one of the switches connecting the string to the amplifier. figure 28. resistor string 7.3.1.2 output amplifier the output buffer amplifier is capable of generating rail-to-rail voltages on its output, giving an output range of 0 v to v dd . it is capable of driving a load of 2 k ? in parallel with 1000 pf to gnd. the source and sink capabilities of the output amplifier can be seen in the typical characteristics . the slew rate is 1.4 v/ s with a full- scale setting time of 8 s with the output unloaded. the inverting input of the output amplifier is brought out to the v fb pin. this configuration allows for better accuracy in critical applications by tying the v fb point and the amplifier output together directly at the load. other signal conditioning circuitry may also be connected between these points for specific applications. 7.3.2 power-on reset the dacx551-q1 contains a power-on-reset circuit that controls the output voltage during power up. on power up, the dac registers are filled with zeros and the output voltages are 0 v; they remain that way until a valid write sequence is made to the dac. the power-on reset is useful in applications where it is important to know the state of the output of the dac while it is in the process of powering up. v ref rr r r v ref 2 r divider to output amplifier (2x gain)
15 DAC8551-Q1 , dac6551-q1 www.ti.com slaseb8c ? february 2016 ? revised november 2016 product folder links: DAC8551-Q1 dac6551-q1 submit documentation feedback copyright ? 2016, texas instruments incorporated 7.4 device functional modes 7.4.1 power-down modes the dacx551-q1 supports four separate modes of operation. these modes are programmable by setting two bits (pd1 and pd0) in the control register. table 1 shows how the state of the bits corresponds to the mode of operation of the device. table 1. operating modes pd1 (db17) pd0 (db16) operating mode 0 0 normal operation ? ? power-down modes 0 1 output typically 1 k ? to gnd 1 0 output typically 100 k ? to gnd 1 1 high-z when both bits are set to 0, the device works normally with its typical current consumption of 160 a at 5 v. however, for the three power-down modes, the supply current falls to 800 na at 5 v. not only does the supply current fall, but the output stage is also internally switched from the output of the amplifier to a resistor network of known values. this configuration has the advantage that the output impedance of the device is known while it is in power-down mode. there are three different options. the output is connected internally to gnd through a 1 ? k ? resistor, a 100-k ? resistor, or it is left open-circuited (high-z). the output stage is illustrated in figure 29 . figure 29. output stage during power down all analog circuitry is shut down when the power-down mode is activated. however, the contents of the dac register are unaffected when in power down. the time to exit power-down is typically 2.5 s for v dd = 5 v, and 5 s for v dd = 3 v. see the typical characteristics for more information. v out amplifier resistor string dac power-down circuitry resistornetwork v fb copyright ? 2016, texas instruments incorporated
16 DAC8551-Q1 , dac6551-q1 slaseb8c ? february 2016 ? revised november 2016 www.ti.com product folder links: DAC8551-Q1 dac6551-q1 submit documentation feedback copyright ? 2016, texas instruments incorporated 7.5 programming the DAC8551-Q1 and dac6551-q1 devices have a 3-wire serial interface ( sync, sclk, and d in ), which is compatible with spi, qspi, and microwire interface standards, as well as most dsps. see the serial write operation timing diagram section for an example of a typical write sequence. the input shift register is 24 bits wide, as shown in figure 30 and figure 31 . the first six bits are don't care bits. the next two bits (pd1 and pd0) are control bits that control which mode of operation the part is in (normal mode or any one of three power-down modes). a more complete description of the various modes is located in the power-down modes section. the next 16 bits are the left aligned data bits. these bits are transferred to the dac register on the 24th falling edge of sclk. db23 db0 x x x x x x pd1 pd0 d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 figure 30. DAC8551-Q1 data-input register format db23 db0 x x x x x x pd1 pd0 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 0 0 0 0 figure 31. dac6551-q1 data-input register format the write sequence begins by bringing the sync line low. data from the d in line are clocked into the 24-bit shift register on each falling edge of sclk. the serial clock frequency can be as high as 30 mhz, making the devices compatible with high-speed dsps. on the 24th falling edge of the serial clock, the last data bit is clocked in and the programmed function is executed (that is, a change in dac register contents and/or a change in the mode of operation). at this point, the sync line may be kept low or brought high. in either case, it must be brought high for a minimum of 33 ns before the next write sequence so that a falling edge of sync can initiate the next write sequence. as previously mentioned, it must be brought high again just before the next write sequence. 7.5.1 sync interrupt in a normal write sequence, the sync line is kept low for at least 24 falling edges of sclk, and the dac is updated on the 24th falling edge. however, if sync is brought high before the 24th falling edge, it acts as an interrupt to the write sequence. the shift register is reset, and the write sequence is seen as invalid. neither an update of the dac register contents nor a change in the operating mode occurs, as shown in figure 32 . figure 32. sync interrupt facility clk sync d in valid write sequence: output updates on the 24th falling edge 24th falling edge 24th falling edge db23 db80 db23 db80
17 DAC8551-Q1 , dac6551-q1 www.ti.com slaseb8c ? february 2016 ? revised november 2016 product folder links: DAC8551-Q1 dac6551-q1 submit documentation feedback copyright ? 2016, texas instruments incorporated 8 application and implementation note information in the following applications sections is not part of the ti component specification, and ti does not warrant its accuracy or completeness. ti ? s customers are responsible for determining suitability of components for their purposes. customers should validate and test their design implementation to confirm system functionality. 8.1 application information the DAC8551-Q1 and dac6551-q1 devices are aec-q100 qualified, low-power, ultralow-glitch, 16-bit and 12- bit dacs, respectively. the wide temperature range, low-power consumption and very low glitch of the devices make them a great choice for automotive applications such as radar and sensor conditioning. 8.2 typical applications 8.2.1 loop-powered 2-wire 4-ma to 20-ma transmitter with xtr116 figure 33. loop-powered transmitter 8.2.1.1 design requirements this design is commonly referred to as a loop-powered, or 2-wire, 4 ma to 20 ma transmitter. the transmitter has only two external input terminals: a supply connection and an output, or return, connection. the transmitter communicates back to its host, typically a plc analog input module, by precisely controlling the magnitude of its return current. in order to conform to the 4 ma to 20 ma communication standard, the complete transmitter must consume less than 4 ma of current. the DAC8551-Q1 device enables the accurate control of the loop current from 4 ma to 20 ma in 16-bit steps. 8.2.1.2 detailed design procedure although it is possible to recreate the loop-powered circuit using discrete components, the xtr116 provides simplicity and improved performance due to the matched internal resistors. the output current can be modified if necessary by looking using equation 2 . (2) reg ref out n 1 3 v v code 2475 i (code) 1 r 25 2 r ? ? ? ? w ? = + + ? ? w ? ? u1 dac8551 r3 25.6 k r 1 102.4 k u2 + 2475 v reg q1 v+ e b regulator reference 25 v ref i in i ret r lim xtr116 c 1 2.2 f r 2 49.9 w q1 v+ i o v+ v ref v out v+ return c || c 2 3 0.1001 f copyright ? 2016, texas instruments incorporated
18 DAC8551-Q1 , dac6551-q1 slaseb8c ? february 2016 ? revised november 2016 www.ti.com product folder links: DAC8551-Q1 dac6551-q1 submit documentation feedback copyright ? 2016, texas instruments incorporated typical applications (continued) for more details of this application, see 2-wire, 4-20ma transmitter, emc/emi tested reference design ( tiduao7 ). it covers in detail the design of this circuit as well as how to protect it from emc/emi tests. 8.2.1.3 application curves total unadjusted error (tue) is a good estimate for the performance of the output as shown in figure 34 . the linearity of the output or inl is in figure 35 . figure 34. total unadjusted error figure 35. integral nonlineareity 8.2.2 bipolar operation using the DAC8551-Q1 device the DAC8551-Q1 device has been designed for single-supply operation, but a bipolar output range is also possible using the circuit in figure 36 . the circuit shown gives an output voltage range of v ref . rail-to-rail operation at the amplifier output is achievable using an opa703 as the output amplifier. figure 36. bipolar output range the output voltage for any input code can be calculated as follows: (3) where d represents the input code in decimal (0 ? 65,535) with v ref = 5v, r 1 = r 2 = 10 k ? . (4) v ref r 2 10 k w 10 k w v fb r 1 v out 10 f m 0.1 f m 6 v 5 v three-wire serial interface v ref DAC8551-Q1 opa703 C6 v code total unadjusted error (%fsr) -0.1 -0.05 0 0.05 0.1 0 10k 20k 30k 40k 50k 60k 65535 d001 code integral nonlinearity (lsbs) -10 -8 -6 -4 -2 0 2 4 6 8 10 0 10k 20k 30k 40k 50k 60k 65535 d002 o 10 d v 5 v 65536 ? ? = - ? ? 1 2 2 o ref ref 1 1 r r r d v v v 65536 r r ? ? ? ? + ? ? = - ? ? ? ? ? ? ? ?
19 DAC8551-Q1 , dac6551-q1 www.ti.com slaseb8c ? february 2016 ? revised november 2016 product folder links: DAC8551-Q1 dac6551-q1 submit documentation feedback copyright ? 2016, texas instruments incorporated using this example, an output voltage range of 5 v with 0000h corresponding to a ? 5 v output and ffffh corresponding to a 5 v output can be achieved. similarly, using v ref = 2.5 v, a 2.5 v output voltage range can be achieved. 8.2.3 using the ref02 as a power supply for the dacx551-q1 due to the extremely low supply current required by the dacx551-q1, an alternative option is to use a precision reference such as the ref02 device to supply the required voltage to the device, as illustrated in figure 37 . figure 37. ref02 as a power supply to the dacx551-q1 this configuration is especially useful if the power supply is quite noisy or if the system supply voltages are at some value other than 5 v. the ref02 device outputs a steady supply voltage for the device. if the ref02 device is used, the current it must supply to the device is 200 a. this configuration is with no load on the output of the dac. when a dac output is loaded, the ref02 also must supply the current to the load. the total current required (with a 5 k ? load on the dac output) is: (5) the load regulation of the ref02 is typically 0.005%/ma, resulting in an error of 299 v for the 1.2 ma current drawn from it. this value corresponds to a 3.9 lsb error. 200 a 5v 5k 1.2ma ref02 three-wire serial interface 285 a m v = 0 v to 5 v out sync sclk d in dacx551-q1 15 v 5 v
20 DAC8551-Q1 , dac6551-q1 slaseb8c ? february 2016 ? revised november 2016 www.ti.com product folder links: DAC8551-Q1 dac6551-q1 submit documentation feedback copyright ? 2016, texas instruments incorporated 8.3 system examples 8.3.1 interface from the dacx551-q1 to 8051 see figure 38 for a serial interface between the dacx551-q1 and a typical 8051-type microcontroller. the setup for the interface is as follows: txd of the 8051 drives sclk of the dacx551-q1, whereas rxd drives the serial data line of the device. the sync signal is derived from a bit-programmable pin on the port of the 8051. in this case, port line p3.3 is used. when data are to be transmitted to the dacx551-q1, p3.3 is taken low. the 8051 transmits data in 8-bit bytes; thus, only eight falling clock edges occur in the transmit cycle. to load data to the dac, p3.3 is left low after the first eight bits are transmitted, then a second write cycle is initiated to transmit the second byte of data. p3.3 is taken high following the completion of the third write cycle. the 8051 outputs the serial data in a format that has the lsb first. the dacx551-q1 requires data with the msb as the first bit received. therefore, the 8051 transmit routine must take this into account, and mirror the data as needed. figure 38. interface from the dacx551-q1 to 80c51 or 80l51 8.3.2 interface from the dacx551-q1 to microwire figure 39 shows an interface between the dacx551-q1 and any microwire-compatible device. serial data are shifted out on the falling edge of the serial clock and is clocked into the dacx551-q1 on the rising edge of the sk signal. figure 39. interface from the dacx551-q1 to microwire 8.3.3 interface from the dacx551-q1 to 68hc11 figure 40 shows a serial interface between the dacx551-q1 and the 68hc11 microcontroller. sck of the 68hc11 drives sclk of the dacx551-q1, whereas the mosi output drives the serial data line of the dac. the sync signal is derived from a port line (pc7), similar to the 8051 diagram. figure 40. interface from the dacx551-q1 to 68hc11 the 68hc11 should be configured so that its cpol bit is 0 and its cpha bit is 1. this configuration causes data appearing on the mosi output to be valid on the falling edge of sck. when data are being transmitted to the dac, the sync line is held low (pc7). serial data from the 68hc11 are transmitted in 8-bit bytes with only eight falling clock edges occurring in the transmit cycle. (data are transmitted msb first.) in order to load data to the dacx551-q1, pc7 is left low after the first eight bits are transferred, then a second and third serial write operation are performed to the dac. pc7 is taken high at the end of this procedure. 68hc11 (1) pc7 sck mosi sync sclkd in note: (1) additional pins omitted for clarity. dacx551-q1 (1) microwire tm cs sk so sync sclkd in note: (1) additional pins omitted for clarity. dacx551-q1 (1) 80c51 or 80l51 (1) p3.3 txd rxd sync sclk d in note: (1) additional pins omitted for clarity. dacx551-q1 (1)
21 DAC8551-Q1 , dac6551-q1 www.ti.com slaseb8c ? february 2016 ? revised november 2016 product folder links: DAC8551-Q1 dac6551-q1 submit documentation feedback copyright ? 2016, texas instruments incorporated 9 power supply recommendations the dacx551-q1 can operate within the specified supply voltage range of 3 v to 5.5 v. the power applied to v dd should be well-regulated and low-noise. switching power supplies and dc/dc converters often have high- frequency glitches or spikes riding on the output voltage. in addition, digital components can create similar high- frequency spikes. this noise can easily couple into the dac output voltage through various paths between the power connections and analog output. in order to further minimize noise from the power supply, a strong recommendation is to include a 1- f to 10- f capacitor and 0.1- f bypass capacitor. the current consumption on the v dd pin, the short-circuit current limit, and the load current for the device is listed in the electrical characteristics table. the power supply must meet the aforementioned current requirements. 10 layout 10.1 layout guidelines a precision analog component requires careful layout, adequate bypassing, and clean, well-regulated power supplies. the dacx551-q1 offers single-supply operation, and is often used in close proximity with digital logic, microcontrollers, microprocessors, and digital signal processors. the more digital logic present in the design and the higher the switching speed, the more difficult it is to keep digital noise from appearing at the output. due to the single ground pin of the dacx551-q1, all return currents, including digital and analog return currents for the dac, must flow through a single point. ideally, gnd would be connected directly to an analog ground plane. this plane would be separate from the ground connection for the digital components until they were connected at the power-entry point of the system. as with the gnd connection, v dd should be connected to a power-supply plane or trace that is separate from the connection for digital logic until they are connected at the power-entry point. in addition, a 1 f to 10 f capacitor and 0.1 f bypass capacitor are strongly recommended. in some situations, additional bypassing may be required, such as a 100 f electrolytic capacitor or even a pi filter made up of inductors and capacitors ? all designed to essentially low-pass filter the 5 v supply, removing the high-frequency noise. 10.2 layout example figure 41. layout diagram 12 3 4 5 6 7 8
22 DAC8551-Q1 , dac6551-q1 slaseb8c ? february 2016 ? revised november 2016 www.ti.com product folder links: DAC8551-Q1 dac6551-q1 submit documentation feedback copyright ? 2016, texas instruments incorporated 11 device and documentation support 11.1 documentation support 11.1.1 related documentation 2-wire, 4-20ma transmitter, emc/emi tested reference design ( tiduao7 ) 11.2 receiving notification of documentation updates to receive notification of documentation updates, navigate to the device product folder on ti.com. in the upper right corner, click on alert me to register and receive a weekly digest of any product information that has changed. for change details, review the revision history included in any revised document. 11.3 community resources the following links connect to ti community resources. linked contents are provided "as is" by the respective contributors. they do not constitute ti specifications and do not necessarily reflect ti's views; see ti's terms of use . ti e2e ? online community ti's engineer-to-engineer (e2e) community. created to foster collaboration among engineers. at e2e.ti.com, you can ask questions, share knowledge, explore ideas and help solve problems with fellow engineers. design support ti's design support quickly find helpful e2e forums along with design support tools and contact information for technical support. 11.4 trademarks e2e is a trademark of texas instruments. all other trademarks are the property of their respective owners. 11.5 electrostatic discharge caution these devices have limited built-in esd protection. the leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the mos gates. 11.6 glossary slyz022 ? ti glossary . this glossary lists and explains terms, acronyms, and definitions. 12 mechanical, packaging, and orderable information the following pages include mechanical, packaging, and orderable information. this information is the most- current data available for the designated devices. this data is subject to change without notice and without revision of this document. for browser-based versions of this data sheet, see the left-hand navigation pane.
package option addendum www.ti.com 14-dec-2016 addendum-page 1 packaging information orderable device status (1) package type package drawing pins package qty eco plan (2) lead/ball finish (6) msl peak temp (3) op temp (c) device marking (4/5) samples dac6551aqdgkrq1 preview vssop dgk 8 2500 green (rohs & no sb/br) cu nipdauag level-2-260c-1 year -40 to 125 d61q dac8551aqdgkrq1 active vssop dgk 8 2500 green (rohs & no sb/br) cu nipdauag level-2-260c-1 year -40 to 125 d81q (1) the marketing status values are defined as follows: active: product device recommended for new designs. lifebuy: ti has announced that the device will be discontinued, and a lifetime-buy period is in effect. nrnd: not recommended for new designs. device is in production to support existing customers, but ti does not recommend using this part in a new design. preview: device has been announced but is not in production. samples may or may not be available. obsolete: ti has discontinued the production of the device. (2) eco plan - the planned eco-friendly classification: pb-free (rohs), pb-free (rohs exempt), or green (rohs & no sb/br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. tbd: the pb-free/green conversion plan has not been defined. pb-free (rohs): ti's terms "lead-free" or "pb-free" mean semiconductor products that are compatible with the current rohs requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. where designed to be soldered at high temperatures, ti pb-free products are suitable for use in specified lead-free processes. pb-free (rohs exempt): this component has a rohs exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. the component is otherwise considered pb-free (rohs compatible) as defined above. green (rohs & no sb/br): ti defines "green" to mean pb-free (rohs compatible), and free of bromine (br) and antimony (sb) based flame retardants (br or sb do not exceed 0.1% by weight in homogeneous material) (3) msl, peak temp. - the moisture sensitivity level rating according to the jedec industry standard classifications, and peak solder temperature. (4) there may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) multiple device markings will be inside parentheses. only one device marking contained in parentheses and separated by a "~" will appear on a device. if a line is indented then it is a continuation of the previous line and the two combined represent the entire device marking for that device. (6) lead/ball finish - orderable devices may have multiple material finish options. finish options are separated by a vertical ruled line. lead/ball finish values may wrap to two lines if the finish value exceeds the maximum column width. important information and disclaimer: the information provided on this page represents ti's knowledge and belief as of the date that it is provided. ti bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. efforts are underway to better integrate information from third parties. ti has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. ti and ti suppliers consider certain information to be proprietary, and thus cas numbers and other limited information may not be available for release.
package option addendum www.ti.com 14-dec-2016 addendum-page 2 in no event shall ti's liability arising out of such information exceed the total purchase price of the ti part(s) at issue in this document sold by ti to customer on an annual basis. other qualified versions of DAC8551-Q1 : ? catalog: dac8551 note: qualified version definitions: ? catalog - ti's standard catalog product
tape and reel information *all dimensions are nominal device package type package drawing pins spq reel diameter (mm) reel width w1 (mm) a0 (mm) b0 (mm) k0 (mm) p1 (mm) w (mm) pin1 quadrant dac6551aqdgkrq1 vssop dgk 8 2500 330.0 12.4 5.3 3.4 1.4 8.0 12.0 q1 dac8551aqdgkrq1 vssop dgk 8 2500 330.0 12.4 5.3 3.4 1.4 8.0 12.0 q1 package materials information www.ti.com 22-dec-2016 pack materials-page 1
*all dimensions are nominal device package type package drawing pins spq length (mm) width (mm) height (mm) dac6551aqdgkrq1 vssop dgk 8 2500 367.0 367.0 38.0 dac8551aqdgkrq1 vssop dgk 8 2500 367.0 367.0 38.0 package materials information www.ti.com 22-dec-2016 pack materials-page 2

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