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slls552d ? december 2002 ? revised april 2005 features common-mode voltage range (?20 v to 25 v) more than doubles tia/eia-485 requirement receiver equalization extends cable length, signaling rate (hvd23, hvd24) reduced unit-load for up to 256 nodes bus i/o protection to over 16-kv hbm failsafe receiver for open-circuit, short-circuit and idle-bus conditions low standby supply current 1- a max more than 100 mv receiver hysteresis applications long cable solutions ? factory automation ? security networks ? building hvac severe electrical environments ? electrical power inverters ? industrial drives ? avionics description the transceivers in the hvd2x family offer performance far exceeding typical rs?485 devices. in addition to meeting all requirements of the tia/eia?485?a standard, the hvd2x family operates over an extended range of common-mode voltage, and has features such as high esd protection, wide receiver hysteresis, and failsafe operation. this family of devices is ideally suited for long-cable networks, and other applications where the environment is too harsh for ordinary transceivers. these devices are designed for bidirectional data transmission on multipoint twisted-pair cables. example applications are digital motor controllers, remote sensors and terminals, industrial process control, security stations, and environmental control systems. these devices combine a 3-state differential driver and a differential receiver, which operate from a single 5-v power supply. the driver differential outputs and the receiver differential inputs are connected internally to form a differential bus port that of fers minimum loading to the bus. this port features an extended common-mode voltage range making the device suitable for multipoint applications over long cable runs. ?20 v +25 v ?7 v +12 v super?485 rs?485 ?20 v ?15 v ?10 v ?5 v 0 5 v 10 v 15 v 20 v 25 v hvd2x devices operate over a wider common-mode voltage range 0.1 1 10 100 10 100 1000 hvd20 hvd23 hvd24 hvd21 hvd22 cable length ? m signaling rate ? mbps hvd2x application space please be aware that an important notice concerning availability , standard warranty, and use in critical applications of t exas instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. www.ti.com copyright ? 2002 ? 20 03, texas instruments incorporated
slls552d ? december 2002 ? revised april 2005 www.ti.com 2 these devices have limited built-in esd protection. the leads should be shorted together or the device placed in conductive foam duri ng storage or handling to prevent electrostatic damage to the mos gates. description (continued) the ?hvd20 provides high signaling rate (up to 25 mbps) for interconnecting networks of up to 64 nodes. the ?hvd21 allows up to 256 connected nodes at moderate data rates (up to 5 mbps). the driver output slew rate is controlled to provide reliable switching with shaped transitions which reduce high-frequency noise emissions. the ?hvd22 has controlled driver output slew rate for low radiated noise in emission-sensitive applications and for improved signal quality with long stubs. up to 256 ?hvd22 nodes can be connected at signaling rates up to 500 kbps. the ?hvd23 implements receiver equalization technology for improved jitter performance on differential bus applications with data rates up to 25 mbps at cable lengths up to 160 meters. the ?hvd24 implements receiver equalization technology for improved jitter performance on differential bus applications with data rates in the range of 1 mbps to 10 mbps at cable lengths up to 1000 meters. the receivers also include a failsafe circuit that provides a high-level output within 250 microseconds after loss of the input signal. the most common causes of signal loss are disconnected cables, shorted lines, or the absence of any active transmitters on the bus. this feature prevents noise from being received as valid data under these fault conditions. this feature may also be used for wired-or bus signaling. the sn65hvd2x devices are characterized for operation over the temperature range of ?40 c to 85 c. product selection guide part numbers cable length and signaling rate (1) nodes marking sn65hvd20 up to 50 m at 25 mbps up to 64 d: vp20 p: 65hvd20 sn65hvd21 up to 150 m at 5 mbps (with slew rate limit) up to 256 d: vp21 p: 65hvd21 sn65hvd22 up to1200 m at 500 kbps (with slew rate limit) up to 256 d: vp22 p: 65hvd22 sn65hvd23 up to 160 m at 25 mbps (with receiver equalization) up to 64 d: vp23 p: 65hvd23 SN65HVD24 up to 500 m at 3 mbps (with receiver equalization) up to 256 d: vp24 p: 65hvd24 (1) distance and signaling rate predictions based upon belden 3105a cable and 15% eye pattern jitter. available options plastic through-hole p?package (jedec ms-001) plastic small-outline (1) d?package (jedec ms-012) sn65hvd20p sn65hvd21p sn65hvd22p sn65hvd23p SN65HVD24p sn65hvd20d sn65hvd21d sn65hvd22d sn65hvd23d SN65HVD24d (1) add r suffix for taped and reeled carriers.
slls552d ? december 2002 ? revised april 2005 www.ti.com 3 driver function table hvd20, hvd21, hvd22 hvd23, hvd24 input enable outputs input enable outputs d de a b d de a b h h h l h h h l l h l h l h l h x l z z x l z z x open z z x open z z open h h l open h l h h = high level, l= low level, x = don?t care, z = high impedance (off), ? = indeterminate receiver function table differential input enable output v id = (v a ? v b ) re r 0.2 v v id l h ?0.2 v < v id < 0.2 v l h (see note a) v id ?0.2 v l l x h z x open z open circuit l h short circuit l h idle (terminated) bus l h h = high level, l= low level, z = high impedance (off) note a: if the differential input v id remains within the transition range for more than 250 s, the integrated failsafe circuitry detects a bus fault, and set the receiver output to a high state. see figure 15. absolute maximum ratings over oper ating free-air temperature range unless otherwise noted (1) sn65hvd2x supply voltage (2) , v cc ?0.5 v to 7 v voltage at any bus i/o terminal ?27 v to 27 v voltage input, transient pulse, a and b, (through 100 ? , see figure 16) ?60 v to 60 v voltage input at any d, de or re terminal ?0.5 v to v cc + 0.5 v receiver output current, i o ?10 ma to 10 ma human body model (3) a, b, gnd 16 kv electrostatic discharge human body model (3) all pins 5 kv electrostatic discharge charged-device model (4) all pins 1.5 kv machine model (5) all pins 200 v continuous total power dissipation see power dissipation rating t able junction temperature, t j 150 c (1) stresses beyond those listed under ?absolute maximum ratings? may cause permanent damage to the device. these are stress ratings only, a nd functional operation of the device at these or any other conditions beyond those indicated under ?recommended operating conditi ons? is not implied. exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. (2) all voltage values, except differential i/o bus voltages, are with respect to network ground terminal. (3) tested in accordance with jedec standard 22, test method a1 14-a. (4) tested in accordance with jedec standard 22, test method c101. (5) tested in accordance with jedec standard 22, test method a1 15-a.
slls552d ? december 2002 ? revised april 2005 www.ti.com 4 power dissipation ratings package circuit board model t a 25 c power rating derating factor (3) above t a = 25 c t a = 70 c power rating t a = 85 c power rating d low-k (1) 577 mw 4.62 mw/ c 369 mw 300 mw d high-k (2) 913 mw 7.3 mw/ c 584 mw 474 mw p low-k (1) 984 mw 7.87 mw/ c 630 mw 512 mw p high-k (2) 1344 mw 10.8 mw/ c 860 mw 700 mw (1) in accordance with the low-k thermal metric definitions of eia/jesd51?3. (2) in accordance with the high-k thermal metric definitions of eia/jesd51?7. (3) this is the inverse of the junction-to-ambient thermal resistance when board-mounted and with no air flow. thermal characteristics parameter test conditions value units jb junction-to-board thermal resistance d 86.2 jb junction-to-board thermal resistance p 56 c/w jc junction-to-case thermal resistance d 47.1 c/w jc junction-to-case thermal resistance p 54 hvd20 v cc = 5 v, t j = 25 c, 25 mbps 295 hvd21 v cc = 5 v, t j = 25 c, r l = 54 ? , c l = 50 pf (driver), c = 15 pf (receiver), 5 mbps 260 typical hvd22 r l = 54 , c l = 50 pf (driver), c l = 15 pf (receiver), 50% duty cycle square-wave signal, 500 kbps 233 typical hvd23 50% duty cycle square-wave signal, driver and receiver enabled 25 mbps 302 p d device power dissipation hvd24 driver and receiver enabled 5 mbps 267 mw p d device power dissipation hvd20 25 mbps 408 mw hvd21 v cc = 5.5 v, t j = 125 c,r l = 54 ? , c = 50 pf, c = 15 pf (receiver), 5 mbps 342 worst case hvd22 v cc = 5.5 v, t j = 125 c,r l = 54 , c l = 50 pf, c l = 15 pf (receiver), 50% duty cycle square-wave signal, 500 kbps 300 worst case hvd23 50% duty cycle square-wave signal, driver and receiver enabled 25 mbps 417 hvd24 driver and receiver enabled 5 mbps 352 t sd thermal shut-down junction temperature 170 c recommended operating conditions min nom max unit supply voltage, v cc 4.5 5 5.5 v voltage at any bus i/o terminal a, b ?20 25 v high-level input voltage, v ih d, de, re 2 v cc v low-level input voltage, v il d, de, re 0 0.8 v differential input voltage, v id a with respect to b ?25 25 v output current driver ?110 110 ma output current receiver ?8 8 ma operating free-air temperature, t a (1) ?40 85 c junction temperature, t j ?40 130 c (1) maximum free-air temperature operation is allowed as long as the device recommended junction temperature is not exceeded.
slls552d ? december 2002 ? revised april 2005 www.ti.com 5 driver electrical characteristics over recommended operating conditions (unless otherwise noted) (1) parameter test conditions min typ (1) max unit v ik input clamp voltage i i = ?18 ma ?1.5 0.75 v v o open-circuit output voltage a or b, no load 0 v cc v steady-state differential output voltage no load (open circuit) 3.3 4.2 v cc ? v od(ss) ? steady-state differential output voltage magnitude r l = 54 ? , see figure 1 1.8 2.5 v ? v od(ss) ? ?| v od(ss) | change in steady-state differential output voltage between logic states see figure 1 and figure 3 ?0.1 0.1 v v oc(ss) steady-state common-mode output voltage see figure 1 2.1 2.5 2.9 v ? v oc(ss) change in steady-state common-mode output voltage, v oc(h) ? v oc(l) see figure 1 and figure 4 ?0.1 0.1 v v oc(pp) peak-to-peak common-mode output voltage, v oc(max) ? v oc(min) r l = 54 ? , c l = 50 pf, see figure 1 and figure 4 0.35 v v od(ring) differential output voltage over and under shoot r l = 54 ? , c l = 50 pf, see figure 5 10% i i input current d, de ?100 100 a i o(off) output current with power off v cc < = 2.5 v see receiver line input i oz high impedance state output current de at 0 v see receiver line input current i os short-circuit output current v o = ?20 v to 25 v, see figure 9 ?250 250 ma c od differential output capacitance see receiver c i (1) all typical values are at v cc = 5 v and 25 c. driver switching characteristics over recommended operating conditions (unless otherwise noted) parameter test conditions min typ (1) max unit t differential output propagation delay, low-to- high r = 54 , hvd20, hvd23 6 10 20 t plh differential output propagation delay, low-to- high r l = 54 ? , hvd20, hvd23 6 10 20 t plh differential output propagation delay, low-to- high r l = 54 ? , c l = 50 pf, hvd21, hvd24 20 32 60 ns t differential output propagation delay, high-to-low c l = 50 pf, see figure 3 hvd21, hvd24 20 32 60 ns t phl differential output propagation delay, high-to-low c l = 50 pf, see figure 3 hvd22 160 280 500 ns t phl differential output propagation delay, high-to-low see figure 3 hvd22 160 280 500 t differential output rise time r = 54 , hvd20, hvd23 2 6 12 t r differential output rise time r l = 54 , hvd20, hvd23 2 6 12 t r differential output rise time r l = 54 ? , c l = 50 pf, hvd21, hvd24 20 40 60 ns t differential output fall time c l = 50 pf, see figure 3 hvd21, hvd24 20 40 60 ns t f differential output fall time c l = 50 pf, see figure 3 hvd22 200 400 600 ns t f differential output fall time see figure 3 hvd22 200 400 600 t propagation delay time, high-impedance-to-high-level output hvd20, hvd23 40 t pzh propagation delay time, high-impedance-to-high-level output re at 0 v, hvd20, hvd23 40 t pzh propagation delay time, high-impedance-to-high-level output re at 0 v, hvd21, hvd24 100 ns t propagation delay time, high-level-output-to-high-impedance re at 0 v, see figure 6 hvd21, hvd24 100 ns t phz propagation delay time, high-level-output-to-high-impedance see figure 6 hvd22 300 ns t phz propagation delay time, high-level-output-to-high-impedance see figure 6 hvd22 300 t propagation delay time, high-impedance-to-low-level output hvd20, hvd23 40 t pzl propagation delay time, high-impedance-to-low-level output re at 0 v, hvd20, hvd23 40 t pzl propagation delay time, high-impedance-to-low-level output re at 0 v, hvd21, hvd24 100 ns t propagation delay time, low-level-output-to-high-impedance re at 0 v, see figure 7 hvd21, hvd24 100 ns t plz propagation delay time, low-level-output-to-high-impedance see figure 7 hvd22 300 ns t plz propagation delay time, low-level-output-to-high-impedance see figure 7 hvd22 300 t d(standby) time from an active differential output to standby re at v cc , see figure 8 2 s t d(wake) wake-up time from standby to an active differential output re at v cc , see figure 8 8 s hvd20, hvd23 2 t sk(p) pulse skew | t plh ? t phl | hvd21, hvd24 6 ns t sk(p) pulse skew | t plh ? t phl | hvd22 50 ns (1) all typical values are at v cc = 5 v and 25 c.
slls552d ? december 2002 ? revised april 2005 www.ti.com 6 receiver electrical characteristics over recommended operating conditions parameter test conditions min typ (1) max unit v it(+) positive-going differential input voltage threshold see figure 10 v o = 2.4 v, i o = ?8 ma 60 200 mv v it(?) negative-going differential input voltage threshold see figure 10 v o = 0.4 v, i o = 8 ma ?200 ?60 mv v hys hysteresis voltage (v it+ ? v it? ) 100 130 mv v it(f+) positive-going differential input failsafe voltage see figure 15 v cm = ?7 v to 12 v 40 120 200 mv v it(f+) positive-going differential input failsafe voltage threshold see figure 15 v cm = ?20 v to 25 v 120 250 mv v it(f?) negative-going differential input failsafe voltage see figure 15 v cm = ?7 v to 12 v ?200 ?120 ?40 mv v it(f?) negative-going differential input failsafe voltage threshold see figure 15 v cm = ?20 v to 25 v ?250 ?120 mv v ik input clamp voltage i i = ?18 ma ?1.5 v v oh high-level output voltage v id = 200 mv, i oh = ?8 ma, see figure 11 4 v v ol low-level output voltage v id = ?200 mv, i ol = 8 ma, see figure 11 0.4 v v i = ?7 to 12 v, hvd20, hvd23 ?400 500 i i(bus) bus input current (power on or power off) v i = ?7 to 12 v, other input = 0 v hvd21, hvd22, hvd24 ?100 125 a i i(bus) bus input current (power on or power off) v i = ?20 to 25 v, hvd20, hvd23 ?800 1000 a v i = ?20 to 25 v, other input = 0 v hvd21, hvd22, hvd24 ?200 250 i i input current re ?100 100 a r i input resistance hvd20, 23 24 k ? ? c id differential input capacitance v id = 0.5 + 0.4 sine (2 x 1.5 x 10 6 t) 20 pf (1) all typical values are at 25 c. receiver switching characteristics over recommended operating conditions parameter test conditions min typ max unit t plh propagation delay time, low-to-high level output see figure 11 hvd20, hvd23 16 35 ns t phl propagation delay time, high-to-low level output see figure 11 hvd21, hvd22, hvd24 25 50 ns t phl propagation delay time, high-to-low level output see figure 11 hvd21, hvd22, hvd24 25 50 ns t r receiver output rise time see figure 11 2 4 ns t f receiver output fall time see figure 11 2 4 ns t pzh receiver output enable time to high level see figure 12 90 120 ns t phz receiver output disable time from high level see figure 12 16 35 ns t pzl receiver output enable time to low level see figure 13 90 120 ns t plz receiver output disable time from low level see figure 13 16 35 ns t r(standby) time from an active receiver output to standby 2 t r(wake) wake-up time from standby to an active receiver output see figure 14, de at 0 v 8 s t sk(p) pulse skew | t plh ? t phl | 5 ns t sk(p) pulse skew | t plh ? t phl | 5 ns t sk(p) pulse skew | t plh ? t phl | 5 ns t p(set) delay time, bus fail to failsafe set see figure 15, pulse rate = 1 khz 250 350 s t p(reset) delay time, bus recovery to failsafe reset see figure 15, pulse rate = 1 khz 50 ns
slls552d ? december 2002 ? revised april 2005 www.ti.com 7 receiver equalization characteristics (1) over recommended operating conditions parameter test conditions min typ (2) max unit 0 m hvd23 2 100 m hvd20 6 100 m hvd23 3 25 mbps 150 m hvd20 15 25 mbps 150 m hvd23 4 200 m hvd20 27 200 m hvd23 8 200 m hvd20 22 200 m hvd23 8 peak-to-peak pseudo-random nrz code with a bit 16 10 mbps 250 m hvd20 34 t j(pp) peak-to-peak eye-pattern jitter pseudo-random nrz code with a bit pattern length of 2 16 ? 1 , beldon 3105a cable, see figure 27 10 mbps 250 m hvd23 15 ns t j(pp) eye-pattern jitter pattern length of 2 16 ? 1 , beldon 3105a cable, see figure 27 300 m hvd20 49 ns 300 m hvd23 27 5 mbps 500 m hvd21 128 5 mbps 500 m hvd24 18 hvd20 93 3 mbps 500 m hvd21 103 3 mbps 500 m hvd23 90 hvd24 16 1 mbps 1000 m hvd21 216 1 mbps 1000 m hvd24 62 (1) the hvd20 and hvd21 do not have receiver equalization, but are specified for comparison. (2) all typical values are at v cc = 5 v, and temperature = 25 c. supply current over recommended operating conditions (unless otherwise noted) parameter test conditions min typ max unit hvd20 6 9 driver enabled (de at v cc ), receiver enabled (re at 0 v) hvd21 8 12 driver enabled (de at v cc ), receiver enabled (re at 0 v) no load, v i = 0 v or v cc hvd22 6 9 ma no load, v i = 0 v or v cc hvd23 7 11 ma hvd24 10 14 hvd20 5 8 driver enabled (de at v cc ), receiver disabled (re at v cc ) hvd21 7 11 driver enabled (de at v cc ), receiver disabled (re at v cc ) no load, v i = 0 v or v cc hvd22 5 8 ma i cc supply current no load, v i = 0 v or v cc hvd23 5 9 ma i cc supply current hvd24 8 12 hvd20 4 7 driver disabled (de at 0 v), receiver enabled (re at 0 v) hvd21 5 8 driver disabled (de at 0 v), receiver enabled (re at 0 v) no load hvd22 4 7 ma no load hvd23 4.5 9 ma hvd24 5.5 10 driver disabled (de at 0 v), receiver disabled (re at v cc ) d open all hvd2x 1 a
slls552d ? december 2002 ? revised april 2005 www.ti.com 8 equivalent input and output schematic diagrams 9 v 1 k ? 100 k ? input v cc re inputs 9 v 1 k ? 100 k ? input v cc de input 29 v r3 r1 r2 input a input 29 v r3 r1 r2 input b input 29 v v cc a and b outputs 9 v v cc r output 5 ? output v cc hvd20, 23 hvd21, 22, 24 r1/r2 9 k ? 36 k ? r3 45 k ? 180 k ? v cc output d inputs (hvd20, 21, 22) d inputs (hvd23, 24) 29 v
slls552d ? december 2002 ? revised april 2005 www.ti.com 9 parameter measurement information notes: test load capacitance includes probe and jig capacitance (unless otherwise specified). signal generator characteristics: rise and fall time < 6 ns, pulse rate 100 khz, 50% duty cycle, z o = 50 ? (unless otherwise specified) i i i o i o v od 50 pf 27 ? 27 ? v oc 0 v or 3 v figure 1. driver test circuit, v od and v oc without common-mode loading i o i o v od 60 ? v test 0 v or 3 v 375 ? 375 ? v test = ?20 v to 25 v figure 2. driver test circuit, v od with common-mode loading v od 50 ? r l = 54 ? c l = 50 pf signal generator 1.5 v 1.5 v 3 v 0 v t plh t phl v od(h) v od(l) 90% 0 v 10% t r t f input output figure 3. driver switching test circuit and waveforms v oc 50 ? signal generator a b 27 ? 27 ? 50 pf d v a v b v oc v oc(pp) ? v oc(ss) 3.25 v 1.75 v figure 4. driver v oc test circuit and waveforms
slls552d ? december 2002 ? revised april 2005 www.ti.com 10 v od(pp) v od(ring) v od(ring) v od(ss) v od(ss) 0 v differential note : v od(ring) is measured at four points on the output waveform, corresponding to overshoot and undershoot from the v od(h) and v od(l) steady state values. figure 5. v od(ring) waveform and definitions 50 ? c l = 50 pf signal generator de d 0 v or 3 v 3 v if testing a output 0 v if testing b output a b r l = 110 ? output s1 t pzh t phz 0.5 v de output 1.5 v 1.5 v 2.5 v 3 v 0 v v oh v off 0 figure 6. driver enable/disable test, high output 50 ? c l = 50 pf signal generator de d 0 v or 3 v 0 v if testing a output 3 v if testing b output r l = 110 ? output s1 t pzl t plz 0.5 v de output 1.5 v 1.5 v 2.5 v 3 v 0 v 5 v v ol 5 v figure 7. driver enable/disable test, low output v od r l = 54 ? c l = 50 pf 50 ? signal generator de d 0 v or 3 v a b 3 v 1.5 v 0 v 0.2 v 1.5 v t d(wake) t d(standby) de ? v od ? figure 8. driver standby/wake test circuit and waveforms
slls552d ? december 2002 ? revised april 2005 www.ti.com 11 voltage source i os v o figure 9. driver short-circuit test i o v o v id figure 10. receiver dc parameter definitions 50 ? signal generator c l = 15 pf 50 ? signal generator a v id b r i o v o 50% 90% 10% 1.5 v 0 v v oh v ol t plh t phl t r t f input b input a output 1.5 v figure 11. receiver switching test circuit and waveforms 50 ? signal generator re b a 54 ? c l = 15 pf r 1 k ? 0 v v cc v cc d de re r 1.5 v t pzh t phz 3 v 0 v v oh v oh ?0.5 v gnd 1.5 v figure 12. receiver enable test circuit and waveforms, data output high
slls552d ? december 2002 ? revised april 2005 www.ti.com 12 50 ? signal generator re b a 54 ? c l = 15 pf r 1 k ? 5 v 0 v v cc d de re r 1.5 v t pzl t plz 3 v 0 v v cc v ol +0.5 v 1.5 v v ol figure 13. receiver enable test circuit and waveforms, data output low 1.5 v 50 ? signal generator re b a c l = 15 pf r 1 k ? switch down for v (a) = 1.5 v, switch up for v (a) = ?1.5 v v cc 1.5 v or ?1.5 v t r(wake) t r(standby) re 5 v 0 v 1.5 v v oh ?0.5 v v ol +0.5 v 3 v 0 v v oh v ol r figure 14. receiver standby and wake test circuit and waveforms bus data valid region bus data transition region bus data valid region t p(set) t p(reset) 200 mv ?40 mv ?200 mv ?1.5 v v oh v ol 1.5 v v id r figure 15. receiver active failsafe definitions and waveforms pulse generator, 15 s duration, 1% duty cycle 100 ? v test 0 v 15 s 1.5 ms ?v test figure 16. test circuit and waveforms, transient overvoltage test
slls552d ? december 2002 ? revised april 2005 www.ti.com 13 pin assignments 1 2 3 4 8 7 6 5 r re de d v cc b a gnd d or p package (top view) logic diagram positive logic 6 7 a b 3 4 2 1 de d re r typical characteristics figure 17 ?600 ?400 ?200 0 200 400 600 ?30 ?20 ?10 0 10 20 30 v cc = 0 v v cc = 5 v bus pin current ? bus pin voltage ? v hvd20, hvd23 bus pin current vs bus pin voltage a de = 0 v figure 18 ?150 ?100 ?50 0 50 100 150 ?30 ?20 ?10 0 10 20 30 v cc = 0 v v cc = 5 v bus pin current ? bus pin voltage ? v hvd21, hvd22, hvd24 bus pin current vs bus pin voltage a de = 0 v
slls552d ? december 2002 ? revised april 2005 www.ti.com 14 figure 19 40 45 50 55 60 65 70 75 0.1 1 10 100 hvd22 hvd21 hvd20 v cc = 5 v, de = re = v cc , load = 54 ? , 50 pf i cc ? supply current ? ma signaling rate ? mbps supply current vs signaling rate figure 20 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 0 1020304050607080 v cc = 5.5 v v cc = 5 v v cc = 4.5 v ? driver differential output voltage ? v driver differential output voltage vs driver load current v od i l ? driver load current ? ma figure 21 ?1 0 1 2 3 4 5 6 ?0.2 ?0.1 0 0.1 0.2 v cm = 25 v v cm = 0 v v cm = ?20 v v cm = 25 v v cm = 0 v v cm = ?20 v ? receiver output voltage ? v v o v id ? differential input voltage ? v receiver output voltage vs differental input volatge v it(?) v it(+) figure 22 0 5 10 15 20 25 30 100 120 140 160 180 200 hvd20 = 25 mbps peak-to-peak jitter ? ns cable length ? m hvd20, hvd23 peak-to-peak jitter vs cable length hvd23 = 25 mbps v cc = 5 v, t a = 25 c, v ic = 2.5 v, cable: belden 3105a
slls552d ? december 2002 ? revised april 2005 www.ti.com 15 figure 23 0 10 20 30 40 50 60 70 200 220 240 260 280 300 hvd21 = 10 mbps hvd20 = 10 mbps hvd23 = 10 mbps hvd24 = 10 mbps peak-to-peak jitter ? ns cable length ? m hvd20, hvd21, hvd23, hvd24 peak-to-peak jitter vs cable length v cc = 5 v, t a = 25 c, v ic = 2.5 v, cable: belden 3105a figure 24 10 30 50 70 90 110 130 3 3.5 4 4.5 5 hvd21: 500 m cable peak-to-peak jitter ? ns signaling rate ? mbps hvd20, hvd23 peak-to-peak jitter vs signaling rate v cc = 5 v, t a = 25 c, v ic = 2.5 v, cable: belden 3105a hvd24: 500 m cable
slls552d ? december 2002 ? revised april 2005 www.ti.com 16 application information theory of operation the hvd2x family of devices integrates a differential receiver and differential driver with additional features for improved performance in electrically-noisy, long-cable, or other fault-intolerant applications. the receiver hysteresis (typically 130 mv) is much larger than found in typical rs-485 transceivers. this helps reject spurious noise signals which would otherwise cause false changes in the receiver output state. slew rate limiting on the driver outputs (sn65hvd21, 22, and 24) reduces the high-frequency content of signal edges. this decreases reflections from bus discontinuities, and allows longer stub lengths between nodes and the main bus line. designers should consider the maximum signaling rate and cable length required for a specific application, and choose the transceiver best matching those requirements. when de is low, the differential driver is disabled, and the a and b outputs are in high-impedance states. when de is high, the differential driver is enabled, and drives the a and b outputs according to the state of the d input. when re is high, the dif ferential receiver output buf fer is disabled, and the r output is in a high-impedance state. when re is low, the differential receiver is enabled, and the r output reflects the state of the differential bus inputs on the a and b pins. if both the driver and receiver are disabled, (de low and re high) then all nonessential circuitry, including auxiliary functions such as failsafe and receiver equalization is placed in a low-power standby state. this reduces power consumption to less than 5 w. when either enable input is asserted, the circuitry again becomes active. in addition to the primary differential receiver, these devices incorporate a set of comparators and logic to implement an active receiver failsafe feature. these components determine whether the differential bus signal is valid. whenever the differential signal is close to zero volts (neither high nor low), a timer initiates, if the differential input remains within the transition range for more than 250 microseconds, the timer expires and set the receiver output to the high state. if a valid bus input (high or low) is received at any time, the receiver output reflects the valid bus state, and the timer is reset. b a 6 7 r 2 1 re de d 3 4 active filters + ? + ? 120 mv 120 mv timer 250 (v a ?v b ) : not high (v a ?v b ) : not low bus input invalid slew rate control standby s figure 25. function block diagram
slls552d ? december 2002 ? revised april 2005 www.ti.com 17 figure 26. hvd22 receiver operation with 20-v offset on input signal h(s) k 0 1?k 1 k 1 p 1 s p 1 1?k 2 k 2 p 2 s p 2 1?k 3 k 3 p 3 s p 3 k0 (dc loss) p1 (mhz) k1 p2 (mhz) k2 p3 (mhz) k3 similar to 160m of belden 3105a 0.95 0.25 0.3 3.5 0.5 15 1 similar to 250m of belden 3105a 0.9 0.25 0.4 3.5 0.7 12 1 similar to 500m of belden 3105a 0.8 0.25 0.6 2.2 1 8 1 similar to 1000m of belden 3105a 0.6 0.3 1 3 1 6 1 h(s) signal generator figure 27. cable attenuation model for jitter measurements
slls552d ? december 2002 ? revised april 2005 www.ti.com 18 integrated receiver equalization using the hvd23 figure 28 illustrates the benefits of integrated receiver equalization as implemented in the hvd23 transceiver. in this test setup, a differential signal generator applied a signal voltage at one end of the cable, which was belden 3105a twisted-pair shielded cable. the test signal was a pseudo-random bit stream (prbs) of nonreturn-to-zero (nrz) data. channel 1 (top) shows the eye-pattern of the differential voltage at the receiver inputs (after the cable attenuation). channel 2 (bottom) shows the output of the receiver. figure 28. hvd23 receiver performance at 25 mbps over 150 meter cable
slls552d ? december 2002 ? revised april 2005 www.ti.com 19 integrated receiver equalization using the hvd24 figure 29 illustrates the benefits of integrated receiver equalization as implemented in the hvd24 transceiver. in this test setup, a differential signal generator applied a signal voltage at one end of the cable, which was belden 3105a twisted-pair shielded cable. the test signal was a pseudo-random bit stream (prbs) of nonreturn-to-zero (nrz) data. channel 1 (top) shows the eye-pattern of the bit stream. channel 2 (middle) shows the eye-pattern of the differential voltage at the receiver inputs (after the cable attenuation). channel 3 (bottom) shows the output of the receiver. figure 29. hvd24 receiver performance at 5 mbps over 500 meter cable
slls552d ? december 2002 ? revised april 2005 www.ti.com 20 noise considerations for equalized receivers the simplest way of overcoming the effects of cable losses is to increase the sensitivity of the receiver. if the maximum attenuation of frequencies of interest is 20 db, increasing the receiver gain by a factor of ten compensates for the cable. however, this means that both signal and noise are amplified. therefore, the receiver with higher gain is more sensitive to noise and it is important to minimize differential noise coupling to the equalized receiver. differential noise is crated when conducted or radiated noise energy generates more voltage on one line of the differential pair than the other. for this to occur from conducted or electric far-field noise, the impedance to ground of the lines must differ. for noise frequency out to 50 mhz, the input traces can be treated as a lumped capacitance if the receiver is approximately 10 inches or less from the connector. therefore, matching impedance of the lines is accomplished by matching the lumped capacitance of each. the primary factors that affect the capacitance of a trace are in length, thickness, width, dielectric material, distance from the signal return path, stray capacitance, and proximity to other conductors. it is difficult to match each of the variables for each line of the differential pair exactly, but a reasonable effort to do so keeps the lines balanced and less susceptible to differential noise coupling. another source of differential noise is from near-field coupling. in this situation, an assumption of equal noise-source impedance cannot be made as in the far-field. familiarly known as crosstalk, more energy from a nearby signal is coupled to one line of the differential pair. minimization of this differential noise is accomplished by keeping the signal pair close together and physical separation from high-voltage, high-current, or high-frequency signals. in summary, follow these guidelines in board layout for keeping differential noise to a minimum. keep the differential input traces short. match the length, physical dimensions, and routing of each line of the pair. keep the lines close together. match components connected to each line. separate the inputs from high-voltage, high-frequency, or high-current signals.
packaging information orderable device status (1) package type package drawing pins package qty eco plan (2) lead/ball finish msl peak temp (3) sn65hvd20d active soic d 8 75 tbd cu nipdau level-1-220c-unlim sn65hvd20dr active soic d 8 2500 tbd cu nipdau level-1-220c-unlim sn65hvd20p active pdip p 8 50 pb-free (rohs) cu nipdau level-nc-nc-nc sn65hvd21d active soic d 8 75 tbd cu nipdau level-1-220c-unlim sn65hvd21dr active soic d 8 2500 tbd cu nipdau level-1-220c-unlim sn65hvd21p active pdip p 8 50 pb-free (rohs) cu nipdau level-nc-nc-nc sn65hvd22d active soic d 8 75 tbd cu nipdau level-1-220c-unlim sn65hvd22dr active soic d 8 2500 tbd cu nipdau level-1-220c-unlim sn65hvd22p active pdip p 8 50 pb-free (rohs) cu nipdau level-nc-nc-nc sn65hvd22pe4 active pdip p 8 50 pb-free (rohs) cu nipdau level-nc-nc-nc sn65hvd23d active soic d 8 75 tbd cu nipdau level-1-220c-unlim sn65hvd23dr active soic d 8 2500 tbd cu nipdau level-1-220c-unlim sn65hvd23p active pdip p 8 50 pb-free (rohs) cu nipdau level-nc-nc-nc sn65hvd23pe4 active pdip p 8 50 pb-free (rohs) cu nipdau level-nc-nc-nc SN65HVD24d active soic d 8 75 tbd cu nipdau level-1-220c-unlim SN65HVD24dr active soic d 8 2500 tbd cu nipdau level-1-220c-unlim SN65HVD24p active pdip p 8 50 pb-free (rohs) cu nipdau level-nc-nc-nc SN65HVD24pe4 active pdip p 8 50 pb-free (rohs) cu nipdau level-nc-nc-nc (1) the marketing status values are defined as follows: active: product device recommended for new designs. lifebuy: ti has announced that the device will be discontinued, and a lifetime-buy period is in effect. nrnd: not recommended for new designs. device is in production to support existing customers, but ti does not recommend using this part in a new design. preview: device has been announced but is not in production. samples may or may not be available. obsolete: ti has discontinued the production of the device. (2) eco plan - the planned eco-friendly classification: pb-free (rohs) or green (rohs & no sb/br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. tbd: the pb-free/green conversion plan has not been defined. pb-free (rohs): ti's terms "lead-free" or "pb-free" mean semiconductor products that are compatible with the current rohs requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. where designed to be soldered at high temperatures, ti pb-free products are suitable for use in specified lead-free processes. green (rohs & no sb/br): ti defines "green" to mean pb-free (rohs compatible), and free of bromine (br) and antimony (sb) based flame retardants (br or sb do not exceed 0.1% by weight in homogeneous material) (3) msl, peak temp. -- the moisture sensitivity level rating according to the jedec industry standard classifications, and peak solder temperature. important information and disclaimer: the information provided on this page represents ti's knowledge and belief as of the date that it is provided. ti bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. efforts are underway to better integrate information from third parties. ti has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on package option addendum www.ti.com 4-nov-2005 addendum-page 1
incoming materials and chemicals. ti and ti suppliers consider certain information to be proprietary, and thus cas numbers and other limited information may not be available for release. in no event shall ti's liability arising out of such information exceed the total purchase price of the ti part(s) at issue in this document sold by ti to customer on an annual basis. package option addendum www.ti.com 4-nov-2005 addendum-page 2
mechanical data mpdi001a january 1995 revised june 1999 post office box 655303 ? dallas, texas 75265 p (r-pdip-t8) plastic dual-in-line 8 4 0.015 (0,38) gage plane 0.325 (8,26) 0.300 (7,62) 0.010 (0,25) nom max 0.430 (10,92) 4040082/d 05/98 0.200 (5,08) max 0.125 (3,18) min 5 0.355 (9,02) 0.020 (0,51) min 0.070 (1,78) max 0.240 (6,10) 0.260 (6,60) 0.400 (10,60) 1 0.015 (0,38) 0.021 (0,53) seating plane m 0.010 (0,25) 0.100 (2,54) notes: a. all linear dimensions are in inches (millimeters). b. this drawing is subject to change without notice. c. falls within jedec ms-001 for the latest package information, go to http://www.ti.com/sc/docs/package/pkg_info.htm

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