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an important notice at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. advance information for pre-production products; subject to change without notice. TPS3840 snvsb03 ? december 2018 TPS3840 nano power, high input voltage supervisor with mr and programmable delay 1 1 features 1 ? wide operating voltage : 1.5 v to 10 v ? nano supply current : 350 na (typical) ? fixed threshold voltage (v it- ) ? threshold from 1.6 v to 4.9 v in 0.1-v steps ? high accuracy: 1% (typical) ? built-in hysteresis (v it+ ) ? 1.6 v < v it- 3.1 v = 100 mv (typical) ? 3.2 v v it- < 4.9 v = 200 mv (typical) ? reset time delay (t d ): capacitor-based programmable ? minimum time delay: 80 s (maximum) without capacitor ? active-low manual reset ( mr) ? three output topologies: ? TPS3840dl: open-drain, active-low ( reset) ? TPS3840pl: push-pull, active-low ( reset) ? TPS3840ph: push-pull, active-high (reset) ? wide temperature range: ? 40 c to +125 c ? package: sot23-5 (dbv) 2 applications ? grid infrastructure: circuit breaker, smart meter, other monitoring and protection equipment ? factory automation: field transmitter, plc. ? building automation: fire safety, smoke detector, and hvac ? electronic point of sale ? portable, battery-powered systems 3 description the TPS3840 family of voltage supervisors or reset ics can operate at high voltage levels while maintaining very low quiescent current across the whole v dd and temperature range. TPS3840 offers best combination of low power consumption, high accuracy and low propagation delay (t p_hl = 30 s typical). reset output signal is asserted when the voltage at vdd drops below the negative voltage threshold (v it- ) or when manual reset is pulled to a low logic (v mr_l ). reset signal is cleared when v dd rise above v it- plus hysteresis (v it+ ) and manual reset ( mr) is floating or above v mr_h and the reset time delay (t d ) expires. reset time delay can be programmed by connecting a capacitor between ct pin and ground. for a fast reset ct pin can be left floating. additional features: low power-on reset voltage (v por ), built-in glitch immunity protection for mr and vdd, built-in hysteresis, low open-drain output leakage current (i lkg(od) ). TPS3840 is a perfect voltage monitoring solution for industrial applications and battery-powered / low power applications. device information (1) part number package body size (nom) TPS3840 sot-23 (5) ( dbv ) 2.90 mm 1.60 mm (1) for package details, see the mechanical drawing addendum at the end of the data sheet. typical application circuit TPS3840 typical supply current TPS3840pl18 mr vdd gnd ct reset TPS3840dl30 vdd gnd reset mr ct microcontroller v core v i/o 3.3v 1.8v reset vdd (v) idd (a) 1 2 3 4 5 6 7 8 9 10 0 0.1 0.2 0.3 0.4 0.5 iddv dl49 pl49 ph49 advance information technical documents support &community ordernow productfolder tools & software
2 TPS3840 snvsb03 ? december 2018 www.ti.com product folder links: TPS3840 submit documentation feedback copyright ? 2018, texas instruments incorporated table of contents 1 features .................................................................. 1 2 applications ........................................................... 1 3 description ............................................................. 1 4 revision history ..................................................... 2 5 device comparison table ..................................... 3 6 pin configuration and functions ......................... 4 7 specifications ......................................................... 5 7.1 absolute maximum ratings ...................................... 5 7.2 esd ratings ............................................................ 5 7.3 recommended operating conditions ....................... 5 7.4 thermal information .................................................. 5 7.5 electrical characteristics ........................................... 6 7.6 timing requirements ................................................ 7 7.7 typical characteristics .............................................. 9 8 detailed description ............................................ 14 8.1 overview ................................................................. 14 8.2 functional block diagram ....................................... 14 8.3 feature description ................................................. 14 8.4 device functional modes ........................................ 17 9 application and implementation ........................ 18 9.1 application information ............................................ 18 9.2 typical application ................................................. 18 10 power supply recommendations ..................... 25 11 layout ................................................................... 25 11.1 layout guidelines ................................................. 25 11.2 layout example .................................................... 25 12 device and documentation support ................. 26 12.1 device nomenclature ............................................ 26 12.2 community resources .......................................... 27 12.3 trademarks ........................................................... 27 12.4 electrostatic discharge caution ............................ 27 12.5 glossary ................................................................ 27 13 mechanical, packaging, and orderable information ........................................................... 27 4 revision history note: page numbers for previous revisions may differ from page numbers in the current version. date revision notes december 2018 * initial release advance information
3 TPS3840 www.ti.com snvsb03 ? december 2018 product folder links: TPS3840 submit documentation feedback copyright ? 2018, texas instruments incorporated (1) TPS3840dl: open-drain, active-low ( reset) (2) TPS3840pl: push-pull, active-low ( reset) (3) TPS3840ph: push-pull, active-high (reset) 5 device comparison table device comparison table shows the variants planned to release at rtm, however other voltages from table 3 at the end of datasheet can be sample upon request, please contact ti sales representative for details. part number output topology threshold (v it- ) (v) hysteresis (mv) TPS3840dl20 (1) open-drain, active-low 2 100 TPS3840pl25 (2) push-pull, active-low 2.5 100 TPS3840pl28 (2) push-pull, active-low 2.8 100 TPS3840ph30 (3) push-pull, active-high 3.0 100 TPS3840dl27 (1) open-drain, active-low 2.7 100 TPS3840dl29 (1) open-drain, active-low 2.9 100 advance information
4 TPS3840 snvsb03 ? december 2018 www.ti.com product folder links: TPS3840 submit documentation feedback copyright ? 2018, texas instruments incorporated 6 pin configuration and functions dbv package 5-pin wson TPS3840pl, TPS3840dl top view dbv package 5-pin wson TPS3840ph top view pin functions pin i/o description name TPS3840pl, TPS3840dl TPS3840ph reset n/a 1 o active-high output reset signal: this pin is driven high when either the mr pin is driven to a logic low or vdd voltage falls below the negative voltage threshold (v it- ). reset remains high (asserted) for the delay time period (t d ) after both mr is floating or above v mr_l and vdd voltage rise above v it+. reset 1 n/a o active-low output reset signal: this pin is driven logic when either the mr pin is driven to a logic low or vdd voltage falls below the negative voltage threshold (v it- ). reset remains low (asserted) for the delay time period (t d ) after both mr is floating or above v mr_l and vdd voltage rise above v it+. vdd 2 2 i input supply voltage. TPS3840 monitors vdd voltage gnd 3 3 _ ground mr / nc 4 4 i manual reset . pull this pin to a logic low (v mr_l ) to assert a reset signal in the output pin. after the mr pin is left floating or pull to v mr_h the output goes to the nominal state after the reset delay time(t d ) expires. mr can be left floating when not in use. nc stands for "no connection" or floating. ct 5 5 - capacitor time delay pin . the ct pin offers a user-programmable delay time. connect an external capacitor on this pin to adjust time delay. when not in use leave pin floating for the smallest fixed time delay. 1 reset 2 vdd 3 gnd 4 mr 5 ct not to scale / nc advance information 1 reset 2 vdd 3 gnd 4 mr 5 ct not to scale / nc
5 TPS3840 www.ti.com snvsb03 ? december 2018 product folder links: TPS3840 submit documentation feedback copyright ? 2018, texas instruments incorporated (1) stresses beyond those listed under absolute maximum rating may cause permanent damage to the device. these are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under recommended operating condition . exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. (2) if the logic signal driving mr is less than v dd , then additional current flows into v dd and out of mr. v mr should not be higher than v dd. (3) as a result of the low dissipated power in this device, it is assumed that t j = t a . 7 specifications 7.1 absolute maximum ratings over operating free-air temperature range, unless otherwise noted (1) min max unit voltage vdd ? 0.3 12 v reset (TPS3840pl) ? 0.3 v dd + 0.3 reset (TPS3840ph) ? 0.3 v dd + 0.3 reset (TPS3840dl) ? 0.3 12 mr (2) ? 0.3 12 ct ? 0.3 5.5 current reset pin and reset pin 70 ma temperature (3) operating junction temperature, t j ? 40 125 c storage, t stg ? 65 150 (1) jedec document jep155 states that 500-v hbm allows safe manufacturing with a standard esd control process. (2) jedec document jep157 states that 250-v cdm allows safe manufacturing with a standard esd control process. 7.2 esd ratings value unit v (esd) electrostatic discharge human body model (hbm), per ansi/esda/jedec js- 001 (1) 2000 v charged device model (cdm), per jedec specification jesd22-c101 (2) 750 (1) if the logic signal driving mr is less than v dd , then additional current flows into v dd and out of mr. v mr should not be higher than v dd. 7.3 recommended operating conditions over operating free-air temperature range (unless otherwise noted) min nom max unit v dd input supply voltage 1.5 10 v v reset , v reset reset pin and reset pin voltage 0 10 v i reset , i reset reset pin and reset pin current 0 5 ma t j junction temperature (free air temperature) ? 40 125 c v mr (1) manual reset pin voltage 0 v dd v (1) for more information about traditional and new thermal metrics, see the semiconductor and ic package thermal metrics application report. 7.4 thermal information thermal metric (1) TPS3840 unit dbv (sot23-5) 5 pins r ja junction-to-ambient thermal resistance 187.5 c/w r jc(top) junction-to-case (top) thermal resistance 109.2 c/w r jb junction-to-board thermal resistance 92.8 c/w jt junction-to-top characterization parameter 35.4 c/w jb junction-to-board characterization parameter 92.5 c/w r jc(bot) junction-to-case (bottom) thermal resistance n/a c/w advance information
6 TPS3840 snvsb03 ? december 2018 www.ti.com product folder links: TPS3840 submit documentation feedback copyright ? 2018, texas instruments incorporated (1) v it- threshold voltage range from 1.6 v to 4.9 v in 100 mv steps, for released versions see device voltage thresholds table. (2) v it+ = v hys + v it- (3) if the logic signal driving mr is less than vdd, then additional current flows into vdd and out of mr (4) v por is the minimum v dd voltage level for a controlled output state. v dd slew rate 100mv/ s 7.5 electrical characteristics at 1.5 v v dd 10 v, ct = mr = open, reset pull-up resistor (r pull-up ) = 100 k to vdd, output reset load (c load ) = 10 pf and over the operating free-air temperature range ? 40 c to 125 c, unless otherwise noted. typical values are at t j = 25 c. parameter test conditions min typ max unit common parameters v dd input supply voltage 1.5 10 v v it- negative-going input threshold accuracy (1) -40 c to 125 c ? 2.5 1 2.5 % -40 c to 105 c ? 1.5 1 1.5 % v hys hysteresis on v it- pin v it- = 1.6 v to 3.1 v 75 100 125 mv v it- = 3.2 v to 4.9 v 150 200 250 mv i dd supply current into vdd pin vdd = 1.5 v < v dd < 10 v vdd > v it+ (2) t a = -40 c to 125 c 0.35 1 a i dd vdd = 1.5 v < v dd < 5.5 v vdd > v it+ (2) t a = -40 c to 85 c 350 500 na v mr_l manual reset logic low input (3) 300 mv v mr_h manual reset logic high input (3) 0.8v dd v r mr manual reset internal pull-up resistance 100 k r ct ct pin internal resistance 500 k variant-specific parameters v por TPS3840pl (push-pull active-low) power on reset voltage (4) v ol(max) = 200 mv i out(sink) = 200 na 300 mv v ol low level output voltage 1.5 v < v dd < 5 v v dd < v it- i out(sink) = 2 ma 200 mv v oh high level output voltage 1.5 v < v dd < 5 v v dd > v it+ (2) i out(source ) = 2 ma 0.8v dd v v oh 5 v < v dd < 10 v v dd > v it+ (2) i out(source) = 5 ma 0.8v dd v v por TPS3840ph (push-pull active-high) power on reset voltage (4) v oh , i out(source) = 500 na 920 mv v ol low level output voltage 1.5 v < v dd < 5 v v dd > v it+ (2) i out(sink) = 2 ma 200 mv v ol 1.5 v < v dd < 5 v v dd > v it+ (2) i out(sink) = 5 ma 200 mv v oh high level output voltage 1.5 v < v dd < 5 v, v dd < v it- , i out(source) = 2 ma 0.8v dd v v por TPS3840dl (open-drain) power on reset voltage (4) v ol(max) = 0.2 v i out (sink) = 5.6 ua 900 mv v ol low level output voltage 1.5 v < v dd < 5 v v dd < v it- i out(sink) = 2 ma 200 mv i lkg(od) open-drain output leakage current reset pin in high impedance, v dd = v reset = 5.5 v v it+ < v dd 90 na advance information
7 TPS3840 www.ti.com snvsb03 ? december 2018 product folder links: TPS3840 submit documentation feedback copyright ? 2018, texas instruments incorporated (1) when vdd starts from less than the specified minimum v dd and then exceeds v it- , reset is release after the startup delay (t strt ), a capacitor at ct pin will add t d delay to t strt time (2) t p_hl measured from threhold trip point (v it- ) to v ol for active low variants and v oh for active high variants. (3) overdrive % = [(v dd / v it- ) - 1] 100% 7.6 timing requirements at 1.5 v v dd 10 v, ct = mr = open, reset pull-up resistor (r pull-up ) = 100 k to vdd, output reset load (c load ) = 10 pf and over the operating free-air temperature range ? 40 c to 125 c, unless otherwise noted. typical values are at t j = 25 c. parameter test conditions min typ max unit t strt startup delay (1) ct pin open tbd 220 tbd s t p_hl propagation detect delay for vdd falling below v it- v dd = v it+ to (v it- ) - 10% (2) 30 50 s t d reset time delay ct pin = open 80 s ct pin = 10 nf 6.2 ms ct pin = 1 f 619 ms t gi_vit- glitch immunity v it- 5% v it- overdrive (3) 10 s t mr_pw mr pin pulse duration to initiate reset 300 ns t mr_res propagation delay from mr low to reset v dd = 4.5 v, mr < v mr_l 700 ns t mr_td delay from release mr to deasert reset v dd = 4.5 v, mr = v mr_l to v mr_h t d ms (1) t d (no cap) is included in t strt time delay. if t d delay is programmed by an external capacitor connected to ct pin then t d programmed time will be added to the startup time, vdd slew rate = 100 mv / s. (2) open-drain timing diagram assumes pull-up resistor is connected to reset figure 3. timing diagram TPS3840dl (open-drain active-low) advance information t d t p_hl vdd v por v oh v ol v it+ v dd(min) v it- reset t strt + t d t p_hl t strt + t d
8 TPS3840 snvsb03 ? december 2018 www.ti.com product folder links: TPS3840 submit documentation feedback copyright ? 2018, texas instruments incorporated (3) t d (no cap) is included in t strt time delay. if t d delay is programmed by an external capacitor connected to ct pin, then t d programmed time will be added to the startup time. vdd slew rate = 100 mv / s. figure 4. timing diagram TPS3840pl (push-pull active-low) (4) t d (no cap) is included in t strt time delay. if t d delay is programmed by an external capacitor connected to ct pin, then t d programmed time will be added to the total startup time. vdd slew rate = 100 mv / s. figure 5. timing diagram TPS3840ph (push-pull active-high) t d t p_hl vdd v por v oh v ol v it+ v dd(min) v it- reset t strt + t d t p_hl t strt + t d t d t p_hl vdd v por v oh v ol v it+ v dd(min) v it- reset t p_hl t strt + t d t strt + t d advance information
9 TPS3840 www.ti.com snvsb03 ? december 2018 product folder links: TPS3840 submit documentation feedback copyright ? 2018, texas instruments incorporated 7.7 typical characteristics typical characteristics show the typical performance of the TPS3840 device. test conditions are t j = 25 c, v dd = 3.3 v, r pull- up = 100 k ? , c load = 50 pf, unless otherwise noted. figure 6. supply current vs supply voltage for TPS3840dl49 figure 7. supply current vs supply voltage for TPS3840pl49 figure 8. supply current vs supply voltage for TPS3840ph49 figure 9. negative-going input threshold accuracy over temperature for TPS3840dlxx figure 10. negative-going input threshold accuracy over temperature for TPS3840plxx figure 11. negative-going input threshold accuracy over temperature for TPS3840phxx temperature (c) vit- accuracy (%) -40 -20 0 20 40 60 80 100 120 140 -0.6 -0.5 -0.4 -0.3 -0.2 -0.1 0 0.1 0.2 0.3 0.4 0.5 0.6 vit_ pl16 pl28 pl49 temperature (c) vit- accuracy (%) -40 -20 0 20 40 60 80 100 120 140 -0.6 -0.5 -0.4 -0.3 -0.2 -0.1 0 0.1 0.2 0.3 0.4 0.5 0.6 vit_ ph16 ph30 ph49 advance information vdd (v) idd (a) 1 2 3 4 5 6 7 8 9 10 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5 0.55 0.6 iddv 25c -40c 125c vdd (v) idd (a) 1 2 3 4 5 6 7 8 9 10 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5 0.55 0.6 iddv 25c -40c 125c temperature (c) vit- accuracy (%) -40 -20 0 20 40 60 80 100 120 140 -0.6 -0.5 -0.4 -0.3 -0.2 -0.1 0 0.1 0.2 0.3 0.4 0.5 0.6 vit_ dl16 dl29 dl49 vdd (v) idd (a) 1 2 3 4 5 6 7 8 9 10 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5 0.55 0.6 iddv 25c -40c 125c
10 TPS3840 snvsb03 ? december 2018 www.ti.com product folder links: TPS3840 submit documentation feedback copyright ? 2018, texas instruments incorporated typical characteristics (continued) typical characteristics show the typical performance of the TPS3840 device. test conditions are t j = 25 c, v dd = 3.3 v, r pull- up = 100 k ? , c load = 50 pf, unless otherwise noted. figure 12. input threshold v it- hysteresis accuracy for TPS3840dlxx figure 13. input threshold v it- hysteresis accuracy for TPS3840plxx figure 14. input threshold v it- hysteresis accuracy for TPS3840phxx figure 15. low level output voltage over temperature for TPS3840dl49 figure 16. low level output voltage over temperature for TPS3840pl49 figure 17. low level output voltage over temperature for TPS3840ph49 temperature (c) vhys accuracy (%) -40 -20 0 20 40 60 80 100 120 140 -20 -15 -10 -5 0 5 10 15 20 vhys ph16 ph30 ph49 vdd (v) vol (v) 1.5 2 2.5 3 3.5 4 4.5 5 0.015 0.02 0.025 0.03 0.035 0.04 0.045 0.05 0.055 volv 25c -40c 125c advance information vdd (v) vol (v) 5 5.5 6 6.5 7 7.5 8 8.5 9 9.5 10 10.5 0.015 0.02 0.025 0.03 0.035 0.04 0.045 0.05 0.055 0.06 0.065 0.07 0.075 0.08 0.085 0.09 volv 25c -40c 125c temperature (c) vhys accuracy (%) -40 -20 0 20 40 60 80 100 120 140 -20 -15 -10 -5 0 5 10 15 20 vhys dl16 dl29 dl49 vdd (v) vol (v) 1.5 2 2.5 3 3.5 4 4.5 5 0.015 0.02 0.025 0.03 0.035 0.04 0.045 0.05 0.055 volv 25c -40c 125c temperature (c) vhys accuracy (%) -40 -20 0 20 40 60 80 100 120 140 -20 -15 -10 -5 0 5 10 15 20 vhys pl16 pl28 pl49
11 TPS3840 www.ti.com snvsb03 ? december 2018 product folder links: TPS3840 submit documentation feedback copyright ? 2018, texas instruments incorporated typical characteristics (continued) typical characteristics show the typical performance of the TPS3840 device. test conditions are t j = 25 c, v dd = 3.3 v, r pull- up = 100 k ? , c load = 50 pf, unless otherwise noted. figure 18. high level output voltage over temperature for TPS3840pl49 figure 19. high level output voltage over temperature for TPS3840ph49 figure 20. manual reset logic low voltage threshold over temperature for TPS3840dlxx figure 21. manual reset logic low voltage threshold over temperature for TPS3840plxx figure 22. manual reset logic low voltage threshold over temperature for TPS3840phxx figure 23. manual reset logic high voltage threshold over temperature for TPS3840dlxx temperature (c) v_mr_l (v) -40 -20 0 20 40 60 80 100 120 140 0.5 0.75 1 1.25 1.5 1.75 2 2.25 2.5 2.75 mr_l ph16 ph230 ph49 temperature (c) v_mr_h (v) -40 -20 0 20 40 60 80 100 120 140 0.75 1 1.25 1.5 1.75 2 2.25 2.5 2.75 mr_h dl16 dl29 dl49 temperature (c) v_mr_l (v) -40 -20 0 20 40 60 80 100 120 140 0.5 0.75 1 1.25 1.5 1.75 2 2.25 2.5 2.75 mr_l dl16 dl29 dl49 temperature (c) v_mr_l (v) -40 -20 0 20 40 60 80 100 120 140 0.5 0.75 1 1.25 1.5 1.75 2 2.25 2.5 2.75 mr_l pl16 pl28 pl49 vdd (v) voh (v) 1.5 2 2.5 3 3.5 4 4.5 5 1 1.5 2 2.5 3 3.5 4 4.5 5 vohv 25c -40c 125c advance information vdd (v) voh (v) 1.5 2 2.5 3 3.5 4 4.5 5 1 1.5 2 2.5 3 3.5 4 4.5 5 vohv 25c -40c 125c
12 TPS3840 snvsb03 ? december 2018 www.ti.com product folder links: TPS3840 submit documentation feedback copyright ? 2018, texas instruments incorporated typical characteristics (continued) typical characteristics show the typical performance of the TPS3840 device. test conditions are t j = 25 c, v dd = 3.3 v, r pull- up = 100 k ? , c load = 50 pf, unless otherwise noted. figure 24. manual reset logic high voltage threshold over temperature for TPS3840plxx figure 25. manual reset logic high voltage threshold over temperature for TPS3840phxx figure 26. glitch immunity on v it- vs overdrive (data taken with TPS3840pl28) figure 27. ct pin internal resistance over temperature figure 28. startup delay over temperature figure 29. reset time delay with no capacitor over temperature temperature (c) v_mr_h (v) -40 -20 0 20 40 60 80 100 120 140 0.75 1 1.25 1.5 1.75 2 2.25 2.5 2.75 mr_h ph16 ph30 ph49 temperature (c) v_mr_h (v) -40 -20 0 20 40 60 80 100 120 140 0.75 1 1.25 1.5 1.75 2 2.25 2.5 2.75 mr_h pl16 pl28 pl49 temperature (c) r_ct (kohm) -40 -20 0 20 40 60 80 100 120 140 458 460 462 464 466 468 470 472 474 476 478 rctv dl49 pl49 ph49 advance information overdrive (%) glitch immunity (s) 5 10 15 20 25 30 35 40 45 50 12 13 14 15 16 17 18 19 20 21 22 glit 25c -40c 125c temperature (c) t_d no capacitor (s) -40 -20 0 20 40 60 80 100 120 140 3 6 9 12 15 dela dl49 pl49 ph49 temperature (c) t_strt (s) -40 -20 0 20 40 60 80 100 120 140 170 175 180 185 190 195 200 205 210 215 star dl49 pl49 ph49
13 TPS3840 www.ti.com snvsb03 ? december 2018 product folder links: TPS3840 submit documentation feedback copyright ? 2018, texas instruments incorporated typical characteristics (continued) typical characteristics show the typical performance of the TPS3840 device. test conditions are t j = 25 c, v dd = 3.3 v, r pull- up = 100 k ? , c load = 50 pf, unless otherwise noted. figure 30. reset time delay vs capacitor value (data taken with TPS3840pl16) figure 31. reset time delay vs small capacitor values (data taken with TPS3840pl16) figure 32. reset time delay vs large capacitor values (data taken with TPS3840pl16) figure 33. propagation detect time delay for vdd falling below v it- (high-to-low) over temperature figure 34. propagation time delay from mr asserted to reset over temperature figure 35. propagation time delay from mr release to deasserted reset over temperature temperature (c) t_mr_res (ns) -40 -20 0 20 40 60 80 100 120 140 415 420 425 430 435 440 445 450 455 460 465 mr_r dl49 pl49 ph49 temperature (c) t_p_hl (s) -40 -20 0 20 40 60 80 100 120 140 14.75 15 15.25 15.5 15.75 16 16.25 16.5 16.75 17 17.25 tphl dl49 pl49 ph49 capacitor (f) t_d (ms) 0.01 0.02 0.05 0.1 0.2 0.3 0.5 1 2 3 4 5 6 7 10 0 500 1000 1500 2000 2500 3000 3500 4000 4500 5000 dela 25c -40c 125c temperature (c) t_mr_ td (s) -40 -20 0 20 40 60 80 100 120 140 3.1 3.15 3.2 3.25 3.3 3.35 3.4 3.45 3.5 3.55 mrde dl49 pl49 ph49 advance information capacitor value (f) td with capacitor (s) 1 2 3 4 5 6 7 8 9 10 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 dela 25c -40c 125c capacitor value (f) td with capacitor (ms) 0.01 0.02 0.03 0.05 0.07 0.1 0.2 0.3 0.5 0.7 1 0 100 200 300 400 500 600 dela 25c -40c 125c
14 TPS3840 snvsb03 ? december 2018 www.ti.com product folder links: TPS3840 submit documentation feedback copyright ? 2018, texas instruments incorporated 8 detailed description 8.1 overview the TPS3840 is a family of wide vdd and nano-quiescent current voltage detectors with fixed threshold voltage. TPS3840 features include programable reset time delay using external capacitor, active-low manual reset, 1% typical monitor threshold accuracy with hysteresis and glitch immunity. fixed negative threshold voltages (v it- ) can be factory set from 1.6 v to 4.9 v (see the device comparison table for available options). TPS3840 is available in sot-23 5 pin industry standard package. 8.2 functional block diagram 8.3 feature description 8.3.1 input voltage (vdd) vdd pin is monitored by the internal comparator to indicate when vdd falls below the fixed threshold voltage. vdd also functions as the supply for the internal bandgap, internal regulator, state machine, buffers and other control logic blocks. good design practice involve placing a 0.1 uf to 1 uf bypass capacitor at vdd input for noisy applications to ensure enough charge is available for the device to power up correctly. advance information + v ref vdd reset reset gnd vdd reset logic timer ct mr / nc vdd r mr push-pull version only copyright ? 2018, texas instruments incorporated r ct subreg
15 TPS3840 www.ti.com snvsb03 ? december 2018 product folder links: TPS3840 submit documentation feedback copyright ? 2018, texas instruments incorporated feature description (continued) 8.3.1.1 vdd hysteresis the internal comparator has built-in hysteresis to avoid erroneous output reset release. if the voltage at the vdd pin falls below v it- the output reset is asserted. when the voltage at the vdd pin goes above v it- plus hysteresis (v hys ) the output reset is deasserted after t d delay. figure 36. hysteresis diagram 8.3.1.2 vdd transient immunity the TPS3840 is immune to quick voltage transients or excursion on vdd. sensitivity to transients depends on both pulse duration and overdrive. overdrive is defined by how much vdd deviates from the specified threshold. threshold overdrive is calculated as a percent of the threshold in question, as shown in equation 1 . overdrive = | (v dd / v it- ? 1) 100% | (1) figure 37. overdrive vs pulse duration 8.3.2 user-programmable reset time delay the reset time delay can be set to a minimum value of 80 s by leaving the ct pin floating, or a maximum value of approximately 6.2 seconds by connecting 10 f delay capacitor. the reset time delay (t d ) can be programmed by connecting a capacitor no larger than 10 f between ct pin and gnd. the relationship between external capacitor (c ct_ext ) at ct pin and the time delay is given by equation 2 . t d = -ln (0.29) x r ct x c ct_ext + t d (no cap) (2) equation 2 is simplified to equation 3 by plugging r ct and t d(no cap) given in electrical characteristics section : t d = 618937 x c ct_ext + 80 s (3) equation 4 solves for external capacitor value (c ct_ext ) c ct_ext = (t d - 80 s) 618937 (4) the recommended maximum delay capacitor for the TPS3840 is limited to 10 f as this ensures there is enough time for the capacitor to fully discharge when the reset condition occurs. when a voltage fault occurs, the previously charged up capacitor discharges, and if the monitored voltage returns from the fault condition before the delay capacitor discharges completely, the delay capacitor will begin charging from a voltage above zero and the reset delay will be shorter than expected. larger delay capacitors can be used so long as the capacitor has enough time to fully discharge during the duration of the voltage fault. vdd hystersis width v it+ v it- reset reset vdd hystersis width v it+ v it- advance information overdrive pulse duration vdd v it- v it+
16 TPS3840 snvsb03 ? december 2018 www.ti.com product folder links: TPS3840 submit documentation feedback copyright ? 2018, texas instruments incorporated feature description (continued) 8.3.3 manual reset ( mr) input the manual reset ( mr) input allows a processor gpio or other logic circuits to initiate a reset. a logic low on mr with pulse duration longer than t mr_res will causes reset output to assert. after mr returns to a logic high (v mr_h ) and vdd is above v it+ , reset is deasserted after the user programmed reset time delay (t d ) expires. if mr is not controlled externally, then mr can be left disconnected. if the logic signal controlling mr is less than vdd, then additional current flows from vdd into mr internally. for minimum current consumption, drive mr to either vdd or gnd. v mr should not be higher than vdd voltage. figure 38. timing diagram mr and reset (TPS3840dl) 8.3.4 output logic 8.3.4.1 reset output, active-low reset (active-low) applies to TPS3840d l (open-drain) and TPS3840p l (push-pull) hence the " l " in the device name. reset remains high (deasserted) as long as vdd is above the negative threshold (v it- ) and the mr pin is floating or above v mr_h . if vdd falls below the negative threshold (v it- ) or if mr is driven low, then reset is asserted. when mr is again logic high or floating and vdd rise above v it+ , the delay circuit will hold reset low for the specified reset time delay (t d ). when the reset time delay has elapsed, the reset pin goes back to logic high voltage (v oh ). the TPS3840dl (open-drain) version, denoted with " d " in the device name, requires a pull-up resistor to hold reset pin high. connect the pull-up resistor to the desired pull-up voltage source and reset can be pulled up to any voltage up to 10 v independent of the vdd voltage. to ensure proper voltage levels, give some consideration when choosing the pull-up resistor values. the pull-up resistor value determines the actual v ol , the output capacitive loading, and the output leakage current (i lkg(od) ). the push-pull variants (TPS3840 p l and TPS3840 p h), denoted with " p " in the device name, does not require a pull-up resistor 8.3.4.2 reset output, active-high reset (active-high), denoted with no bar above the pin label, applies only to TPS3840ph push-pull active-high version. reset remains low (deasserted) as long as vdd is above the threshold (v it- ) and the manual reset signal ( mr) is logic high or floating. if vdd falls below the negative threshold (v it- ) or if mr is driven low, then reset is asserted driving the reset pin to high voltage (v oh ). when mr is again logic high and vdd is above v it+ the delay circuit will hold reset high for the specified reset time delay (t d ). when the reset time delay has elapsed, the reset pin goes back to low voltage (v ol ) v it+ t p_hl v hys t d v it+ v hys v it- t mr_td v mr_l t mr_res t mr_pw reset not asserted pulse width less than t mr_pw reset mr vdd v mr_h v it- advance information
17 TPS3840 www.ti.com snvsb03 ? december 2018 product folder links: TPS3840 submit documentation feedback copyright ? 2018, texas instruments incorporated (1) when v dd falls below v dd(min) , undervoltage-lockout (uvlo) takes effect and output reset is held asserted until v dd falls below v por . 8.4 device functional modes table 1 summarizes the various functional modes of the device. logic high is represented by "h" and logic low is represented by "l". table 1. truth table vdd mr reset reset vdd < v por ignored undefined undefined v por < v dd < v it- (1) ignored h l vdd v it- l h l vdd v it- h l h vdd v it- floating l h 8.4.1 normal operation (v dd > v dd(min) ) when vdd is greater than v dd(min) , the reset signal is determined by the voltage on the vdd pin with respect to the trip point (v it- ) and the logic state of mr. ? mr high: the reset signal corresponds to vdd with respect to the threshold voltage. ? mr low: in this mode, the reset is asserted regardless of the threshold voltage. 8.4.2 vdd between vpor and v dd(min) when the voltage on vdd is less than the v dd(min) voltage, and greater than the power-on-reset voltage (v por ), the reset signal is asserted. 8.4.3 below power-on-reset (v dd < v por ) when the voltage on vdd is lower than v por , the device does not have enough bias voltage to internally pull the asserted output low or high and reset voltage level is undefined. advance information
18 TPS3840 snvsb03 ? december 2018 www.ti.com product folder links: TPS3840 submit documentation feedback copyright ? 2018, texas instruments incorporated 9 application and implementation note information in the following applications sections is not part of the ti component specification, and ti does not warrant its accuracy or completeness. ti ? s customers are responsible for determining suitability of components for their purposes. customers should validate and test their design implementation to confirm system functionality. 9.1 application information the following sections describe in detail how to properly use this device, depending on the requirements of the final application. 9.2 typical application 9.2.1 design 1: dual rail monitoring with power-up sequencing a typical application for the TPS3840 is voltage rail monitoring and power-up sequencing as shown in figure 39 . the TPS3840 can be used to monitor any rail above 1.6 v. in this design application, two tps3480 devices monitor two separate voltage rails and sequences the rails upon power-up. the TPS3840pl30 is used to monitor the 3.3-v main power rail and the TPS3840dl16 is used to monitor the 1.8-v rail provided by the ldo for other system peripherals. the reset output of the TPS3840pl30 is connected to the enable input of the ldo. a reset event is initiated on either voltage supervisor when the vdd voltage is less than v it- or when mr is driven low by an external source. figure 39. TPS3840 voltage rail monitor and power-up sequencer design block diagram 9.2.1.1 design requirements this design requires voltage supervision on two separate rails: 3.3-v and 1.8-v rails. the voltage rail needs to sequence upon power up with the 3.3-v rail coming up first followed by the 1.8-v rail at least 25 ms after. parameter design requirement design result two rail voltage supervision monitor 3.3-v and 1.8-v rails two TPS3840 devices provide voltage monitoring with 1% accuracy with device options available in 0.1 v variations voltage rail sequencing power up the 3.3-v rail first followed by 1.8-v rail 25 ms after the ct capacitor on tps38240pl28 is set to 0.047 f for a reset time delay of 29 ms typical output logic voltage 3.3-v open-drain 3.3-v open-drain maximum device current consumption 1 a each TPS3840 requires 350 na typical TPS3840pl30 mr vdd gnd ct reset TPS3840dl16 vdd gnd reset mr ct microcontroller v core 3.3v reset vdd ldo en 1.8 v 0.047f v i/o nc 1 f 1 f 10 n? copyright ? 2018, texas instruments incorporated advance information
19 TPS3840 www.ti.com snvsb03 ? december 2018 product folder links: TPS3840 submit documentation feedback copyright ? 2018, texas instruments incorporated 9.2.1.2 detailed design procedure the primary constraint for this application is choosing the correct device to monitor the supply voltage of the microprocessor. the TPS3840 can monitor any voltage between 1.6 v and 10 v and is available in 0.1 v increments. depending on how far away from the nominal voltage rail the user wants the voltage supervisor to trigger determines the correct voltage supervisor variant to choose. in this example, the first TPS3840 triggers when the 3.3-v rail falls to 3.0 v. the second TPS3840 triggers a reset when the 1.8-v rail falls to 1.6 v. the secondary constraint for this application is the reset time delay that must be at least 25 ms to allow the microprocessor, and all other devices using the 3.3-v rail, enough time to startup correctly before the 1.8-v rail is enabled via the ldo. because a minimum time is required, the user must account for capacitor tolerance. for applications with ambient temperatures ranging from ? 40 c to +125 c, c ct can be calculated using r ct and solving for c ct in equation 2 . solving equation 2 for 25 ms gives a minimum capacitor value of 0.04 f which is rounded up to a standard value 0.047 f to account for capacitor tolerance. a 1- f decoupling capacitor is connected to the vdd pin as a good analog design practice. the pull-up resistor is only required for the open-drain device variants and is calculated to maintain the reset current within the 5 ma limit found in the recommended operating conditions : r pull-up = v pull-up 5 ma. for this design, a standard 10-k ? pull-up resistor is selected to minimize current draw when reset is asserted. keep in mind the lower the pull-up resistor, the higher v ol . the mr pin can be connected to an external signal if desired or left floating if not used due to the internal pull-up resistor to vdd. 9.2.1.3 application curves figure 40. startup sequence highlighting the delay between 3.3v and 1.8v rails advance information vdd reset (ldo enable) v (ldo) out 30ms delay from vdd (3.3v) to ldo enable set by 0.047f on ct of TPS3840pl30 negligible delay from ldo enable to 1.8v v out
20 TPS3840 snvsb03 ? december 2018 www.ti.com product folder links: TPS3840 submit documentation feedback copyright ? 2018, texas instruments incorporated 9.2.2 design 2: battery voltage and temperature monitor a typical application for the TPS3840 is battery voltage and temperature monitoring. the TPS3840 is offered in active-low or active-high output topologies meaning the device can be used as an undervoltage monitor as shown in figure 39 or overvoltage monitor as shown in figure 42 . the TPS3840 can be used to monitor any rail above 1.6 v. in this design application, a tps3480dl30 monitors the 3.3-v battery voltage rail and triggers a reset fault condition if the battery voltage falls below 3 v and TPS3840ph30 monitors a 2.8-v battery and triggers a reset at 3.1 v due to the 100 mv hysteresis for the rising input trigger. both designs monitor the battery temperature and trigger a fault if the battery temperature falls outside of a defined window temperature range by utilizing the tmp303. the tmp303 device is a temperature switch that monitors the battery temperature and sends a signal to the manual reset pin on the TPS3840 if the battery temperature is out of range. figure 41. low battery voltage and window temperature monitoring solution figure 42. overvoltage and window temperature monitoring solution 9.2.2.1 design requirements this design requires voltage and temperature supervision on a battery voltage rail and the requirements may differ depending on if undervoltage or overvoltage monitoring is required. for this design, both requirements are considered to show the flexibility of the TPS3840 device. for the undervoltage requirement, the fault occurs when the battery voltage drops below 3 v or when the battery temperature is outside the range from 0 c to 60 c. for the overvoltage requirement, the fault occurs when the battery voltage rises above 3.1 v or when the battery temperature is outside the range from 0 c to 60 c. note that if using two TPS3840 devices for both undervoltage and overvoltage monitoring on the same battery, only one single tmp303 temperature monitoring device is required. TPS3840ph30 vdd gnd reset mr ct battery charger 2.8v gnd tmp303 out hyst hyst set0 set1 soh v s enable 10f TPS3840dl30 vdd gnd reset mr ct microcontroller v core 3.3v gnd tmp303 out hyst hyst set0 set1 soh v s fault 10f 1 0? advance information
21 TPS3840 www.ti.com snvsb03 ? december 2018 product folder links: TPS3840 submit documentation feedback copyright ? 2018, texas instruments incorporated parameter design requirement design result battery voltage supervision monitor 3.3-v battery for undervoltage condition TPS3840 provides voltage monitoring with 1% accuracy with device options available in 0.1 v variations. TPS3840dl30 triggers a reset when vdd falls below 3 v. TPS3840ph30 triggers a reset when vdd rises above 3 v plus hysteresis setting the overvoltage threshold to 3.1 v. monitor 2.8-v battery for overvoltage condition battery temperature supervision monitor battery temperature between 0 c and 60 c with 1 c resolution tmp303a monitors temperature within 0 c to 60 c with 1 c resolution output topology undervoltage: active-low, open-drain TPS3840 is offered in active-low open-drain, active-low push-pull, and active-high push-pull topologies overvoltage: active-high, push-pull maximum device current consumption 10 a TPS3840 requires 350 na (typical) and tmp303 requires 3.5 a (typical) delay when returning from fault condition delay of at least 6 seconds when returning from the fault to prevent operation in fault conditions c ct = 10 f sets 6.18 second delay 9.2.2.2 detailed design procedure the primary constraint for this application is choosing the correct device to monitor the battery supply voltage. the TPS3840 can monitor any voltage between 1.6 v and 10 v and is available in 0.1 v increments. depending on how far away from the nominal voltage rail the user wants the voltage supervisor to trigger determines the correct voltage supervisor variant to choose. in this example, the TPS3840dl30 triggers when the 3.3-v rail falls to 3 v and the TPS3840ph30 triggers when the 2.8-v rail rises to 3.1 v. the secondary constraint for this application is the battery temperature monitoring accomplished by the tmp303. typical lithium ion battery discharge temperature range is 0 c to 60 c. the tmp303 triggers a fault to the mr pin of the TPS3840 whenever the temperature is outside of the temperature range. the tmp303 offers 1 c resolution to meet the high resolution requirement. the last constraint is the reset/reset time delay set by c ct . for applications with ambient temperatures ranging from ? 40 c to +125 c, c ct can be calculated using r ct and solving for c ct in equation 2 . by choosing a standard 10% capacitor value of 10 f ensures the reset/reset time delay will be at least 6 seconds. note: active-low devices use the output label reset and active-high devices use the output label reset. a 0.1- f decoupling capacitor is connected to the vdd pin as a good analog design practice. the pull-up resistor is only required for the open-drain device variants and is calculated to maintain the reset current within the 5 ma limit found in the recommended operating conditions : r pull-up = v pull-up 5 ma. for this design, a 1-m ? pull-up resistor is selected to minimize current draw when reset is asserted and to prevent the battery from unnecessary discharge. keep in mind the lowering the pull-up resistor, increases v ol and i out . the mr pin is used for a second fault condition provided by the temperature switch. 9.2.3 design 3: fast start undervoltage supervisor with level-shifted input a typical application for the TPS3840 is a fast startup undervoltage supervisor that operates with an input power supply higher than the recommended maximum of 10 v through the use of a resistor divider at the input as shown in figure 43 . the TPS3840 can be used to monitor any rail above 1.6 v and only requires maximum 500 s upon startup before the device can begin monitoring a voltage. in this design application, a tps3480 monitors a 12-v rail and triggers a reset fault condition if the voltage rail voltage drops below 10 v using a TPS3840 device with v it- of 4.9 v. this design also accounts for a wide input range in the case the 12-v rail rises higher, the resistor divider is set so that the voltage at the vdd pin never exceeds 10 v. TPS3840 is available in both active-low and active-high topologies providing the flexibility to monitor undervoltage or overvoltage with either output logic. this design uses the active-low, open-drain TPS3840dl49 variant so that when the undervoltage condition occurs, that is when the voltage at vdd pin falls below the voltage threshold set by the external resistor divider, the output transitions to logic-low and can be used to flag an undervoltage condition or used to connect to the enable of the next device to shut it off as a logic low on an enable pin typically disables the device. in this design, the output of the TPS3840 simply connects to a mcu to flag an undervoltage condition. advance information
22 TPS3840 snvsb03 ? december 2018 www.ti.com product folder links: TPS3840 submit documentation feedback copyright ? 2018, texas instruments incorporated figure 43. fast start undervoltage supervisor with level-shifted input 9.2.3.1 design requirements this design requires voltage supervision on a 12-v power supply voltage rail with possibility of the 12-v rail rising up as high as 18 v. the undervoltage fault occurs when the power supply voltage drops below 10 v. parameter design requirement design result power rail voltage supervision monitor 12-v power supply for undervoltage condition, trigger a undervoltage fault at 10 v. TPS3840 provides voltage monitoring with 1% accuracy with device options available in 0.1 v variations. the TPS3840 monitors voltages above 1.6 v. maximum input power operate with power supply input up to 18 v. the TPS3840 limits vdd to 10 v but can monitor voltages higher than the maximum vdd voltage with the use of an external resistor divider. output logic voltage 3.3-v open-drain 3.3-v open-drain maximum device current consumption 35 a when power supply is at 18 v maximum TPS3840 requires 350 na (typical) and the external resistor divider will also consume current. there is a tradeoff between current consumption and voltage monitor accuracy but generally set the resistor divider to consume 100 times current into vdd. voltage monitor accuracy typical voltage monitor accuracy of 2.5%. this allows the voltage threshold to range between 11.75 v and 10.25 v. the TPS3840 has 1% typical voltage monitor accuracy. by decreasing the ratio of resistor values, the resistor divider will consume more current but the accuracy will increase. the resistor tolerance also needs to be accounted for. delay when returning from fault condition reset delay of at least 200 ms when returning from a undervoltage fault. c ct = 0.33 f sets 204 ms delay 9.2.3.2 detailed design procedure the primary constraint for this application is monitoring a 12-v rail while preventing the vdd pin on TPS3840 from exceeding the recommended maximum of 10 v. this is accomplished by sizing the resistor divider so that when the 12-v rail drops to 10 v, the vdd pin for TPS3840 will be at 4.9 v which is the v it- threshold for triggering a undervoltage condition for TPS3840dl49 as shown in equation 5 . v rail_trigger = v it- x (r bottom (r top + r bottom )) (5) where v rail_trigger is the trigger voltage of the rail being monitored, v it- is the falling threshold on the vdd pin of TPS3840, and r top and r bottom are the top and bottom resistors of the external resistor divider. v it- is fixed per device variant and is 4.9 v for TPS3840dl49. substituting in the values from figure 43 , the undervoltage trigger threshold for the rail is set to 10.045 v. TPS3840dl49 vdd gnd reset mr ct microcontroller v core reset 3.3v 0.33f nc 10 n? 10.5 n? 125 n? 12v advance information
23 TPS3840 www.ti.com snvsb03 ? december 2018 product folder links: TPS3840 submit documentation feedback copyright ? 2018, texas instruments incorporated since the undervoltage trigger of 10 v on the rail corresponds to 4.9 v undervoltage threshold trigger of the TPS3840 device, there is plenty of room for the rail to rise up while maintaining less than 10 v on the vdd pin of the TPS3840. equation 6 shows the maximum rail voltage that still meets the 10 v maximum at the vdd pin for TPS3840. v rail_max = 10 x (10,000 (10,500 + 10,000)) = 20.5 v (6) this means the monitored voltage rail can go as high as 20.5 v and still not violate the recommended maximum for the vdd pin on TPS3840. this is useful when monitoring a voltage rail that has a wide range that may go much higher than the nominal rail voltage such as in this case with the specification that the 12-v rail can go as high as 18 v. 9.2.4 design 4: voltage monitor with back-up battery switchover a typical application for the TPS3840 is to monitor a voltage rail and switch the power to a back-up battery if the main supply is in undervoltage condition. because systems that utilize a back-up battery tend to require low quiescent current, TPS3840 serves as the perfect solution as this device only requires 350 na typically. the TPS3840 monitors the main power rail via the vdd pin and when the main power rail falls, the reset output asserts causing a switch to close on the back-up battery rail. the diodes provide an oring logic function to prevent reverse leakage and to allow either rail to connect to the output depending on the status of the main voltage rail. figure 44. voltage monitor with back-up battery switchover solution 9.2.4.1 design requirements this design requires voltage supervision on a 5-v main supply voltage rail and when the main rail fails, switch to a back-up battery supply to prevent complete power loss in the system. the system output must remain above 1.8 v even when the main supply completely fails. the design requires less than 500 na of total current consumption and must prevent battery leakage when the battery is not being used. when the system is using the back-up battery and the main supply voltage rail comes back up, the system must switch back to the main power supply in less than 100 s to save battery power. parameter design requirement design result main supply voltage supervision monitor 5-v main supply for undervoltage condition. when main supply drops below 3 v, switch to back-up battery. TPS3840 provides voltage monitoring with 1% accuracy with device options available in 0.1 v variations. this design uses TPS3840pl30 to set the undervoltage trigger at 3 v. batck-up battery switchover when undervoltage occurs on the main supply voltage rail, switch to the back-up batter. when undervoltage occurs on the main supply rail, the pmos switch closes allowing the back-up battery to connect to the system output. the diodes prevent reverse leakage and allow either power supply to connect to the system output. main power supply to back-up battery switch response time no more than 50 s to switch to the back-up battery when the main power supply falls to undervoltage condition. TPS3840 provides a propagation delay for vdd falling below the undervoltage threshold (t p_hl ) of 50 s maximum to meet the requirement. TPS3840pl30 vdd gnd reset mr ct nc 5v + 3.3v vbat system output nc advance information
24 TPS3840 snvsb03 ? december 2018 www.ti.com product folder links: TPS3840 submit documentation feedback copyright ? 2018, texas instruments incorporated parameter design requirement design result back-up battery to main power supply switch back response time less than 100 s when switching from back-up battery back to main power supply when undervoltage condition is removed. by leaving mr disconnected, the reset delay is set to a maximum of 80 s to meet the requirement. device current consumption 500 na TPS3840 requires 350 na (typical) system output voltage system output must remain above 1.8 v in all cases when the main 5-v rail is connected, the system output will be the rail voltage minus a diode voltage drop so at least 3 v - 0.7 v ~ 2.3 v. when the voltage rail drops below 3 v, the back-up battery switches into the system and the system output becomes the battery voltage minus a diode voltage drop so 3.3 v - 0.7 v ~ 2.6 v. the threshold at which the battery switches into the system directly depends on the TPS3840 variant chosen. 9.2.4.2 detailed design procedure the primary constraints for this application are choosing the correct device variant for the monitored voltage and deciding the preferred solution to switch the back-up battery in and out of the system. for this design, the TPS3840pl30 provides an active-low, push-pull output topology that turns on the pfet when the 5-v rail monitored by vdd drops to 3.0 v. the diodes logically or the power supply with the back-up battery and prevents reverse current leakage. using this solution, the system output remains above 1.8 v in all circumstances unless both the 5-v rail and back-up battery fail. the system output voltage will follow the 5-v rail minus a diode drop until the 5-v rail drops to 3 v then the back-up battery switches into the system providing 3.3 v minus a diode drop to the system output. when the 5-v rail comes back above 3.1 v accounting for hysteresis, the pfet turns off to disconnect the back-up battery from the system. since this design disconnects the battery when not being used, this solution maximizes battery life. 9.2.5 application curve: TPS3840evm these application curves are taken with the TPS3840evm . please see the TPS3840evm user guide for more information. figure 45. TPS3840evm reset time delay (t d ) with no capacitor figure 46. TPS3840evm reset time delay (t d ) with 0.01- f capacitor figure 47. TPS3840evm reset time delay (t d ) with 1- f capacitor advance information vdd reset reset delay (t d ) = 5.8 ms vdd reset reset delay (t d ) = 22 s vdd reset reset delay (t d )= 654 ms
25 TPS3840 www.ti.com snvsb03 ? december 2018 product folder links: TPS3840 submit documentation feedback copyright ? 2018, texas instruments incorporated 10 power supply recommendations these devices are designed to operate from an input supply with a voltage range between 1.5 v and 10 v. ti recommends an input supply capacitor between the vdd pin and gnd pin. this device has a 12-v absolute maximum rating on the vdd pin. if the voltage supply providing power to vdd is susceptible to any large voltage transient that can exceed 12 v, additional precautions must be taken. 11 layout 11.1 layout guidelines make sure that the connection to the vdd pin is low impedance. good analog design practice recommends placing a minimum 0.1- f ceramic capacitor as near as possible to the vdd pin. if a capacitor is not connected to the ct pin, then minimize parasitic capacitance on this pin so the rest time delay is not adversely affected. ? make sure that the connection to the vdd pin is low impedance. good analog design practice is to place a > 0.1- f ceramic capacitor as near as possible to the vdd pin. ? if a c ct capacitor is used, place these components as close as possible to the ct pin. if the ct pin is left unconnected, make sure to minimize the amount of parasitic capacitance on the pin to < 5 pf. ? place the pull-up resistors on reset pin as close to the pin as possible. 11.2 layout example the layout example in shows how the TPS3840 is laid out on a printed circuit board (pcb) with a user-defined delay. figure 48. TPS3840 recommended layout gnd c in gnd vdd vias used to connect pins for application-specific connections c ct r pull-up reset ct mr vdd pull-up resistor required for open-drain (TPS3840dlxx) only advance information
26 TPS3840 snvsb03 ? december 2018 www.ti.com product folder links: TPS3840 submit documentation feedback copyright ? 2018, texas instruments incorporated 12 device and documentation support 12.1 device nomenclature table 2 shows how to decode the function of the device based on its part number table 2. device naming convention description nomenclature value engineering prototype pre-release sample p engineering prototype sample part number TPS3840 TPS3840 variant code (output topology) dl open-drain, active-low ph push-pull, active-high pl push-pull, active-low detect voltage option ## (two characters) example: 12 stands for 1.2 v threshold package dbv sot23-5 reel r large reel table 3 shows the possible variants of the TPS3840. contact texas instruments for details and availability of other options shown; minimum order quantities apply. table 3. device threshold product voltage threshold (v it- ) hysteresis (v hyst ) open-drain, active-low push-pull, active-low push-pull, active-high typ (v) typ (v) TPS3840dl16 TPS3840pl16 TPS3840ph16 1.6 0.100 TPS3840dl17 TPS3840pl17 TPS3840ph17 1.7 0.100 TPS3840dl18 TPS3840pl18 TPS3840ph18 1.8 0.100 TPS3840dl19 TPS3840pl19 TPS3840ph19 1.9 0.100 TPS3840dl20 TPS3840pl20 TPS3840ph20 2.0 0.100 TPS3840dl21 TPS3840pl21 TPS3840ph21 2.1 0.100 TPS3840dl22 TPS3840pl22 TPS3840ph22 2.2 0.100 TPS3840dl23 TPS3840pl23 TPS3840ph23 2.3 0.100 TPS3840dl24 TPS3840pl24 TPS3840ph24 2.4 0.100 TPS3840dl25 TPS3840pl25 TPS3840ph25 2.5 0.100 TPS3840dl26 TPS3840pl26 TPS3840ph26 2.6 0.100 TPS3840dl27 TPS3840pl27 TPS3840ph27 2.7 0.100 TPS3840dl28 TPS3840pl28 TPS3840ph28 2.8 0.100 TPS3840dl29 TPS3840pl29 TPS3840ph29 2.9 0.100 TPS3840dl30 TPS3840pl30 TPS3840ph30 3.0 0.100 TPS3840dl31 TPS3840pl31 TPS3840ph31 3.1 0.100 TPS3840dl32 TPS3840pl32 TPS3840ph32 3.2 0.200 TPS3840dl33 TPS3840pl33 TPS3840ph33 3.3 0.200 TPS3840dl34 TPS3840pl34 TPS3840ph34 3.4 0.200 TPS3840dl35 TPS3840pl35 TPS3840ph35 3.5 0.200 TPS3840dl36 TPS3840pl36 TPS3840ph36 3.6 0.200 TPS3840dl37 TPS3840pl37 TPS3840ph37 3.7 0.200 TPS3840dl38 TPS3840pl38 TPS3840ph38 3.8 0.200 TPS3840dl39 TPS3840pl39 TPS3840ph39 3.9 0.200 TPS3840dl40 TPS3840pl40 TPS3840ph40 4.0 0.200 TPS3840dl41 TPS3840pl41 TPS3840ph41 4.1 0.200 TPS3840dl42 TPS3840pl42 TPS3840ph42 4.2 0.200 advance information
27 TPS3840 www.ti.com snvsb03 ? december 2018 product folder links: TPS3840 submit documentation feedback copyright ? 2018, texas instruments incorporated table 3. device threshold (continued) product voltage threshold (v it- ) hysteresis (v hyst ) open-drain, active-low push-pull, active-low push-pull, active-high typ (v) typ (v) TPS3840dl43 TPS3840pl43 TPS3840ph43 4.3 0.200 TPS3840dl44 TPS3840pl44 TPS3840ph44 4.4 0.200 TPS3840dl45 TPS3840pl45 TPS3840ph45 4.5 0.200 TPS3840dl46 TPS3840pl46 TPS3840ph46 4.6 0.200 TPS3840dl47 TPS3840pl47 TPS3840ph47 4.7 0.200 TPS3840dl48 TPS3840pl48 TPS3840ph48 4.8 0.200 TPS3840dl49 TPS3840pl49 TPS3840ph49 4.9 0.200 12.2 community resources the following links connect to ti community resources. linked contents are provided "as is" by the respective contributors. they do not constitute ti specifications and do not necessarily reflect ti's views; see ti's terms of use . ti e2e ? online community ti's engineer-to-engineer (e2e) community. created to foster collaboration among engineers. at e2e.ti.com, you can ask questions, share knowledge, explore ideas and help solve problems with fellow engineers. design support ti's design support quickly find helpful e2e forums along with design support tools and contact information for technical support. 12.3 trademarks e2e is a trademark of texas instruments. all other trademarks are the property of their respective owners. 12.4 electrostatic discharge caution this integrated circuit can be damaged by esd. texas instruments recommends that all integrated circuits be handled with appropriate precautions. failure to observe proper handling and installation procedures can cause damage. esd damage can range from subtle performance degradation to complete device failure. precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. 12.5 glossary slyz022 ? ti glossary . this glossary lists and explains terms, acronyms, and definitions. 13 mechanical, packaging, and orderable information the following pages include mechanical, packaging, and orderable information. this information is the most current data available for the designated devices. this data is subject to change without notice and revision of this document. for browser-based versions of this data sheet, refer to the left-hand navigation. advance information
package option addendum www.ti.com 6-dec-2018 addendum-page 1 packaging information orderable device status (1) package type package drawing pins package qty eco plan (2) lead/ball finish (6) msl peak temp (3) op temp (c) device marking (4/5) samples pTPS3840dl20dbvr active sot-23 dbv 5 3000 tbd call ti call ti -40 to 125 pTPS3840dl27dbvr active sot-23 dbv 5 3000 tbd call ti call ti -40 to 125 pTPS3840dl29dbvr active sot-23 dbv 5 3000 tbd call ti call ti -40 to 125 pTPS3840ph30dbvr active sot-23 dbv 5 3000 tbd call ti call ti -40 to 125 pTPS3840pl25dbvr active sot-23 dbv 5 3000 tbd call ti call ti -40 to 125 pTPS3840pl28dbvr active sot-23 dbv 5 3000 tbd call ti call ti -40 to 125 (1) the marketing status values are defined as follows: active: product device recommended for new designs. lifebuy: ti has announced that the device will be discontinued, and a lifetime-buy period is in effect. nrnd: not recommended for new designs. device is in production to support existing customers, but ti does not recommend using this part in a new design. preview: device has been announced but is not in production. samples may or may not be available. obsolete: ti has discontinued the production of the device. (2) rohs: ti defines "rohs" to mean semiconductor products that are compliant with the current eu rohs requirements for all 10 rohs substances, including the requirement that rohs substance do not exceed 0.1% by weight in homogeneous materials. where designed to be soldered at high temperatures, "rohs" products are suitable for use in specified lead-free processes. ti may reference these types of products as "pb-free". rohs exempt: ti defines "rohs exempt" to mean products that contain lead but are compliant with eu rohs pursuant to a specific eu rohs exemption. green: ti defines "green" to mean the content of chlorine (cl) and bromine (br) based flame retardants meet js709b low halogen requirements of <=1000ppm threshold. antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. (3) msl, peak temp. - the moisture sensitivity level rating according to the jedec industry standard classifications, and peak solder temperature. (4) there may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) multiple device markings will be inside parentheses. only one device marking contained in parentheses and separated by a "~" will appear on a device. if a line is indented then it is a continuation of the previous line and the two combined represent the entire device marking for that device. (6) lead/ball finish - orderable devices may have multiple material finish options. finish options are separated by a vertical ruled line. lead/ball finish values may wrap to two lines if the finish value exceeds the maximum column width.
package option addendum www.ti.com 6-dec-2018 addendum-page 2 important information and disclaimer: the information provided on this page represents ti's knowledge and belief as of the date that it is provided. ti bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. efforts are underway to better integrate information from third parties. ti has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. ti and ti suppliers consider certain information to be proprietary, and thus cas numbers and other limited information may not be available for release. in no event shall ti's liability arising out of such information exceed the total purchase price of the ti part(s) at issue in this document sold by ti to customer on an annual basis.

important notice and disclaimer ti provides technical and reliability data (including datasheets), design resources (including reference designs), application or other design advice, web tools, safety information, and other resources ? as is ? and with all faults, and disclaims all warranties, express and implied, including without limitation any implied warranties of merchantability, fitness for a particular purpose or non-infringement of third party intellectual property rights. these resources are intended for skilled developers designing with ti products. you are solely responsible for (1) selecting the appropriate ti products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable standards, and any other safety, security, or other requirements. these resources are subject to change without notice. ti grants you permission to use these resources only for development of an application that uses the ti products described in the resource. other reproduction and display of these resources is prohibited. no license is granted to any other ti intellectual property right or to any third party intellectual property right. ti disclaims responsibility for, and you will fully indemnify ti and its representatives against, any claims, damages, costs, losses, and liabilities arising out of your use of these resources. ti ? s products are provided subject to ti ? s terms of sale ( www.ti.com/legal/termsofsale.html ) or other applicable terms available either on ti.com or provided in conjunction with such ti products. ti ? s provision of these resources does not expand or otherwise alter ti ? s applicable warranties or warranty disclaimers for ti products. mailing address: texas instruments, post office box 655303, dallas, texas 75265 copyright ? 2018, texas instruments incorporated

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