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1 ? fn6722.0 caution: these devices are sensitive to electrosta tic discharge; follow proper ic handling procedures. 1-888-intersil or 1-888-468-3774 | intersil (and design) is a registered trademark of intersil americas inc. copyright ? intersil americas inc. 2008. all rights reserved all other trademarks mentioned are the property of their respective owners. ISL9506 multiphase pwm controller with programmable output voltage the ISL9506 is a multiphase pwm buck controller for high performance digital processor core. this multiphase buck controller uses interleaved c hannels to reduce the total output voltage ripple with each channel carrying a portion of total load current. the multiple phase implementation results in better system performance, superior thermal management, lower component cost, reduced power dissipation, and smaller implementation area. the ISL9506 multiphase controller together with isl6208 external ga te drivers provide a complete solution to power the processor core. the pwm modulator of ISL9506 is based on intersil's robust ripple regulator technology (r 3 ). compared with the traditional multiphase buck regulator, the r 3 modulator commands variable switching frequency during load transients, which achieves faster transient response. with the sa me modulator, the switching frequency is reduced at light load conditions resulting higher operation efficiency. ISL9506 responds to lp (low power) signal by adding or dropping pwm2 and adjusting overcurrent protection accordingly. ISL9506 enables diode emulation and stretches switching period at light load conditions to improve efficiency. the diode emulation feature is programmed by de_en (diode emulation enable) and de_enn pins. the ISL9506 has several other key features. ISL9506 reports output power through a power monitor pin (pmon). current sense can be achieved by using ei ther inductor dcr or discrete precision resistor. in the case of dcr current sensing, a single ntc thermistor is used to thermally compensate the inductor dcr variation with temperature. a unity gain, differential amplifier is available for remote voltage sensing. this allows the voltage at the load point to be accurately m easured and regulated per voltage selection pins. features ? precision multiphase voltage regulation - 0.5% system accuracy over temperature - enhanced droop impedance accuracy ? voltage selection input - 7-bit vsel (voltage selection) input - 0.300v to 1.500v in 12.5mv steps - supports vsel c hanges on-the-fly ? multiple current sensin g approaches supported - lossless dcr current sensing - precision resistive current sensing ? optimized efficiency across overall load range ? superior noise immunity and transient response ? power monitor and thermal monitor ? differential remote voltage sensing ? programmable 1, 2 or 3 power channels ? excellent dynamic current balance between channels ? small footprint 40 ld 6x6 qfn package ? pb-free (rohs compliant) applications ? mobile laptop computers ? high performance point-of-load power supply pinout ISL9506 (40 ld qfn) top view ordering information part number (note) part marking temp. range (c) package (pb-free) pkg. dwg. # ISL9506hrz ISL9506 hrz -10 to +100 40 ld 6x6 qfn l40.6x6 ISL9506hrz-t ISL9506 hrz -10 to +100 40 ld 6x6 qfn tape and reel l40.6x6 *please refer to tb347 for detai ls on reel specifications. note: these intersil pb-free pl astic packaged products employ special pb-free material sets, molding compounds/die attach materials, and 100% matte tin plate plus anneal (e3 termination finish, which is rohs compliant and compatible with both snpb and pb-free soldering operations). intersil pb-f ree products are msl classified at pb-free peak reflow temperatures that meet or exceed the pb-free requirements of ipc/jedec j std-020. 1 40 2 3 4 5 6 7 8 9 10 30 29 28 27 26 25 24 23 22 21 39 38 37 36 35 34 33 32 31 11 12 13 14 15 16 17 18 19 20 gnd pad (bottom) p g d _ n d e _ e n v r _ e n v s e l 6 v s e l 5 v s e l 4 v s e l 3 vsel2 p g o o d v i n vrhot# ntc vsel1 vsel0 pwm1 pwm3 fccm isen1 isen2 v s u m v o ocset r tn v s e n v d i f f fb comp vw v d d v s s soft pmon rbias lp d e _ e n n d f b d r o o p 3 v 3 pwm2 isen3 data sheet august 13, 2008
2 fn6722.0 august 13, 2008 functional pin description lp (pin 1) low power indicator input. when asserted low, indicates a reduced load-current condition. for ISL9506, when lp is asserted low, pwm2 will be disabled. pmon (pin 2) an analog output. pmon sends out an analog signal proportional to the product of vsen voltage and the droop voltage. rbias (pin 3) connect a 147k resistor to vss, sets the internal current reference. vrhot# (pin 4) thermal overload output indicator. ntc (pin 5) thermistor input to vrhot# circuit. soft (pin 6) a capacitor from this pin to vss sets the maximum slew rate of the output voltage. it affects both soft start and vsel transitioning slew rate. soft pin is the non-inverting input of the error amplifier. ocset (pin 7) overcurrent set input. a resistor from this pin to vo sets droop voltage limit for oc trip. a 10a current source is connected internally to this pin. vw (pin 8) a resistor from this pin to comp programs the switching frequency. (7k gives approximately 300khz). vw pin sources current. comp (pin 9) this pin is the output of the error amplifier. fb (pin 10) this pin is the inverting input of error amplifier. vdiff (pin 11) this pin is the output of the differential amplifier. vsen (pin 12) remote output voltage sense input. connect to the point of load. rtn (pin 13) remote voltage sensing return. connect to ground at the point of load. droop (pin 14) output of droop amplifier. output = vo + droop. dfb (pin 15) inverting input to droop amplifier. vo (pin 16) an input to the ic that reports the local output voltage. vsum (pin 17) this pin is connected to the current summation junction. vin (pin 18) battery supply voltage, used for feed forward. vss (pin 19) signal ground; connect to local controller ground. vdd (pin 20) 5v bias power. isen3 (pin 21) individual current sensing for channel 3. isen2 (pin 22) individual current sensing for channel 2. isen1 (pin 23) individual current sensing for channel 1. fccm (pin 24) forced continuous conduction mode (fccm) enable pin to mosfet drivers. it will disable diode emulation. pwm3 (pin 25) pwm output for channel 3. when pwm3 is pulled to 5v vdd, pwm3 will be disabled and allow other channels to operate. 1 40 2 3 4 5 6 7 8 9 10 30 29 28 27 26 25 24 23 22 21 39 38 37 36 35 34 33 32 31 11 12 13 14 15 16 17 18 19 20 gnd pad (bottom) p g d _ n d e _ e n v r _ e n v s e l 6 v s e l 5 v s e l 4 v s e l 3 vsel2 p g o o d v i n vrhot# ntc vsel1 vsel0 pwm1 pwm3 fccm isen1 isen2 v s u m v o ocset r t n v s e n v d i f f fb comp vw v d d v s s soft pmon rbias lp d e _ e n n d f b d r o o p 3 v 3 pwm2 isen3 ISL9506
3 fn6722.0 august 13, 2008 pwm2 (pin 26) pwm output for channel 2. for ISL9506, lp low will make this output tri-state. when pw m2 is pulled to 5v vdd, pwm2 will be disabled and allow other channels to operate. pwm1 (pin 27) pwm output for channel 1. vsel0:6 (pin28:pin34) voltage selection input with vsel0 = lsb and vsel6 = msb. vr_en (pin 35) voltage regulator enable input. a high level logic signal on this pin enables the regulator. de_en (pin 36) diode emulation enable signal. a high level logic signal on this pin will allow diode emulation operation. only if the current is low enough, the diode emulation will actually be entered. de_en logic high also affects the output voltage transition from one voltage selection to anther programmed by voltage select. de_enn (pin 37) de_en and de_enn work together for diode emulation. generally a reversed logic signal of de_en should be applied to de_enn. pgd_n (pin 38) digital output prior to pgood high. goes nominal (logic 0) after 13 switching cycles after v out is within 10% of 1.2v voltage at start-up. 3v3 (pin 39) 3.3v supply voltage for pgd_n logic, such an implementation will increase power consumption from 3.3v compared to open drain circuit other wise. pgood (pin 40) power good open-drain output. will be pulled up externally by a 1.9k resistor to 3.3v. ISL9506
4 fn6722.0 august 13, 2008 absolute maximum rati ngs thermal information supply voltage, v dd . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 to +7v battery voltage, v in . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +25v open drain outputs, pgood, vrhot# . . . . . . . . . . . . -0.3 to +7v all other pins . . . . . . . . . . . . . . . . . . . . . . . . . -0.3v to (vdd + 0.3v) operating conditions temperature range . . . . . . . . . . . . . . . . . . . . . . . . .-10c to +100c supply voltage range (typical). . . . . . . . . . . . . . . . . . . . . +5v 5% thermal resistance (notes 1, 2) ja (c/w) jc (c/w) 40 ld qfn package. . . . . . . . . . . . . . . 30 5.5 maximum junction temperature . . . . . . . . . . . . . . . . . . . . . . +150c storage temperature . . . . . . . . . . . . . . . . . . . . . . . .-65c to +150c pb-free reflow profile. . . . . . . . . . . . . . . . . . . . . . . . .see link below http://www.intersil.com/pbfree/pb-freereflow.asp caution: do not operate at or near the maximum ratings listed fo r extended periods of time. exposure to such conditions may adv ersely impact product reliability and result in failures not covered by warranty. notes: 1. ja is measured with the component mounted on a low effective therma l conductivity test board in free air. see tech brief tb379 fo r details. 2. for jc , the ?case temp? location is the center of the exposed metal pad on the package underside. 3. limits established by characteri zation and are not production tested. electrical specifications operating conditions: vdd = 5v, t a = -10c to +100c, unless otherwise noted. parameters with min and/or max limits are 100% tested at +25c, unless otherwi se specified. temperatur e limits established by characterization and are not production tested. parameter symbol test conditions min typ max units input power supply +5v supply current i vdd vr_en = 3.3v 3.6 4.2 ma vr_en = 0v 1 a +3.3v supply current i 3v3 no load on pgd_n 1 a battery supply current i vin vr_en = 0v 1 a v in input resistance r vin vr_en = 3.3v 900 k power-on-reset threshold por r v dd rising 4.35 4.5 v por f v dd falling 4.00 4.15 v system and references system accuracy %error (v out ) no load; closed loop, nominal mode range vsel = 0.75v to 1.50v -0.5 +0.5 % vsel = 0.5v to 0.7375v -8 +8 mv vsel = 0.3 to 0.4875v -15 +15 mv v start 1.176 1.200 1.224 v maximum output voltage v out(max) vsel = [0000000] 1.500 v minimum output voltage v out(min) vsel = [1100000] 0.300 v vsel off state vsel = [1111111] 0.0 v r bias voltage r bias = 147k 1.45 1.47 1.49 v channel frequency nominal channel frequency f sw(nom) r fset = 7k , 3 channel operation, v comp =2v 285 300 315 khz adjustment range see equation 6 r fset selection 200 500 khz amplifiers droop amplifier offset -0.3 +0.3 mv error amp dc gain a v0 (note 3) 90 db error amp gain-bandwidth product gbw c l = 20pf (note 3) 18 mhz fb input current i in(fb) 10 150 na ISL9506
5 fn6722.0 august 13, 2008 isen imbalance voltage maximum of isens - minimum of isens 2 mv input bias current 20 na soft current soft-start current i ss -47 -42 -37 a soft geyserville current i gv |soft-v dac | >100mv 180 205 230 a soft diode emulation entry current i c4 de_en = 3.3v -47 -42 -37 a soft diode emulation exit current i c4ea de_en = 3.3v 37 42 47 a soft diode emulation exit current i c4eb de_en = 0v 180 205 230 a power good and protection monitors pgood low voltage v ol i pgood = 4ma 0.26 0.4 v pgood leakage current i oh pgood = 3.3v -1 1 a pgood delay tpgd pgd_n low to pgood high 6.3 7.6 8.9 ms overvoltage threshold ov h vo rising above setpoint for >1ms 160 200 240 mv severe overvoltage threshold ov hs vo rising for >2s 1.675 1.7 1.725 v ocset reference current i(r bias ) = 10a 9.8 10 10.2 a oc threshold offset droop rising above ocset for >150s -2 4 mv current imbalance threshold one isen above another isen for >1.2ms 9 mv undervoltage threshold (vdiff/soft) uv f vo falling below setpoint for >1.2ms -355 -295 -235 mv logic thresholds vr_en and de_en input low v il(3.3v) 1.0 v vr_en and de_en input high v ih(3.3v) 2.3 v vsel0: vsel6, lp, de_enn input low v il(1.0v) 0.3 v vsel0: vsel6, lp, de_enn input high v ih(1.0v) 0.7 v pwm pwm (pwm1 to pwm3) output low v ol(5.0v) sinking 5ma 1.0 v fccm output low v ol_fccm sinking 3ma 1.0 v pwm (pwm1 to pwm3) and fccm output high v oh(5.0v) sourcing 5ma 3.5 v pwm tri-state leakage pwm = 2.5v -1 1 a thermal monitor ntc source current ntc = 1.3v 53 60 67 a over-temperature threshold v (ntc) falling 1.18 1.2 1.22 v vrhot# low output resistance r tt i = 20ma 6.5 9 electrical specifications operating conditions: vdd = 5v, t a = -10c to +100c, unless otherwise noted. parameters with min and/or max limits are 100% tested at +25c, unless otherwi se specified. temperatur e limits established by characterization and are not production tested. (continued) parameter symbol test conditions min typ max units ISL9506
6 fn6722.0 august 13, 2008 pgd_n output levels pgd_n high output voltage v oh 3v3 = 3.3v, i = -4ma 2.9 3.1 v pgd_n low output voltage v ol i = 4ma 0.26 0.4 v power monitor pmon output voltage v pmon vsen = 1.2v, droop - vo = 80mv 1.638 1.68 1.722 v vsen = 1.0v, droop - vo = 20mv 0.308 0.35 0.392 v pmon maximum voltage v pmonmax 2.8 3 v pmon sourcing current vsen = 1.0v, droop - vo = 50mv 2.0 ma pmon sinking current vsen = 1.0v, droop-vo = 50mv 2.0 ma maximum current sinking capability see figure 36 v pmon / 250 v pmon / 180 v pmon / 130 a pmon impedance when pmon is within its sourcing/sinking current range (note 3) 7 electrical specifications operating conditions: vdd = 5v, t a = -10c to +100c, unless otherwise noted. parameters with min and/or max limits are 100% tested at +25c, unless otherwi se specified. temperatur e limits established by characterization and are not production tested. (continued) parameter symbol test conditions min typ max units typical operating performance 3-phase, dcr sense, hs o ne irf7821, ls two irf7832 per phase, 300khz, 0.5h figure 1. nominal mode efficiency, 3 phase, ccm, lp = high, v sel = 1.4375v figure 2. droop impedance, 3 phase, ccm, lp = high v sel = 1.435v figure 3. diode emulation mode efficiency, 3 phase, dcm operation, lp = low, v sel = 1.4375v figure 4. diode emulation mode droop impedance, 3 phase, ccm, lp = low v sel = 1.435v 50 60 70 80 10 90 100 efficiency (%) 1100 v in = 8.0v v in = 12.6v v in = 19.0v i out (a) 1.32 1.34 1.36 1.38 1.40 1.42 1.44 1.46 0 10 20 30 40 50 v out (v) i out (a) v in = 8.0v v in = 12.6v v in = 19.0v 50 60 70 80 10 90 100 efficiency (%) 1100 i out (a) v in = 8.0v v in = 12.6v v in = 19.0v 1.36 1.37 1.38 1.39 1.40 1.41 1.42 1.43 1.44 0102030 i out (a) v out (v) v in = 8.0v v in = 12.6v v in = 19.0v ISL9506
7 fn6722.0 august 13, 2008 figure 5. diode emulation mode efficiency, 3 phase, dcm operation, lp = low, vsel = 0.75v figure 6. diode emulation mode droop impedance, 3 phase, dcm operation, lp = low, vsel = 0.75v figure 7. nominal mode efficiency, 2 phase, ccm, lp = high, v sel = 1.4375v figure 8. diode emulation mode efficiency, 2 phase, dcm operation, lp = low, v sel = 1.4375v figure 9. diode emulation mode efficiency, 2 phase, dcm operation, lp = low, v sel = 0.75v figure 10. nominal mode droop impedance, 2 phase, ccm, lp = high, v sel = 1.435v typical operating performance 3-phase, dcr sense, hs o ne irf7821, ls two irf7832 per phase, 300khz, 0.5h 50 60 70 80 90 100 0.1 1.0 10.0 i out (a) efficiency (%) v in = 8.0v v in = 12.6v v in = 19.0v 0.68 0.69 0.70 0.71 0.72 0.73 0.74 0.75 0.76 0 102030 i out (a) v out (v) v in = 8.0v v in = 12.6v v in = 19.0v i out (a) 50 60 70 80 90 100 110100 efficiency (%) v in = 8.0v v in = 12.6v v in = 19.0v 50 60 70 80 90 100 efficiency (%) 0.1 1.0 10.0 i out (a) v in = 8.0v v in = 12.6v v in = 19.0v 50 60 70 80 90 100 efficiency (%) 0.1 1.0 10.0 i out (a) v in = 8.0v v in = 12.6v v in = 19.0v 1.32 1.34 1.36 1.38 1.40 1.42 1.44 0 1020304050 i out (a) v out (v) v in = 8.0v v in = 12.6v v in = 19.0v ISL9506
8 fn6722.0 august 13, 2008 figure 11. diode emulation mo de droop impedance, 2 phase, dcm operation, lp = low, v sel = 1.4375v figure 12. diode emulation mode droop impedance, 2 phase, dcm operation, lp = low, v sel = 0.75v typical operating performance 3-phase, dcr sense, hs o ne irf7821, ls two irf7832 per phase, 300khz, 0.5h 1.36 1.37 1.38 1.39 1.40 1.41 1.42 1.43 1.44 0102030 i out (a) v out (v) v in = 8.0v v in = 12.6v v in = 19.0v 0.68 0.69 0.70 0.71 0.72 0.73 0.74 0.75 0.76 0 102030 i out (a) v out (v) v in = 8.0v v in = 12.6v v in = 19.0v typical operating performance figure 13. soft-start waveform 0v to 1.2v (start voltage) and pgd_n timing figure 14. soft-start waveform showing pgood figure 15. 12v-18v input line transient response figure 16. soft-start inrush current, v in = 8v v out pgd_n vr_en vr_en v soft (green) v out (brown) pgood v in v out v out ISL9506
9 fn6722.0 august 13, 2008 figure 17. 3 phase current balance, full load = 50a figure 18. 2 phase current balance, full load = 50a figure 19. transient load response, 40a load step @ 200a/s, 3 phase figure 20. transient load 3 phase operation - current balance figure 21. transient load 3 phase operation, zoom of rising edge current balance figure 22. transient load 3 phase operation, zoom of falling edge current balance typical operating performance (continued) comp pin v out ISL9506
10 fn6722.0 august 13, 2008 figure 23. vsel msb bit change from 1.4375v to 0.65v showing 9mv/s slew rate, de_en = 0, de_enn = 1 figure 24. slew rate entering c4, vsel msb bit change from 1.4375v to 0.65v showing 2mv/s slew rate, de_en = 1, de_enn = 0 figure 25. c4 entry and exit slew rates with de_en and de_enn figure 26. 1.7v ovp showing output pulled low to 0.85v and pwm tri_state figure 27. undervoltage response showing pwm tri-state, vout < vsel - 300mv figure 28. ocp - response typical operating performance (continued) vsel msb v out v out vsel msb v out de_enn and lp de_en and msb v out @ 0.85v pwm v out @ 1.7v v out pwm pgood v out i phase pwm pgood ISL9506
11 fn6722.0 august 13, 2008 figure 29. wocp - short circuit protection figure 30. ISL9506, phase adding and dropping in nominal mode, load current = 15a figure 31. ISL9506 phase adding and dropping in diode emulation mode, load current = 4.35a figure 32. ISL9506, inductor current waveform with phase adding and dropping in dcm or diode emulation mode typical operating performance (continued) pwm i phase v out pgood lp v out pgd_n phase 2 lp pgd_n v out phase 2 phase 1 current phase 2 phase 2 current phase 1 current phase 3 current ISL9506
12 fn6722.0 august 13, 2008 figure 33. ISL9506, inductor current waveform with phase adding and dropping in ccm or nominal mode figure 34. ISL9506, overcurrent due to phase dropping figure 35. power monitor current sourcing capability figure 36. power monitor current sinking capability figure 37. power monitor accuracy figure 38. power monitor vs output current typical operating performance (continued) phase 3 phase 1 current current phase 2 current phase 2 current phase 2 current phase 1 current pgood 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 0.01.02.03.04.05.06.07.0 current sourcing (ma) pmon (v) 19v, 1.15v, 40a 19v, 1.15v, 30a 19v, 1.15v, 20a 19v, 1.15v, 10a 19v, 1.15v, 5a 7 0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 current sinking (ma) pmon (v) vsel = 1.15v, i out = 15a vsel = 1.15v, i out = 10a vsel = 1.15v, i out = 5a vsel = 1.15v, i out = 2.5a 180 50.0 40.0 30.0 20.0 10.0 0.0 25% 20% 15% 10% 5% 0% v in = 19v vsel = 1.15v output current (a) 60.0 50.0 40.0 30.0 20.0 10.0 0.0 power (w) current (a) 0.0 10.0 20.0 30.0 40.0 50.0 pmon measured output power ISL9506
13 fn6722.0 august 13, 2008 simplified applicat ion circuit for dcr current sensing figure 39 shows a simplified application circuit for the isl 9506 converter with inductor dcr current sensing. the isl6208 mosfet gate driver has a force-continuous-c onduction-mode (fccm) input, that when dis abled, allows the regulator to operate in diode emulation for improved light load efficiency. as shown in the circuit diagram, the fccm pin is connected to ISL9506, whic h programs the ccm or dcm mode. figure 39. typical application circuit for dcr sensing r i r 1 r 3 v o v +5 isl6208 v in l o v +5 vcc ugate lgate phase boot pwm fccm gnd c 3 c 1 c 2 v +5 7 vsel<0:6> de_en vr_en c o soft vdiff ocset fb lp rbias fccm pwm3 pwm2 vw vo comp vsels de_en pmon vin vr_en gnd pgood pwm1 vdd rtn v in r n c cs vrhot# vsum r fset lp r l c l isen1 isen2 isen3 vsen pgd_n pgd_n isl6208 vcc ugate lgate phase boot pwm fccm gnd vrhot# ntc ISL9506 power good vsum isen3 v in v +5 isl6208 vcc ugate lgate phase boot pwm fccm gnd v in droop dfb vo' l o r l c l vsum isen2 vo' l o r l c l vsum isen1 vo' vo' vsum 3v3 v +3.3 de_enn de_enn pwr monitor remote sense at pol ISL9506
14 fn6722.0 august 13, 2008 simplified applicati on circuit for resist ive current sensing figure 40 shows a simplified application circuit for the ISL9506 co nverter with external resistor current sensing. a capacitor is added in parallel with rl in order to improve the stability margin of the channel current balance loop. no ntc thermistor is ne eded and the droop circuit is simplified. figure 40. typical application circuit for discrete resistor current sensing r i r 1 r 3 v o v +5 isl6208 v in v +5 vcc ugate lgate phase boot pwm fccm gnd c 3 c 1 c 2 v +5 7 vsel<0:6> vr_en c o soft vdiff ocset fb lp rbias fccm pwm3 pwm2 vw vo comp vsels de_en pmon vin vr_en gnd pgood pwm1 vdd rtn v in vrhot# vsum r fset remote sense at pol isen1 isen2 isen3 vsen pgd_n pgd_n isl6208 vcc ugate lgate phase boot pwm fccm gnd vrhot# ntc ISL9506 power good v in v +5 isl6208 vcc ugate lgate phase boot pwm fccm gnd v in droop dfb vo' vsum l o r l c l vsum isen2 vo' r sen l o r l vsum isen1 vo' r sen l o r l c l vsum isen3 vo' r sen de_enn v +3.3 3v3 c l pwr monitor ISL9506
15 fn6722.0 august 13, 2008 functional block diagram figure 41. simplified block diagram 1 + - dac gnd comp vsel0 vsel1 vsel2 vsel3 vsel4 pwm1 soft pwm2 mode control soft vr_en vin vsel5 fb e/a + - pgood power good monitor rtn pwm3 modulator modulator modulator vin vo vin channel select lp de_en current balance vw clock isen1 isen3 vo vin oc flt flt flt rbias flt vdd isen2 vsum dfb vo droop + - vo protection vdiff vsen vdiff oc ibal ibal pmon dacout pgd_n fccm + - ocset + - ntc vrhot # 54a 1 + - + + oc vin vo oc vin vo oc 1.24v droop vsel6 10a vo mode control de_enn 3v3 pgd_n logic 6a 1.20v gain select) 2x + - fast_oc or way-oc number of phases mode control number of phases vo vsen multiplier vovsen ISL9506
16 fn6722.0 august 13, 2008 theory of operation operational description the ISL9506 is a multiphase regulator for digital processor core power application. it can be programmed for 1-, 2- or 3- channel operation. with is l6208 gate driver capable of diode emulation, the ISL9506 provides optimum efficiency in both heavy and light load conditions. ISL9506 uses intersil patented r 3 (robust ripple regulator?) modulator. the r 3 ? modulator combines the best features of fixed frequency pwm and hysteretic pwm while eliminating many of their shortcomings. the ISL9506 modulator internally synthesizes analog signals inside the ic emulating the inductor ripple currents and use hysteretic comparators on those signals to determine switching pulse widths. operating on these large-amplitude, noise-free synthesized signals allows the ISL9506 to achieve lower output ripple and lower phase jitter than conventional hysteretic and fixed pwm mode controllers. unlike conventional hysteretic converters, the ISL9506 has an error amplifier that allows the contro ller to maintain a 0.5% output voltage accuracy. at heavy load conditions, the ISL9506 is switching at a relatively consta nt switching frequency similar to fixed frequency pwm controller. at light load conditions, the ISL9506 is switching at a frequency proportional to load current similar to hysteretic mode controller. the hysteresis window voltage rides on the error amplifier output such that a load current transient results in an increase in switching frequency to give the r 3 regulator a faster response than conventional fixed frequency pwm controllers. the sharing of the hysteretic window voltage also inherently shares the tran sient load current between the phases. the individual average phase voltages are monitored and controlled to equally share the static current among the phases. the ISL9506 disables pwm2 when lp is asserted low, and the power monitor pin provides an analog signal representing the output power of the converter. start-up timing with the controller's +5v v dd voltage above the por threshold, the start-up sequence begins when vr_en exceeds the 3.3v logic high threshold. approximately 120s later soft and v out start ramping up to the start voltage of 1.2v. during this interval, the soft capacitor is charged with approximately 40a. therefore, if the soft capacitor is selected to be 20nf, the soft ramp will be at about 2mv/s for a soft-start time of 600s. once v out is within 10% of the start voltag e for 13 pwm cycles (43s for frequency = 300khz), then pgd_n is pulled low and the soft capacitor is charged up with approximately 200a. therefore, v out slews at +10mv/s to the voltage set by the vsel pins. approximately 7ms later, pgood is asserted high. a typical start-up timing is shown in figure 42. similar results occur if vr_en is tied to v dd , with the soft-start sequence starting 120s after v dd crosses the por threshold. static operation voltage regulation at zero load current after the start sequence, the output voltage will be regulated to the value set by the vsel inputs per table 1. the ISL9506 will control the no-load output voltage to an accuracy of 0.5% over the range of 0.75v to 1.5v. table 1. voltage selection table vsel5 vsel4 vsel3 vsel2 vsel1 vsel0 vsel6=0 vsel6=1 0000001. 5000 0.7000 0000011. 4875 0.6875 0000101. 4750 0.6750 0000111. 4625 0.6625 0001001. 4500 0.6500 0001011. 4375 0.6375 0001101. 4250 0.6250 0001111. 4125 0.6125 0010001. 4000 0.6000 0010011. 3875 0.5875 0010101. 3750 0.5750 0010111. 3625 0.5625 0011001. 3500 0.5500 0011011. 3375 0.5375 0011101. 3250 0.5250 0011111. 3125 0.5125 0100001. 3000 0.5000 010001 1.2875 0.4875 0100101. 2750 0.4750 figure 42. soft-start waveforms using a 20nf soft capacitor 120s 2mv/s 10mv/s ~7ms v dd vr_en soft & vo pgd_n vsel commanded voltage 1.2v pgood 13 switching cycles 90% ISL9506
17 fn6722.0 august 13, 2008 a differential amplifier allows voltage sensing for precise voltage regulation at the point of load. the inputs to the amplifier are the vsen and rtn pins. droop impedance or droop accomplishment as the load current increases from zero, the output voltage will drop from the vsel ta ble value by an amount proportional to load current to achieve certain droop characteristics or droop impedance. the ISL9506 provides for current to be sensed using resistors in series with the channel inductors as shown in the application circuit of figure 40 or using the intrinsic series resistance of the inductors as shown in the applic ation circuit of figure 39. in both cases, signals representing the inductor currents are summed at vsum which is the non-inverting input to the droop amplifier shown in the block diagram of figure 41. the voltage at the droop pin minus the output voltage at vo pin is the total load current multiplied by a gain factor. this value is used as an input to the differential amplifier to achieve the desired droop impeda nce as well as the input of the overcurrent circuit. when using inductor dcr current sensing, a single ntc element is used to compensate the positive temperature coefficient of the copper winding thus sustaining the load-line accuracy with reduced cost. phase current balance in addition to the total current which is used for droop and ocp, the individual channel average currents are also monitored by the phase node voltage. channel current differences are sensed by comparing isen1, isen2, and isen3 voltage. the ibal circuit will adjust the channel pulse-widths up or down relative to the other channels to cause the voltages presented to the isen pins to be equal. enable and disable phases the ISL9506 controller can be configured for three-, two- or single-channel operation. to disable channel 2 and/or channel 3, its pwm output pin should be tied to +5v and the isen pins should be grounded. in three-channel operation, the three-channel pwm's are phase shifted by 120, and in two-channel operation they are phase shifted by 180. 0100111. 2625 0.4625 0101001. 2500 0.4500 0101011. 2375 0.4375 0101101. 2250 0.4250 0101111. 2125 0.4125 0110001. 2000 0.4000 0110011. 1875 0.3875 0110101. 1750 0.3750 0110111. 1625 0.3625 0111001. 1500 0.3500 0111011. 1375 0.3375 0111101. 1250 0.3250 0111111.11250. 3125 1000001. 1000 0.3000 1000011. 0875 off 1000101. 0750 off 1000111. 0625 off 1001001. 0500 off 1001011. 0375 off 1001101. 0250 off 1001111. 0125 off 1010001. 0000 off 1010010. 9875 off 1010100. 9750 off 1010110. 9625 off 1011000. 9500 off 1011010. 9375 off 1011100. 9250 off 1011110. 9125 off 1100000. 9000 off 1100010. 8875 off 1100100. 8750 off 1100110. 8625 off 1101000. 8500 off 1101010. 8375 off 1101100. 8250 off 1101110. 8125 off 1110000. 8000 off 1110010. 7875 off 1110100. 7750 off table 1. voltage selection table (continued) vsel5 vsel4 vsel3 vsel2 vsel 1 vsel0 vsel6=0 vsel6=1 1110110. 7625 off 1111000. 7500 off 1111010. 7375 off 1111100. 7250 off 1111110. 7125 off table 1. voltage selecti on table (continued) vsel5 vsel4 vsel3 vsel2 vsel1 vsel0 vsel6=0 vsel6=1 ISL9506
18 fn6722.0 august 13, 2008 switching frequency in ccm/dcm mode the switching frequency is adjust ed by the resistor between the error amplifier output and the vw pin. when ISL9506 is in continuous conduction mode (ccm), the switching frequency may not be as constant as that of a fixed frequency pwm controllers. however, the switching frequency variation will be kept small to maintain the output voltage ripple within specification. in general, the switching frequency will be very close to the set value at high input voltage and heavy load conditions. when de_en is high and de_enn is low, the fccm pin will become low, and discontinuous conduction mode (dcm) operation will be allowed in the isl6208 gate drive. in dcm, isl6208 turns off the lower fet after its channel current across zero. as load is further reduced, channel switching frequency will drop, providing optimized efficiency at light load. fccm logic low is the signal to enable, or to allow the dcm operation. only if the inductor current is really cross zero, does the true dcm occur. dynamic operation refer to figure 43. the ISL9506 responds to changes in vsel command voltage by slewing to new voltages with a dv/dt set by the soft capacitor and by the state of de_en. with c soft = 20nf and de_en is high, the output voltage will move at 2mv/s for large changes in voltage. for de_en low, the large signal dv/dt will be 10mv/s. as the output approac hes the vsel comm and voltage, the dv/dt rate moderates to prevent overshoot. during geyserville iii transitions where there is one lsb vsel step each 5s, the controller will follow the vsel command with its dv/dt rate of 2.5mv/s. keeping de_en high during vsel transitions will result in reduced dv/dt slew rate and lesser audio noise. for fastest recovery from diode emulation to nominal mode, de_en low achieves higher dv/dt. intersil's r 3 intrinsically has voltage-feed-forward. the output voltage is insensitive to a fast slew input voltage change. refer to figure 15 in the ?typical operating performance? on page 8? section of this document for input transient performance. the hysteresis window voltage is constructed with a resistor on the vw pin to the error amplifier outputs. the synthesized inductor current ripple signal compares with the window voltage and generates pwm signal. at load current step-up, the switching frequency is increased resulting in a faster response than conventional fixed frequency pwm controllers. as all the phases shares the same hysteretic window voltage, it also ensures excellent dynamic current balance between phases. the individual average phase voltages are monitored and controlled to achieve steady st ate current balance among the phases with current balance loop. modes of operation programmed by logic signals the operational modes of ISL9506 are programmed by the control signals of de_en, de_enn, and lp. ISL9506 responds lp signal by adding or dropping pwm2 and adjusting the overcurrent protection level accordingly. for example, if the ISL9506 is initially used as 3-phase controller, the lp signal will add or drop pwm2 and leave pwm1 and pwm3 always in operation. meanwhile, after pwm2 is dropped, the phase shift between the pwm1 and pwm3 is adjusted from 120 to 180 and the overcurrent and the way-overcurrent protection level will be adjusted to 2/3 of the initial value. if th e ISL9506 is initially used as 2-phase operation, it is sugg ested that pwm1 and pwm2 pair, not pwm1 and pwm3 pair, should be used such that the lp signal will enable or disable pwm2 with pwm1 in operation always. the overcurrent and way-overcurrent protection level in two-to-one phase mode operation will be adjusted as two-to-one as well. the dcm mode operation is independent of lp for ISL9506. it responds to the de_en and de_enn. table 2 shows the operation modes of ISL9506 with combinations of control logic. when lp is de-asserted low, isen2 pin is connected to the isen pins of the operationa l phases internally to keep proper current balance and minimize the inductor current overshoot and undershoot wh en the disabled phase is enabled again. figure 43. diode emulation transition showing de_en?s effect on exit slew rate vout 2mv/s -2mv/s vsel6 de_en de_enn 10mv/s table 2. ISL9506 mode of operations de_en de_enn lp mode of operation mode 0 1 1 n phase ccm nominal 0 1 0 n-1 phase ccm low power 1 0 1 n phase dcm diode emulation 1 0 0 n-1 phase dcm diode emulation 0 0 1 n phase ccm 0 0 0 n-1 phase ccm 1 1 1 n phase ccm 1 1 0 n-1phase ccm ISL9506
19 fn6722.0 august 13, 2008 protection the ISL9506 provides overcurrent, overvoltage, and undervoltage protection. overcurr ent protection is related to the voltage droop which is determined by the droop impedance requirement. after the load-line is set, the ocset resistor can be selected to detect overcurrent at any level of droop voltage. for overcurrent less that 2.5x the ocset level, the overload condition must exist for 120s in order to trip the oc fault latch. this is shown in figure 28. for overload exceeding 2.5x the ocset level, the pwm outputs will immediately shut off and pgood will go low to maximize protection due to hard short circuit. this protection was referred to as way-overcurr ent or fast over current, for short-circuit protections. in addition, excessive phase unbalance due to gate driver failure will be detected and will shut down the controller. the phase unbalance is detected by the voltage on the isen pin. if the isen pin voltage differenc e is greater than 9mv for 1ms, the controller will latch off. undervoltage protection is independent of the overcurrent limit. if the output voltage is less than the vsel set value by 300mv or more, a fault will latch after 1ms in that condition. the pwm outputs will turn off and pgood will go low. this is shown in figure 27. note that most practical core voltage regulators will have the overcurrent set to trip before the -300mv undervoltage limit. there are two levels of overvo ltage protection with different responses. the first level of overvoltage protection is referred to as pgood overvoltag e protection. basically, for output voltage exceeding the set value by +200mv for 1ms, a fault will be declared with pgood latched low. all of the above faults have the same action taken: pgood is latched low and the upper and lower power fets are turned off so that inductor current will decay through the fetbody diodes. this condition can be reset by bringing vr_en low or by bringing v dd below por threshold. when these inputs are returned to their high operating levels, a soft-start will occur. the second level of overvoltage protection behaves differently. if the output e xceeds 1.7v, an ov fault is immediately declared, pgoo d is latched low and the low-side fets are turned on. the low-side fets will remain on until the output voltage is pulled down below 0.85v at which time all fets are turned off. if the output again rises above 1.7v, the process is repeated. this affords the maximum amount of protection against a shorted high-side fet while preventing output ringi ng below ground. the 1.7v ovp cannot be reset with vr_en, but requires that v dd be lowered to reset. the 1.7v ov detector is nominal at all times when the controller is enabled including after one of the other faults occurs. this ensures the load is protected against high-side fet leakage while the fets are commanded off. the ISL9506 has a thermal throttling feature. if the voltage on t he ntc pin goes below the 1.18v ot threshold, the vrhot# pin is pulled low indicating the need for thermal throttling to the system oversight load. no other action is taken within the ISL9506 in response to ntc pin voltage. fault protection is summarized in table 3. power monitor the power monitor signal is an analog output. its magnitude is proportional to the product of vsen and the voltage difference between v droop and v o , which is the programmed droop impedance multiplied by load current. the output voltage of the pmon pin is given by: the power consumed by the load can be calculated by: where the 0.0021 is the droop impedance.the power monitor load regulation is about 7 . basically, within its table 3. the fault protection and reset operation of ISL9506 fault duration prior to protection protection actions fault reset overcurrent 120s pwms tri-state, pgood latched low vr_en toggle or vdd toggle way-overcurrent (2.5 x oc) <2s pwms tri-state, pgood latched low vr_en toggle or vdd toggle overvoltage 1.7v immediately low side mo sfet on until vcore <0.85v, then pwm tri-state, pgood latched low. vdd toggle overvoltage +200mv 1ms pwms tri-state, pgood latched low vr_en toggle or vdd toggle undervoltage -300mv 1ms pwms tri-state, pgood latched low vr_en toggle or vdd toggle phase-current unbalance 1ms pwms tri-state, pgood latched low vr_en toggle or vdd toggle over-temperature immediately vrhot# goes low n/a v pmon v sen * (v droop v o ) *17.5 (volt) ? = (eq. 1) p load v pmon /(17.5*0.0021) (watt) = (eq. 2) ISL9506
20 fn6722.0 august 13, 2008 sourcing/sinking current cap ability range, when the power monitor loading changes 1ma, the output of the power monitor will change 7mv. the 7 impedance is associated with the layout and packaging resi stance of pmon pin inside the ic. compared to the load resistance on the power monitor pin in practical applications, 7 output impedance contributes no significance of error. component selection and application soft-start and mode change slew rates the ISL9506 uses 2 slew rates for various modes of operation. the first is a slow slew rate, used to reduce inrush current on start-up. it is also used to reduce audible noise when entering or exiting diode emulation mode. a faster slew rate is used to exit out of diode emulation and to increase system performance by achieving nominal mode regulation more quickly. no te that the soft capacitor current is bidirectional and is flowing into the soft capacitor when the output voltage is commanded to rise, and out of the soft capacitor when the output voltage is commanded to fall. the two slew rates are determined by the currents into the soft pin. as can be seen in figure 44, the soft pin has a capacitance to ground. also, the soft pin is the input to the error amplifier and is, therefore, the commanded system voltage. depending on the state of the system, i.e. start-up or nominal mode, and the state of the de_en pin, one of the two currents shown in figure 44 will be used to charge or discharge this capacitor, thereby controlling the slew rate of the commanded voltage. these currents can be found under the soft current section of the electrical specifications table on page 4. the first current, labeled i ss , is given in the specification table as 42a. this current is used during soft-start. the second current, i 2 sums with i ss to get the large current labeled i gv in the electrical specifications table on page 4 this total current is typically 205 a with a minimum of 180a. the desired v out slew rate will determine the choice of the soft capacitor, c soft , by equation 3: using a slewrate of 10mv/s, and the typical i gv value, given in the electrical specification table of 205a, c soft is calculated by using equation 4: a choice of 0.015f would guarantee a slewrate of 10mv/s is met for minimum i gv value, given in the electrical specifications table on page 4 now this choice of c soft will then control the start-up slewrate as well. one should expect the output voltage to slew to the start value of 1.2v at a rate given by equation 5: generally, when output voltage is approaching its steady state, its dv/dt will slow down to prevent overshoot. in order to compensate the slow-down effe ct, faster initial dv/dt slew rates can be used with small soft capacitors such as 10nf to achieve the desired overall dv/dt in the allocated time interval. selecting r bias to properly bias the ISL9506, a reference current is established by placing a 147k , 1% tolerance resistor from the r bias pin to ground. this will provide a highly accurate, 10a current source from which ocset reference current can be derived. care should be taken in layout that the resistor is placed very close to the r bias pin and that a good quality signal ground is connected to the opposite side of the r bias resistor. do not connect any other components to this pin. capacitance on this pin would create instabilities and should be avoided. start-up operation - pgd_n and pgood the ISL9506 provides a 3.3v logic output pin for pgd_n. the 3v3 pin allows for a system 3.3v source to be connected to separated circuitry inside the ISL9506, solely devoted to the pgd_n function. the output is a 3.3v cmos signal with 4ma of source and sinking capability. this implementation removes the need for an external pull-up resistor on this pin, and due to the normal level of this signal being a low, removes the leakage path from the 3.3v supply to ground through the pull-up resistor. this reduces 3.3v supply current, that would oc cur under normal operation with a pull-up resistor, and prolongs battery life. the 3.3v supply should be decoupled to digital ground, not to analog ground for noise immunity. figure 44. soft pin current sources for fast and slow slew rates c soft soft ISL9506 i ss + v ref i 2 + error amplifier c soft i gv slewrate ----------------------------------- - = (eq. 3) c soft 205 a 10mv 1 s ---------------- ----------------- - 0.0205 f == (eq. 4) dv dt ------- i ss c soft ------------------- 42 a 0.015 f ---------------------- - 2.8 mv s -------- - == = (eq. 5) ISL9506
21 fn6722.0 august 13, 2008 as mentioned in the ??theory of operation? on page 16 section of this data sheet, pgd_n is logic level high at start- up. when the output voltage r eaches 90% of start voltage, a counter is enabled, it counts 13 switching cycles (about 43s for 300khz operation) then pgd_n goes low. this in turn triggers an internal timer for the pgood signal. this timer allows pgood to go high approximately 7ms after pgd_n goes low. static mode of operation - remote voltage sensing remote voltage sensing allows the voltage regulator to compensate for various resist ive drops in the power path and insure that the voltage seen at the point of load is the correct level independent of load current. the vsen and rtn of the ISL9506 are the kelvin connection pins to the point of load. this allows the voltage regulator to tightly control the output voltage at the point of load, independent of layout inc onsistencies and drops. this kelvin sense technique provid es for extremely tight droop impedance regulation. these traces should be laid out as noise sensitive traces. for optimum droop impedance re gulation performance, the traces connecting these two pins to the kelvin sense point of the load must be laid out in parallel and away from rapidly rising voltage nodes (switching nodes) and other noisy traces. to achieve optimum performance, place common mode and differential mode rc filters to analog ground on vsen and rtn as shown in figu re 46. however, the filter resistors should be in order of 10 so that they do not interact with the 50k input resistance of the differential amplifier. due to the fact that the voltage feedback to the switching regulator is sensed at the poin t of load, there exists the potential of an overvoltage due to an open circuit feedback signal, should the regulator be operated without the load installed. due to this fact, we recommend the use of the r opn1 and r opn2 connected to v out and ground as shown in figure 46. these resistors will provide voltage feedback in the event that the system is powered up without the load installed. these resistors are typically 100 . setting the switching frequency - fset the r 3 modulator scheme is not a fixed frequency pwm architecture. the switching frequency can increase during the application of a load to improve transient performance. however, it also varies slightly due changes in input and output voltage and output current, but this variation is normally less than 10% in continuous conduction mode. refer to figure 39. a resistor connected between the vw and comp pins of the is l9506 adjusts the switching window, and therefore adjusts the switching frequency. the r fset resistor that sets up th e switching frequency of the converter operating in ccm can be determined using the following relationship, where r fset is in k and the switching period is in s. in discontinuous conduction mode, (dcm), the ISL9506 runs in period stretching mode. it should be noted that the switching frequency in the elec trical specification table is tested with the error amplifier output or comp pin voltage at 2v. when comp pin voltage is lower, the switching frequency will not be at the tested value but can still maintain the output voltage ripple within specification. voltage regulator thermal throttling the ISL9506 features a thermal monitor which senses the voltage change across an externally placed negative temperature coefficient (ntc) thermistor, see figure 45. proper selection and placemen t of the ntc thermistor allows for detection of a designated temperature rise by the system. figure 45 shows the thermal throttling feature with hysteresis. at low temperature, sw1 is on and sw2 connects to the 1.20v side. t he total current going from ntc pin is 60a. the voltage on ntc pin is higher than threshold voltage of 1.20v and the compar ator output is low. vrhot# is pulling up high by the external resistor. when temperature increases, t he ntc thermistor resistance on ntc pin decreases. the voltage on ntc pin decreases to a level lower than 1.20v. the comparator changes polarity and turns sw1 off and throws sw2 to 1.24v. this pulls vrhot# low and sends the signal to start thermal throttle. there is a 6a current reduction on ntc pin and 40mv voltage increase on threshold voltage of the comparator in this state. the vrhot# signal will be used to change the load operation and decrease the power consumption. when the temperature goes down, th e ntc thermistor voltage will eventually go up. if ntc voltage increases to 1.24v, the comparator will then be able to flip back. the external rfset k () period s () 0.29 ? () 2.33 = (eq. 6) ntc r ntc - + v ntc - + vrhot# 1.24v 54a internal to ISL9506 figure 45. circuitry associated with the thermal throttling feature of the ISL9506 r s 6a 1.20v sw1 sw2 ISL9506
22 fn6722.0 august 13, 2008 resistance difference in these two conditions as shown in equation 7: therefore, proper ntc thermist or has to be chosen such that 2.96k resistor change will be corresponding to required temperature hysteresis. regula r external resistor may need to be in series with ntc resistors to meet the threshold voltage values. the following is an example. for panasonic ntc thermistor wi th b = 4700, its resistance will drop to 0.03322 of its nominal at 105c, and drop to 0.03956 of its nominal at 100 c. if the requirement for the temperature hysteresis is (105-100) c, the required resistance of ntc will be: therefore a larger value thermistor, such as 470k ntc should be used. at 105c, 470k ntc resistance becomes: (0.03322*470k) = 15.6k. with 60a on ntc pin, the voltage is only (15.6k*60a) = 0.937v. th is value is much lower than the threshold voltage of 1.20v. therefore, a resistor is needed to be in series with the ntc. the required resistance can be calculated by using equation 9: 4.42k is a standard resistor value. therefore, the ntc branch should have a 470k ntc and 4.42k resistor in series. the part number for the ntc th ermistor is ertj0ev474j. it is a 0402 package. ntc thermistor will be placed in the hot spot of the board. static mode of operation - static droop using dcr sensing as previously mentioned, the ISL9506 has an internal differential amplifier which provides for extremely accurate voltage regulation at the point of load. the droop impedance regulation is also very accurate, and the process of selecting the components for the appropriate droop impedance is explained here. for dcr sensing, the process of compensation for dcr resistance variation to achiev e the desired droop impedance has several steps and is somewhat iterative. in figure 46 we show a 3 phase solution using dcr sensing. there are two resistor s around the inductor of each phase. these are labeled rs a nd ro. these resistors are used to sense the dc voltage drop across each inductor. each inductor will have a certain level of dc current flowing through it, this current when multiplied by the dcr of the inductor creates a small dc le vel of voltage. when this voltage is summed with the other channels dc voltages, the total dc load current can be derived. ro is typically 5 to 10 . this resistor is used to tie the outputs of all channels togethe r and thus create a summed average of the local core volt age output. rs is determined through an understanding of both the dc and transient load currents. this value will be covered in the next section. however, it is important to keep in mind that the output of each of these rs resistors are tied together to create the vsum voltage node. with both the outputs of ro and rs tied together, the simplified model for the droop circuit can be derived. this is presented in figure 47. figure 47 shows the simplified model of the droop circuitry. essentially one resistor can repl ace the ro resistors of each phase and one rs resistor can replace the rs resistors of each phase. the total dcr drop due to load current can be replaced by a dc source, the value of which is given by equation 10. where n is the number of channels designed for nominal operation. another simplifica tion was done by reducing the ntc network comprised of r ntc , r series and r parallel , given in figure 46, to a single resistor given as rn as shown in figure 47. the first step in droop impedance compensation is to adjust rn, ro eqv and rs eqv such that sufficient droop voltage exists even at light loads be tween the vsum and vo? nodes. we recognize that these components form a voltage divider. as a rule of thumb we start with the voltage drop across the rn network, vn, to be 0.57 x v dcr . this ratio provides for a fairly reasonable amount of light load signal from which to arrive at droop. first we calculate the equivalent ntc network resistance, rn. typical values that provide good performance are, rseries = 3.57k_1%, r par = 4.53k_1% and r ntc = 10k ntc, ert-j1vr103j from panasonic. rn is then given by equation 11. in our second step, we calculate the series resistance from each phase to the v sum node, labeled rs1, rs2 and rs3 in figure 46. 1.24v 54 a --------------- - 1.20v 60 a --------------- - ? 2.96k = (eq. 7) (eq. 8) 2.96k 0.03956 0.03322 ? () ----------------------------------------------------- - 467k = (eq. 9) 1.20v 60 a --------------- - 15.6k ? 4.4k = vdcr eqv i out dcr n --------------------------------- - = (eq. 10) rn rseries rntc + () rpar rseries rntc rpar ++ -------------------------------------------------------------------- 3.4k == (eq. 11) ISL9506
23 fn6722.0 august 13, 2008 we do this using the assumption that we desire approximately a 0.57 gain from the dcr voltage, v dcr , to the rn network. we call this gain, g1. after simplification, then rs eqv is given by equation 13: the individual resistors from each phase to the vsum node, labeled rs1, rs2 and rs3 in figure 46, are then given by equation 14, where n is 3, fo r the number of channels in nominal operation. choosing rs = 7.68k_1% is a good choice. once we know the attenuation of the rs and rn network, we can then determine the droop amplifier gain required to achieve the droop impedance. setting rdr p1 = 1k_1%, then rdrp2 is can be found using equation 15. setting n = 3 for 3 channel operation, droop impedance (rdroop) = 0.0021 (v/a) as pe r the desired specification. figure 47. equivalent model for droop and remote sensing using dcr sensing figure 46. equivalent model for droop and remote sensing using dcr sensing c bulk esr vsum vsum vsum vo' vo' vo' v out i phase1 i phase2 i phase3 rs1 rs2 rs3 ro3 ro2 ro1 internal to isl6260 1 + - rtn vsum dfb vo' vdiff vsen oc + - ocset 1 + - + + droop 10a droop + - vo' vo' r ocset vsum r drp2 r drp1 cn r par r ntc r series isen1 isen2 isen3 isen3 isen2 isen1 v dcr 1 l 1 dcr + - v dcr 2 l 2 dcr + - v dcr 3 l 3 dcr + - isen3 r l3 c l3 isen2 r l2 c l2 isen1 r l1 c l1 vcc_sense vss_sense 10 0.01f 0.22f to processor socket k elvin connections r opn1 r opn2 to v out ISL9506 to po int o f load v out internal to isl6260 1 + - rtn vsum dfb vo' vdiff vsen oc + - ocset 1 + - + + droop 10ua droop + - vo' vsum rdrp2 rdrp1 c n n dcr iout vdcr eqv = n rs rs eqv = ( ) () rpar rseries rntc rpar rseries rntc rn + + + = n ro ro eqv = + vn - ISL9506 g1 0.57 = (eq. 12) rs eqv 1 g1 ------- - 1 ? ?? ?? rn 2.56k == (eq. 13) rs n rs eqv 7.69k == (eq. 14) rdrp2 n rdroop dcr g1 -------------------------------- 1 ? ?? ?? rdrp1 = (eq. 15) ISL9506
24 fn6722.0 august 13, 2008 dcr = 0.0012 typical, rdrp1 = 1k and the attenuation gain (g1) = 0.57, rdrp2 is then: rdrp2 is selected to be a 8.25k_1% resistor. note, we choose to ignore the ro resistors because they do not add significant error. these values are extremely sensitive to layout and coupling factor of the ntc to the inductor. as only one ntc is required in this application, this ntc should be placed as close to the channel 1 inductor as possible. and very importantly, the pcb traces sensing the inductor voltage should be go directly to the inductor pads. once the board has been laid out, some adjustments may be required to adjust the full load droop voltage. this can be accomplished by allowing the system to achieve thermal equilibrium at full load, and then adjusting rdrp2 to obtain the appropriate droop impedance. to see whether the ntc has compensated the temperature change of the dcr, the user c an apply full load current and wait for the thermal steady state and see how much the output voltage will deviate from the initial voltage reading. a good ntc thermistor compensat ion can limit the output voltage drift to 2mv. if the output voltage is decreasing with temperature increase, that ratio between the ntc thermistor value and the rest of the resistor divider network has to be increased. users should use the ISL9506 evaluation board component values and follow t he evaluation board layout of ntc as much as possible to minimize engineering time. the desired droop impedance should be adjusted by rdrp2 based on maximum current steps, not based on small current steps. basically, if the max current is 40a, the required droop voltage is 84mv with 2.1m droop impedance. the user should have 40a load current on the converter and look for 84mv droop. if the droop voltage is less than 84mv, for example, 80mv. the new value will be calculated by equation 17: for the best accuracy, the equi valent resistance on the dfb and vsum pins should be identical so that the bias current of the droop amplifier does not cause an offset voltage. in the example above, the resistance on the dfb pin is rdrp1 in parallel with rdrop2, that is , 1k in parallel with 8.21k or 890 . the resistance on the vsum pin is rn in parallel with rseqv or 3.4k in parallel with 2.56k or 1460 . the mismatch in the effective resistances is 1460 - 890 = 570 . to reduce the mismatch, multiply both rdrp1 and rdrp2 by the appropriate factor. the appropriate factor in the example is 1460/890 = 1.64. dynamic mode of operation - dynamic droop using dcr sensing droop is very important for load transient performance. if the system is not compensated correctly, the output voltage could sag excessively upon load application and potentially create a system failure. the out put voltage could also take a long period of time to settle to its final value. the l/dcr time constant of th e inductor must be matched to the rn*cn time constant as shown in equation 18: solving for cn we now have equation 19: note, ro was neglected. as long as the inductor time constant matches the droop circuit rc time constants as given above, the transient per formance will be optimum. the selection of cn may require a sl ight adjustment to correct for layout inconsistencies and component tolerance. for the example of l = 0.5 h, cn is calculated in equation 20: the value of this capacitor is selected to be 27nf. as the inductors tend to have 20% to 30% tolerances, this cap generally will be tuned on the board by examining the transient voltage. if the output voltage transient has an initial dip, lower than the voltage required by the droop impedance, and is slowly increasing back to the steady state, the capacitor should be increased and vice versa. it is better to have the capacitor value a little bigger to cover the tolerance of the inductor to prevent the output voltage from going lower than the spec. this capacitor needs to be a high grade capacitor like x7r with low tolerance. there is another consideration in order to achieve better time constant match mentioned above. the npo/cog (class-i) capacitors have only 5% tolerance and a very good thermal characteristics. but those capacitors are only available in small capacitance values. in order to use such capacitors, the resistors and thermistors surrounding the droop voltage sensing and droop amplifier has to be resized up to 10x to reduce the capacitance by 10x. but attention has to be paid in balancing the impedance of droop amplifier in this case. dynamic mode of operation - compensation parameters considering the voltage regulator as a black box with a voltage source controlled by vsel and a series impedance, in order to achieve certain droop impedance, the series impedance inside the black box needs to be this desired rdrp2 3 0.0021 0.0012 0.57 ----------------------------------- - 1 ? ?? ?? 1k 8.21k = = (eq. 16) 1 rdrp ) 2 rdrp 1 rdrp ( mv 80 mv 84 new _ 2 rdrp ? + = (eq. 17) l dcr ------------- rn rs eqv rn rs eqv + ---------------------------------- - ?? ?? ?? cn = (eq. 18) cn l dcr ------------- rn rs eqv rn rs eqv + ---------------------------------- - ?? ?? ?? ---------------------------------------- - = (eq. 19) cn 0.5 h 0.0012 ----------------- - 3.4k 2.56k 3.4k 2.56k + ------------------------------------------- ?? ?? ------------------------------------------------ - 28.5nf == (eq. 20) ISL9506
25 fn6722.0 august 13, 2008 value. the compensation design has to ensure the output impedance of the converter be lower than this desired value. there is a mathematical calculat ion file available to the user. the power stage parameters such as l and cs are needed as the input to calculate the compensation component values. attention has be paid to the input resistor to the fb pin. too high of a resistor will cause an error to the output voltage regulation because of bias current flowing in the fb pin. it is better to keep this resistor below 3k when using this file. static mode of operation - current balance using dcr or discrete resistor current sensing current balance is achieved in the ISL9506 through the matching of the voltages present on the isen pins. the ISL9506 adjusts the duty cycles of each phase to maintain equal potentials on the isen pins. rl and cl around each inductor, or around each discrete current resistor, are used to create a rather large time constant such that the isen voltages have minimal ripple voltage and represent the dc current flowing through each channel?s inductor. for optimum performance, rl is chosen to be 10k and cl is selected to be 0.22f. when di screte resistor sensing is used, a capacitor of 10nf should be placed in parallel with rl to properly compensate the current balance circuit. 1. ISL9506 uses rc filter to sense the average voltage on phase node and forces the average voltage on the phase node to be equal for current balance. even though the ISL9506 forces the isen voltages to be almost equal, the inductor currents will not be exactly the same. take dcr current sensing as example, two errors have to be added to find the total current imbalance. 1) mismatch of dcr: if the dcr has a 5% tolerance, then the resistors could mismatch by 10% worst case. if each phase is carrying 20a then the phase currents mismatch by 20a*10% = 2a. 2) mismatch of phase voltages/offset voltage of isen pins. the phase voltages are within 2mv of each other by current balance circuit. the error current that results is given by 2mv/dcr. if dcr = 1m then the error is 2a. in the above example, the two errors add to 4a. for a two phase dc/dc, the currents would be 22a in one phase and 18a in the other phase. in t he above analysis, the current balance can be calculated with 2a/20a = 10%. this is the worst case calculation, for exam ple, the actual tolerance of two 10% dcrs is 10%*sqrt(2) = 7%. there are provisions to correc t the current imbalance due to layout or to purposely divert current to certain phase for better thermal management. customer can put a resistor in parallel with the current sensing capacitor on the phase of interest in order to purposely increase the cu rrent in that phase. it is highly recommended to use symmetrical layout in order to achieve natural current balance. in the case the pcb board trace resistance from the inductor to the point of load are not the same on all three phases, the current will not be balanced. on the phases that have too much trace resistance a resistor can be added in parallel with the isen capacitor that wil l correct for the poor layout. an estimate of the value of the resistor is: where risen is the resistance from the phase node to the isen pin; usually 10k . rdcr is the dcr resistance of the inductor. rtrace is the trace resistance from the inductor to the point of load on the phase that needs to be tweaked. it should be measured with a good micro meter. r min is the trace resistance from the inductor to the load on the phase with the least resistance. for example, if the pc board trace on one phase is 0.5m and on another trace is 0.3m ; and if the dcr is 1.2m ; then the tweaking resistor is for extremely unsymmetrical layout causing phase current unbalance, ISL9506 applications schematics can be modified to correct the problem. droop using discrete resistor sensing - static/ dynamic mode of operation when choosing current sense resistor, not only the tolerance of the resistance is important, but also the tcr. thus, its combined tolerance at a wide temperature range should be calculated. figure 48 shows the equivalent circuit of a discrete current sense approach. figure 40 shows the simplified schematic of this approach. for discrete resistor current sensing circuit, the droop circuit parameters can be solved the same way as the dcr sensing approach with a few slight modifications. first, there is no ntc requ ired for thermal compensation, therefore, the rn resistor netw ork in the previous section is not required. secondly, there is no time constant matching required, therefore, the cn component is not needed to match the l/dcr time constant, but this component does indeed provide noise immunity, especially to noise voltage caused by the esl of the current sensing resistors. a 47pf capacitor can be used for such purposes. the rs values in the previous section, rs = 7.68k_1% are sufficient for this approach. now, the input to the droop amplifier is the v rsense voltage. this voltage is given by equation 23: the gain of the droop amplifie r, g2, must be adjusted equal to the droop impedance. see equation 24: rtweak = risen* [2*rdcr - (rtrace - rmin)]/[2(rtrace - rmin)] (eq. 21) rtweak = 10kw* [2*1.2 - (0.5 - 0.3)]/[2*(0.5 - 0.3)] = 55k (eq. 22) vrsense rsense n ------------------- - i out = (eq. 23) g2 rdroop rsense ---------------------- n = (eq. 24) ISL9506
26 all intersil u.s. products are manufactured, asse mbled and tested utilizing iso9000 quality systems. intersil corporation?s quality certifications ca n be viewed at www.intersil.com/design/quality intersil products are sold by description only. intersil corpor ation reserves the right to make changes in circuit design, soft ware and/or specifications at any time without notice. accordingly, the reader is cautioned to verify that data sheets are current before placing orders. information furnishe d by intersil is believed to be accurate and reliable. however, no responsibility is assumed by intersil or its subsidiaries for its use; nor for any infringements of paten ts or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of intersil or its subsidiari es. for information regarding intersil corporation and its products, see www.intersil.com fn6722.0 august 13, 2008 assuming n = 3, rdroop = 0.0021(v/a) as per the desired specification, rsense = 0.001 , we obtain g2 = 6.3. the values of rdrp1 and rdrp2 are selected to satisfy two requirements. first, the ratio of rdrp2 and rdrp1 determine the gain g2 = (rdrp2/rdrp1)+1. second, the parallel combination of rdrp1 and rdrp2 should equal the parallel combination of the rs resistors. combining these requirements gives: rdrp1 = g2/(g2-1) * rs/n rdrp2 = (g2-1) * rdrp1 in the example above, rs = 7. 68k, n = 3, and g2 = 6.3 so rdrp 3k and rdrp2 is 15.8k . these values are extremely sensitive to layout. once the board has been laid out, some tweaking may be required to adjust the full load droop. this is fairly easy and can be accomplished by allowing the system to achieve thermal equilibrium at full load, and then adjusting rdrp2 to obtain the desired droop value. power monitor the power monitor signal tracks the inductor current. due to the dynamic operation of the l oad, the inductor current is pulsating and the power monitor signal needs to be filtered. if the rc filter is followed by an a/d converter, the input impedance of the a/d converter needs to be much larger than the resistor used for the rc filter. otherwise, the input impedance of the a/d converter a nd the rc filter resistor will construct a resistor divider causing the a/d converter reading incorrect information. it is desirable to choose a small rc filter resistor in order to reduce the resistor divider effect. the ISL9506 comes with a very strong current sinking capability, users can use k resistors for the rc filter. some a/d converters might have 100k input impedance, 1k resistor will cause 1% error. as shown in figure 36, when the load is at 2.5a, pmon can still sink 0.6ma current. this allows the rc filter capacitor to discharge when the load is at low current, thus providing correct average power information on the capacitor. fault protection - overcurrent fault setting as previously described, the ov ercurrent protection of the ISL9506 is related to the droop voltage. previously we have calculated that the droop voltage = i load *rdroop, where rdroop is the droop impedance. knowing this relationship, the overcurrent protection threshold can be set up as a voltage droop level. knowing this voltage droop level, one can program in the appropriate drop across the roc resistor. this voltage drop will be referred to as voc. once the droop voltage is greater than voc, the pwm drives will turn off and pgood will go low. the selection of roc is given in equation 25. assuming we desire an overcurrent trip level, ioc, of 55a, and knowin g from the desir ed specification that the droop impedance, rdroop is 0.0021 (v/a), we can then calculate for r oc as shown in equation 25: note, if the droop impedance is not -0.0021 (v/a) in the application, the overcurrent setpoint will differ from predicted. a capacitor may be added in parallel with r oc to improve noise rejection but the roc*capacitor time constant cannot exceed 20s. do not remove r oc if overcurrent protection is not desired. the maximum r oc is 30k. roc ioc rdroop 10 a ------------------------------------ - 55 0.0021 10x10 6 ? ------------------------------ - 11.5k === (eq. 25) internal to 1 + - rtn vsum dfb vo' vdiff vsen oc + - ocset 1 + - + + droop 10a droop + - vo' vsum rdrp2 rdrp1 c n n rsense iout vrsense eqv = n rs rs eqv = n ro ro eqv = + vn - roc + - voc ISL9506 figure 48. equivalent model for droop and remo te sensing using discrete resistor sensing ISL9506
27 fn6722.0 august 13, 2008 ISL9506 package outline drawing l40.6x6 40 lead quad flat no-lead plastic package rev 3, 10/06 located within the zone indicated. the pin #1 identifier may be unless otherwise specified, tolerance : decimal 0.05 tiebar shown (if present) is a non-functional feature. the configuration of the pin #1 identifier is optional, but must be between 0.15mm and 0.30mm from the terminal tip. dimension b applies to the metallized terminal and is measured dimensions in ( ) for reference only. dimensioning and tolerancing conform to amse y14.5m-1994. 6. either a mold or mark feature. 3. 5. 4. 2. dimensions are in millimeters. 1. notes: (4x) 0.15 index area pin 1 a 6.00 b 6.00 31 36x 0.50 4.5 4x 40 pin #1 index area bottom view 40x 0 . 4 0 . 1 20 b 0.10 11 ma c 4 21 4 . 10 0 . 15 0 . 90 0 . 1 c seating plane base plane 0.08 0.10 see detail "x" c c 0 . 00 min. detail "x" 0 . 05 max. 0 . 2 ref c 5 side view 1 10 30 typical recommended land pattern ( 5 . 8 typ ) ( 4 . 10 ) ( 36x 0 . 5 ) ( 40x 0 . 23 ) ( 40x 0 . 6 ) 6 6 top view 0 . 23 +0 . 07 / -0 . 05

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