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low power stereo audio dac with headphone amplifier v ersion 1.0 3/29/2011 1 ES8155 general description features ES8155 is a high performance, low power and low cost audio dac. it consists of 2 - ch dac, headphone amplifier, digital sound effects, and analog mixing and gain functions. the device uses advanced multi - bit delta - sigma modu lation technique to convert data between digital and analog. the multi - bit delta - sigma modulator s make the device with low sensitivity to clock jitter and low out of band noise . dac ? 24- bit, 8 khz to 96 khz sampling frequency ? 96 db dynamic range, 96 db signal to noise ratio, - 83 db thd+n ? 40 mw headphone amplifier, pop noise free, capless option ? stereo enhancement ? 3 - band fully parametric graphic equalizer ? various analog output mixing and gains low power ? 1.8v to 3.3v operation ? 7 mw playback system ? i 2 c or s pi uc interface ? 256fs, 384fs, usb 12 mhz or 24 mhz ? fractional pll for wide range of system clocks ? master or slave serial port ? i 2 s, left justified, right justified, dsp mode applications ordering information ? cell phone ? gps ? mp3, mp4, pmp ? digital camera , camcorder ? bluetooth ? portable audio devices ES8155 - 40 c ~ +85 c qfn - 28
everest semiconductor ES8155 v ersion 1.0 3/29/2011 2 1 block diagram ..................................................................................... 4 2 28- pin qfn and pin desc riptions .................................................... 5 3 typical application circuit ............................................................ 6 4 clock modes and samp ling frequencies .................................. 6 5 micro - controller configura tion interface ......................... 9 5.1 spi ...................................................................................................... 9 5.2 2 - wire ................................................................................................ 10 6 configuration regist er definition .......................................... 11 6.1 output setting ................................................................................... 15 6.1.1 register 0x00 ? lout1 volume, default 0100 0000 .................. 15 6.1.2 register 0x01 ? rout1 volume, default 0100 0000 .................. 15 6.1.3 register 0x02 ? lout2 volume, default 0100 0000 .................. 15 6.1.4 register 0x03 ? rout2 volume, default 0100 0000 .................. 16 6.1.5 register 0x04 ? mout volume, default 0100 0000 ................... 16 6.1.6 register 0x05 ? out control 1, default 0100 0000 ...................... 16 6.1.7 register 0x06 ? out control 2, default 0000 0000 ...................... 17 6.2 mixer setting ..................................................................................... 17 6.2.1 register 0x07 ? left mixer, default 1111 1111 ............................. 17 6.2.2 register 0x08 ? right mixer, default 1111 1111 ........................... 18 6.2.3 register 0x09 ? mono mixer, default 1111 1111 .......................... 18 6.2.4 register 0x0a ? dac to mixer, default 1 011 1111 ....................... 19 6.2.5 register 0x0b ? mixer lp mode, default 0000 0000 .................. 19 6.3 dac setting ....................................................................................... 19 6.3.1 register 0x0c ? left dac volume, default 1100 0000 ............... 19 6.3.2 register 0x0d ? right dac volume, default 1100 0000 ............. 20 6.3.3 register 0x0e ? dac control 1, default 0101 0101 ................... 20 6.3.4 register 0x0f ? dac control 2, default 1100 0100 .................... 20 6.3.5 register 0x10 dac control 3, default 0000 1000 ....................... 21 6.3.6 register 0x11 ? dac control 4, default 0000 0000 ..................... 21 6.3.7 reg ister 0x12 ? shelving1_a[29:24], default 0001 1111 .......... 21 6.3.8 register 0x13 ? shelving1_a[23:16], default 1111 0111 .......... 21 6.3.9 registe r 0x14 ? shelving1_a[15:8], default 1111 1101 ............ 21 6.3.10 register 0x15 ? shelving1_a[7:0], default 1111 1111 .............. 21 6.3.11 register 0x1 6 ? shelving1_b[29:24], default 0001 1111 .......... 21 6.3.12 register 0x17 ? shelving1_b[23:16], default 1111 0111 .......... 22 6.3.13 register 0x18 ? shelving1_b[15:8], default 1111 1101 ............ 22 6.3.14 register 0x19 ? shelving1_b[7:0], default 1111 1111 .............. 22 6.3.15 register 0x1a ? shel ving2_a[29:24], default 0001 1111 ......... 22 6.3.16 register 0x1b shelving2_a[23:16], default 1111 0111 ............ 22 6.3.17 register 0x1c ? shelvin g2_a[15:8], default 1111 1101 ........... 22 6.3.18 register 0x1d ? shelving2_a[7:0], default 1111 1111 .............. 22 6.3.19 register 0x1e ? shelving2_b[ 29:24], default 0001 1111 ......... 22 6.3.20 register 0x1f ? shelving2_b[23:16], default 1111 0111 .......... 22
everest semiconductor ES8155 v ersion 1.0 3/29/2011 3 6.3.21 register 0x20 ? shelving2_b[15 :8], default 1111 1101 ............ 22 6.3.22 register 0x21 ? shelving2_b[7:0], default 1111 1111 ............. 22 6.3.23 register 0x22 ? shelving3_a[29:24 ], default 0001 1111 ......... 23 6.3.24 register 0x23 ? shelving3_a[23:16], default 1111 0111 ......... 23 6.3.25 register 0x24 ? shelving3_a[15:8] , default 1111 1101 ........... 23 6.3.26 register 0x25 ? shelving3_a[7:0], default 1111 1111 ............. 23 6.3.27 register 0x26 ? shelving3_b[29:24], default 0001 1111 ......... 23 6.3.28 register 0x27 ? shelving3_b[23:16], default 1111 0111 ......... 23 6.3.29 register 0x28 ? shelving3_b[15:8], d efault 1111 1101 ........... 23 6.3.30 register 0x29 ? shelving3_b[7:0], default 1111 1111 ............. 23 6.4 digital audio interface setting ........................................................... 23 6.4.1 register 0x2a ? digital audio interface 1, default 0000 0000 ..... 23 6.4.2 register 0x2b ? digital audio interface 2, default 0000 000 1 ..... 24 6.4.3 register 0x2c ? digital audio sample rate, default 0000 0110 . 24 6.4.4 register 0x2d ? sclk divider, default 0000 0000 ..................... 25 6.5 reference setting .............................................................................. 25 6.5.1 register 0x2e ? control port registers reset, default 0000 0000 25 6.5.2 register 0x2f ? power down control, default 0000 1100 .......... 26 6.5.3 register 0x30 ? reference 1, default 0000 0000 ....................... 26 6.5.4 register 0x31 ? reference 2, default 0010 1000 ....................... 26 6.5.5 register 0x32 ? reference 3, default 0011 0100 ........................ 26 6.5.6 register 0x33 ? reference 4, default 1111 1100 ........................ 27 6.5.7 register 0x34 ? reference 5, default 0101 0101 ....................... 27 6.5 .8 register 0x35 ? reference 6, default 0000 0101 ....................... 27 6.6 pll setting ........................................................................................ 27 6.6.1 register 0x36 ? pll control 1, default 0000 1000 ..................... 27 6.6.2 register 0x37 ? pll control 2, default 0000 0000 ..................... 27 6.6.3 register 0x38 ? pll control 3, default 0000 0000 ..................... 28 6.6.4 register 0x39 ? pll_k[21:16], default 0000 0000 ..................... 28 6.6.5 register 0x3a ? pll_k[15:8], default 0000 0000 ....................... 28 6.6.6 register 0x3b ? pll_k[7:0], default 0000 0000 ......................... 28 7 digital audio interface .............................................................................. 28 8 ele ctrical characterist ics ........................................................ 29 8.1 absolute maximum ratings ............................................................... 29 8.2 recommended operating conditions ............................................... 30 8.3 dac analog and filter characteristics and specifications ................ 30 8.4 power consumption characteristics ................................................. 31 8.5 serial audio port switching specifications ........................................ 31 8.6 serial control port switching specifications ...................................... 31 9 package info rmation ...................................................................... 33 10 corpoaration information ....................................................... 3 3
everest semiconductor ES8155 v ersion 1.0 3/29/2011 4 1 block diagram lin rin se dac dacl mono mono+ mono - se dac dacr mixl + lin mono dacl dacr mixr + rin mono dacl dacr mixm + lin rin dacl dacr mixl mixr lout1 rout1 mixl +/ - mixr lout2 rout2 mixm mout out3 vref rout1 mout dvdd pvdd dgnd avdd agnd hpvdd hpgnd gnd vref vmid mux mclk pll uc interface ce cclk cdata serial audio data dlrck dsdin sclk d2s
everest semiconductor ES8155 v ersion 1.0 3/29/2011 5 2 28- pin qfn and pin descriptions pin name i/o description 1 mclk i master clock 2 dvdd supply digital core supply 3 p vdd supply digital io supply 4 dgnd supply digital ground (return path for both dvdd and p vdd) 5 s clk i/o audio data bit clock 6 dsdin i dac audio data 7 dlrck i/o dac audio data left and right clock 8 gnd supply ground or no connect 9 mout o mono output 1 0 out3 o analog output 3 (can be used as headphone pseudo ground) 1 1 rout1 o right output 1 (line or speaker/ headphone) 1 2 lout 1 o left output 1 ( l ine or speaker/ headphone) 1 3 hpgnd supply ground for analog output drivers (lout1/2, rout1/2) 1 4 rout2 o right output 2 ( l ine or speaker/ headphone) 1 5 lout2 o left output 2 ( l ine or speaker/ headphone) 1 6 hpvdd supply supply fo r analog output drivers (lout1/2, rout1/2) 1 7 avdd supply analog supply 1 8 agnd supply analog ground 19 vref o d ecoupling capacitor 20 vmid o d ecoupling capacitor 2 1 mono - i mono input (negative side) 2 2 mono+ i mono input (positive side) 2 3 rin i r ight channel input 2 4 lin i left channel input gnd mout out3 rout1 lout1 hpgnd rout2 8 9 10 11 12 13 14 mono - vmid vref agnd avdd hpvdd lout2 21 20 19 18 17 16 15 cclk cdata ce nu lin rin mono+ 28 27 26 25 24 23 22 mclk dvdd pvdd dgnd sclk dsdin dlrck 1 2 3 4 5 6 7
everest semiconductor ES8155 v ersion 1.0 3/29/2011 6 25 nu not used by chip (arbitrary connection) 26 c e i control select or d evice address selection 27 cdata i/o control data input or output 28 cclk i control clock input 3 typical application circuit 4 c lock modes and sampl ing frequencies according to the input serial audio data sampling frequency, the device can work in two speed modes: single speed or double speed. the ranges of the sampling frequency in these two modes are listed in table 1. the device can work either in master clock mode or slave clock mode. in slave mode, lrck and sclk are supplied externally. lrck and sclk must be synchronously derived from the system clock with specific rates. the device can auto detect mclk/lrck ratio according to table 1. the device only support s the mclk/lrck ratios listed in table 1. the lrck/sclk ratio is normally 64. table 1 slave mode sampling frequencies and mclk /lrck ratio speed mode sampling frequency mclk /lrck ratio single speed 8khz ? 50khz 256, 384, 5 12, 768, 1024 double speed 50khz ? 100khz 128, 192, 256, 384, 512 in master mode, lrck and sclk are derived internally from mclk. the available mclk/lrck ratios and sclk/lrck ratios are listed in table 2.
everest semiconductor ES8155 v ersion 1.0 3/29/2011 7 table 2 master mode sampling frequencies and mc lk /lrck ratio mclk clkdiv2=0 mclk clkdiv2=1 dac sample rate (dlrck) dacfsratio [4:0] sclk ratio normal mode 12.288 mhz 24.576mhz 8 khz (mclk/1536) 01010 mclk/6 48 khz (mclk/256) 00010 mclk/4 12 khz (mclk/1024) 00111 mclk/4 16 khz (mclk /768) 00110 mclk/6 24 khz (mclk/512) 00100 mclk/4 32 khz (mclk/384) 00011 mclk/6 8 khz (mclk/1536) 01010 mclk/4 48 khz (mclk/256) 00010 mclk/4 96 khz (mclk/128) 00000 mclk/2 11.2896 mhz 22.5792mhz 8.0182 khz (mclk/1408) 01001 mc lk/4 44.1 khz (mclk/256) 00010 mclk/4 11.025 khz (mclk/1024) 00111 mclk/4 22.05 khz (mclk/512) 00100 mclk/4 8.0182 khz (mclk/1408) 01001 mclk/4 44.1 khz (mclk/256) 00010 mclk/4 88.2 khz (mclk/128) 00000 mclk/2 18.432 mhz 36.8 64mhz 8 khz (mclk/2304) 01100 mclk/6 48 khz (mclk/384) 00011 mclk/6 12 khz (mclk/1536) 01010 mclk/6 16 khz (mclk/1152) 01000 mclk/6 24 khz (mclk/768) 00110 mclk/6 32 khz (mclk/576) 00101 mclk/6 8 khz (mclk/2304) 01100 mclk/6 48 khz (mclk/384) 00011 mclk/6 96 khz (mclk/192) 00001 mclk/3 16.9344 mhz 33.8688mhz 8.0182 khz (mclk/2112) 01011 mclk/6 44.1 khz (mclk/384) 00011 mclk/6 11.025 khz (mclk/1536) 01010 mclk/6 22.05 khz (mclk/768) 00110 mclk/6 8.0182 khz (mclk/2112) 01011 mclk/6 44.1 khz (mclk/384) 00011 mclk/6 88.2 khz (mclk/192) 00001 mclk/3 usb mode 12 mhz 24mhz 8 khz (mclk/1500) 11011 mclk 48 khz (mclk/250) 10010 mclk 8.0214 khz (mclk/1496) 11010 mclk 44.118 kh z (mclk/272) 10011 mclk 11.0259 khz (mclk/1088) 11001 mclk
everest semiconductor ES8155 v ersion 1.0 3/29/2011 8 12 khz (mclk/1000) 11000 mclk 16 khz (mclk/750) 10111 mclk 22.0588 khz (mclk/544) 10110 mclk 24 khz (mclk/500) 10101 mclk 32 khz (mclk/375) 10100* mclk 8.0214 khz (mclk/1496) 11010 mclk 44.118 khz (mclk/272) 10011 mclk 8 khz (mclk/1500) 11011 mclk 48 khz (mclk/250) 10010 mclk 88.235 khz (mclk/136) 10001 mclk 96 khz (mclk/125) 10000 mclk ES8155 has a high performance fractional - n pll. pll can be used for non- standard mclk to generate standard internal master clock, for example 12.288 mhz for 48 khz sampling frequency or 11.2896 mhz for 44.1 khz sampling frequency. by default, pll is in power down and reset, and the internal master clock use s mclk clock from pin directly. the following table shows the pll setting (mclkdiv2, pll_n, pll_k and pllout_div2) for typical non - standard mclk to generate standard internal master clock. mclk (mhz) internal master clock (mhz) f2 (mhz) mclkdiv2 pllout_di v2 r n f (*0.6574) pll_n pll_k 11.91 11.2896 90.3168 0 1 7.5833 7 0.3834 7 188 9 f 9 11.91 12.288 98.304 0 1 8.2539 8 0.1669 8 aae98 12 11.2896 90.3168 0 1 7.5264 7 0.3460 7 16256 d 12 12.288 98.304 0 1 8.192 8 0.1262 8 813e0 13 11.2896 90.3168 0 1 6.9474 6 0.6228 6 27d c2b 13 12.288 98.304 0 1 7.5618 7 0.3693 7 17a 33 0 14.4 11.2896 90.3168 0 1 6.272 6 0.1788 6 b717d 14.4 12.288 98.304 0 1 6.8267 6 0.5434 6 22c7 5a 19.2 11.2896 90.3168 1 1 9.408 9 0.2682 9 112a3c 19.2 12.288 98.304 1 1 10.24 10 0.1578 a a18d8 19.68 11.2896 90.3168 1 1 9.1785 9 0.1173 9 782 df 19.68 12.288 98.304 1 1 9.9902 9 0.6509 9 29a 91c 19.8 11.2896 90.3168 1 1 9.1229 9 0.0808 9 52b c1 19.8 12.288 98.304 1 1 9.9297 9 0.6111 9 271d0 2 24 11.2896 90.3168 1 1 7.5264 7 0.3460 7 16256 d 24 12.288 98.304 1 1 8.192 8 0.1262 8 813e0 26 11.2896 90.3168 1 1 6.9474 6 0.6228 6 27d c2b 26 12.288 98.304 1 1 7.5618 7 0.3693 7 17a 33 0 27 11.2896 90.3168 1 1 6.6901 6 0.4536 6 1d08 dd
everest semiconductor ES8155 v ersion 1.0 3/29/2011 9 27 12.288 98.304 1 1 7.2818 7 0.1852 7 bd acc 5 micro - controller co nfiguration interfac e the device supports standard spi and 2 - wire micro - controller configuration interface. external micro - controller can completely configure the device through writing to internal configuration registers. please see section 8 for the deta ils of configuration register definition. the identical device pins are used to configure either spi or 2 - wire interface. in spi mode, pin ce, cclk and cdata function as spi_csn, spi_clk and spi_din. in 2 - wire mode, pin ce, cclk and cdata function as ad0 , scl and sda. to select spi mode, apply high to low transition signal to ce pin . otherwise the device will operate in 2 - wire interface mode. 5.1 spi ES8155 has a spi (serial peripheral interface) compliant synchronous serial slave controller inside the chip . i t provides the ability to allow the external master spi controller to access the internal registers, and thus control the operations of chip . all lines on the spi bus are unidirectional: the spi_clk is generated by the master controller and is primarily u sed to synchronize data transfer, the spi_din line carries data from the master to the slave ; spi_csn is generated by the master to select ES8155. the timing diagram of this interface is given in figure 1. the high to low transition at spi_csn pin indicat es the spi interface selected. each writes procedure contains 3 words, i.e. chip address plus r/w bit, internal register address and internal register data. every word length is fixed at 8 bits. the input spi_din data are sampled at the rising edge of spi_ clk clock. the msb bit in each word is transferred firstly. the transfer rate can be up to 10m bps. chip address 7 bits - 0010000 0 spi_din spi_clk spi_csn 1 r/ wb 5 6 7 8 9 14 15 16 17 22 23 ram 8 bits register data 8 bits figure 1 spi configuration interface timing diagram ram = register address mapping
everest semiconductor ES8155 v ersion 1.0 3/29/2011 10 5.2 2 - wire 2 - wire interface is a bi - directional serial bus that uses a serial data line (sda) and a serial clock line (scl) for data transfer. the timing diagram for data transfer of this interface is given in figure 2. data are transmitted synchronously to scl clock on the sda line on a byte - by - byte basis. each bit in a byte is sampled during scl high with msb bit being transmitt ed firstly. each transferred byte is followed by an acknowledge bit from receiver to pull the sda low. the transfer rate of this interface can be up to 100k bps. a master controller initiates the transmission by sending a ?start? signal, which is defi ned as a high - to - low transition at sda while scl is high. the first byte transferred is the slave address. it is a seven - bit chip address followed by a rw bit. the chip address must be 001000x,where x equals ad0 (pin ce) . the rw bit indicates the slave dat a transfer direction. once an acknowledge bit is received, the data transfer starts to proceed on a byte - by - byte basis in the direction specified by the rw bit. the master can terminate the communication by generating a ?stop? signal, which is defined as a low - to - high transition at sda while scl is high. in 2 - wire interface mode, the registers can be written and read. the formats of ?write? and ?read? instructions are shown in table 3 and table 4. please note that, to read data from a register, you must se t r/w bit to 0 to access the register address and then set r/w to 1 to read data from the register. there are no acknowledge bit after data to be written or read, this is the only difference from the i 2 c protocol. table 3 write data to register in 2 - wire interface mode chip address r/w register address data to be written 001000 ad0 0 ack ram ack data table 4 read data from register in 2 - wire interface mode chip address r/w register address 001000 ad0 0 ack ram chip address r/w data to be read 001000 ad0 1 ack data figure 2 complete data transfer for 2 - wire interface
everest semiconductor ES8155 v ersion 1.0 3/29/2011 11 6 configuration regist er definition spi and 2 - wire configuration interface share the same registers because there is only one interface active at any time. there are total of 61 user programmable 8 - bit regi sters in this device. these registers control the operations of dac. external master controller can access these registers by using the slave address specified in ram (register address map) register as shown in the table 5.
everest semiconductor ES8155 v ersion 1.0 3/29/2011 12 table 5 bit content of registe r address map adr name bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 default 0 output setting lout1 volume lp_out1 pdn_lout1 lout1vol 40 1 rout1 volume pdn_rout1 rout1vol 40 2 lout2 volume lp_out2 pdn_lout2 lout2vol 40 3 rout2 volume pdn_rout2 rout 2vol 40 4 mout volume lp_mout pdn_mout moutvol 40 5 out control 1 lp_out3 pdn_out3 out3sw lp_rout2inv rout2inv 40 6 out control 2 l2r2both l1r1both 00 7 mixer setting left mixer li2lomu li2lovol mi2lomu mi2lovol ff 8 right mixer mi2romu ri2rovol ri2romu mi2rovol ff 9 mono mixer li2momu li2movol ri2momu ri2movol ff a dac to mixer pdn_monodiff dmen ld2momu rd2momu ld2lomu rd2lomu ld2romu rd2romu bf b mixer lp mode lp_monodiff lp_mmix lp_lmix lp_rmix 00 c dac setting left dac volume dacl vol c0 d right dac volume dacr vol c0 e dac control lp_dacl pdn_dacl lp_dacr pdn_dacr dacl mu dacr mu 55 f dac control automute clickfree vppscale daclrboth dacsoftramp dacramprate c4 10 dac control dacinv l dacinv r dactoen dacdat 08 11 dac control daczero l daczero r dacmono dacse 00 12 shelving1_a shv1_a[29:24] 1f 13 shv1_a[23:16] f7 14 shv1_a[15:8] fd 15 shv1_a[7:0] ff
everest semiconductor ES8155 v ersion 1.0 3/29/2011 13 16 shelving1_b shv1_b[29:24] 1f 17 shv1_b[23:16] f7 18 shv1_b[15:8] fd 19 shv1_ b[7:0] ff 1a shelving2_a shv2_a[29:24] 1f 1b shv2_a[23:16] f7 1c shv2_a[15:8] fd 1d shv2_a[7:0] ff 1e shelving2_b shv2_b[29:24] 1f 1f shv2_b[23:16] f7 20 shv2_b[15:8] fd 21 shv2_b[7:0] ff 22 shelving3_a shv3_a[29:24] 1f 23 shv3_a[23:16] f7 24 shv3_a[15:8] fd 25 shv3_a[7:0] ff 26 shelving3_b shv3_b[29:24] 1f 27 shv3_b[23:16] f7 28 shv3_b[15:8] fd 29 shv3_b[7:0] ff 2a digital audio i/f setting digital interface dacformat daclrswp daclrp dacwl 00 2b digital interface mclkdiv2 sclkinv fsmode dacmsc 01 2c sample rate dacsr 06 2d sclk divider sclkdiv 00 2e reference reset rst_cp 00
everest semiconductor ES8155 v ersion 1.0 3/29/2011 14 2f setting power down pdn_ana pdn_dig pdn_fsm pdn_dll 0c 30 reference seqen 00 31 reference enrefr vroi vmidsel vmidlow 28 32 reference pdn_vrefgen pdn_ibiasgen lp_dacvrp lp_vrefbuf pdn_vrefbuf vrefr_lo 34 33 reference ibiassw vsel fc 34 reference mout_ref2 mout_ref1 out3_ref2 out3_ref1 out2_ref2 out2_ ref1 out1_ref2 out1_ref1 55 35 reference mono_ref2 mono_ref1 mix_ref2 mix_ref1 05 36 pll setting pll control pdn cp2 cp1 cp0 supsel1 supsel0 kvco1 kvco0 08 37 pll control lp mclksel pllout_div2 pll_rb pll_en 00 38 pll control dith_ma g pll_n 00 39 pll control pll_k[21:16] 00 3a pll control pll_k[15:8] 00 3b pll control pll_k[7:0] 00
everest semiconductor ES8155 v ersion 1.0 3/29/2011 15 6.1 output setting 6.1.1 register 0 x00 ? lout1 v olume , default 0 1 00 0000 bit name bit description lp_lout1 7 0 ? n ormal (default) 1 ? l ow p ower s et ting for lout1 pdn_lout1 6 0 ? n ot p ower d own 1 ? p ower d own lout1 (default) lout1vol 5:0 lout1 v olume c ontrol 000000 ? - 45 db (default) 000001 ? - 43.5 db 000010 ? - 42 db ? 011110 ? 0 db 011111 ? 1 .5 db ? 100000 ? 3 db 6.1.2 register 0 x01 ? rout1 volume , def ault 0 1 0 0 0000 bit name bit description lp_rout1 7 0 ? n ormal (default) 1 ? l ow p ower s etting for rout1 pdn_rout1 6 0 ? n ot p ower d own 1 ? p ower d own rout1 (default) rout1vol 5:0 rout1 v olume c ontrol 000000 ? - 45 db (default) 000001 ? - 43.5 db 000010 ? - 42 db ? 011110 ? 0 db 011111 ? 1 .5 db ? 100000 ? 3 db 6.1.3 register 0 x02 ? lout2 volume , default 0 100 0000 bit name bit description lp_lout2 7 0 ? n ormal (default) 1 ? l ow p ower s etting for lout2 pdn_lout2 6 0 ? n ot p ower d own 1 ? p ower d own lout2 (defau lt) lout2vol 5:0 lout2 v olume c ontrol 000000 ? - 45 db (default) 000001 ? - 43.5 db
everest semiconductor ES8155 v ersion 1.0 3/29/2011 16 000010 ? - 42 db ? 011110 ? 0 db 011111 ? 1 .5 db ? 100000 ? 3 db 6.1.4 register 0 x03 ? rout2 volume , default 0100 0000 bit name bit description lp_rout2 7 0 ? n ormal (default) 1 ? l ow p ower s etting for rout2 pdn_rout2 6 0 ? n ot p ower d own 1 ? p ower d own rout2 (default) rout2vol 5:0 rout2 v olume c ontrol 000000 ? - 45 db (default) 000001 ? - 43.5 db 000010 ? - 42 db ? 011110 ? 0 db 011111 ? 1 .5 db ? 100000 ? 3 db 6.1.5 register 0 x04 ? mout v olume , default 0 100 0000 bit name bit description lp_mout 7 0 ? n ormal (default) 1 ? l ow p ower s etting for mono out pdn_mout 6 0 ? n ot p ower d own 1 ? p ower d own m ono o ut (default) moutvol 5:0 mono out v olume c ontrol 000000 ? - 45 db (default) 00 0001 ? - 43.5 db 000010 ? - 42 db ? 011110 ? 0 db 011111 ? 1 .5 db ? 100000 ? 3 db 6.1.6 register 0 x05 ? out c ontrol 1 , default 0 1 00 0000 bit name bit description lp_out3 7 0 ? n ormal (default) 1 ? l ow p ower s etting for out3 pdn_out3 6 0 ? n ot p ower d own
everest semiconductor ES8155 v ersion 1.0 3/29/2011 17 1 ? p ower d own out3 (default) out3sw 5:4 out3 select 00 ? vref (default) 01 ? rout1 signal 10 ? monoout 11 ? not used lp_rout2inv 3 0 ? n ormal (default) 1 ? l ow p ower s etting for rout2 inv rout2inv 2 0 ? no inversion (default) 1 ? rout2 signal inverted 6.1.7 reg ister 0 x06 ? out control 2 , default 0000 0000 bit name bit description l2r2both 1 1 ? s imultaneous l oad of lout2vol and rout2vol 0 ? d isable s imultaneous load (default) l1r1both 0 1 ? s imultaneous l oad of lout1vol and rout1vol 0 ? d isable s imultaneous load (default) 6.2 mixer setting 6.2.1 register 0 x07 ? left mixer , default 1 111 11 11 bit name bit description li2lomu 7 1 ? m ute left l ine in to l eft o ut m ixer (default) 0 ? not m ute li2lovol 6:4 left line i n to l eft o ut m ixer v olume c ontrol 000 ? 6 db 001 ? 3 d b 010 ? 0 db 011 ? - 3 db 100 ? - 6 db 101 ? - 9 db 110 ? - 12 db 111 ? - 15 db (default) mi2lomu 3 1 ? m ute m icrophone i n to l eft o ut m ixer (default) 0 ? not m ute mi2lovol 2:0 microphone i n to l eft o ut m ixer v olume c ontrol 000 ? 6 db 001 ? 3 db 010 ? 0 db 01 1 ? - 3 db 100 ? - 6 db 101 ? - 9 db 110 ? - 12 db 111 ? - 15 db (default)
everest semiconductor ES8155 v ersion 1.0 3/29/2011 18 6.2.2 register 0 x08 ? right mixer , default 1 111 1111 bit name bit description mi2romu 7 1 ? m ute m icrophone i n to r ight o ut m ixer (default) 0 ? not m ute ri2rovol 6:4 right l ine i n to r ight s o ut m ixer v olume c ontrol 000 ? 6 db 001 ? 3 db 010 ? 0 db 011 ? - 3 db 100 ? - 6 db 101 ? - 9 db 110 ? - 12 db 111 ? - 15 db (default) ri2romu 3 1 ? m ute r ight l ine i n to r ight o ut m ixer (default) 0 ? not m ute mi2rovol 2:0 microphone i n to r ight o ut m ixer v olume c ontrol 000 ? 6 db 001 ? 3 db 010 ? 0 db 011 ? - 3 db 100 ? - 6 db 101 ? - 9 db 110 ? - 12 db 111 ? - 15 db (default) 6.2.3 register 0 x09 ? mono mixer , default 1111 1111 bit name bit description li2momu 7 1 ? m ute l eft l ine i n to m ono o ut m ixer (default) 0 ? not m ute li2movol 6:4 left l ine i n to m ono o ut m ixer v olume c ontrol 000 ? 6 db 001 ? 3 db 010 ? 0 db 011 ? - 3 db 100 ? - 6 db 101 ? - 9 db 110 ? - 12 db 111 ? - 15 db (default) ri2momu 3 1 ? m ute r ight l ine i n to m ono o ut m ixer (default) 0 ? not m ute ri2m ovol 2:0 right l ine i n to m ono o ut m ixer v olume c ontrol 000 ? 6 db 001 ? 3 db
everest semiconductor ES8155 v ersion 1.0 3/29/2011 19 010 ? 0 db 011 ? - 3 db 100 ? - 6 db 101 ? - 9 db 110 ? - 12 db 111 ? - 15 db (default) 6.2.4 register 0 x0a ? dac to mixer , default 1011 1111 bit name bit description pdn_monodiff 7 1 ? p ower d own m ono diff erential input stage (default) 0 ? n ot p ower d own dmen 6 1 ? mono d ifferential l ine in e nable 0 ? s ingle - ended l ine i n from mono+ (default) ld2momu 5 1 ? m ute left dac to m ono o ut m ixer (default) 0 ? not mute rd2momu 4 1 ? m ute r igh t dac to m ono o ut m ixer (default) 0 ? not m ute ld2lomu 3 1 ? m ute l eft dac to l eft o ut m ixer (default) 0 ? not m ute rd2lomu 2 1 ? m ute r ight dac to l eft o ut m ixer (default) 0 ? not m ute ld2romu 1 1 ? m ute l eft dac to r ight o ut m ixer (default) 0 ? not m u te rd2romu 0 1 ? m ute r ight dac to r ight o ut m ixer (default) 0 ? not m ute 6.2.5 register 0 x0b ? mixer lp m ode , default 0000 0000 bit name bit description lp_monodiff 3 0 ? n ormal (default) 1 ? l ow p ower s etting for m ono diff erential input stage lp_mmix 2 0 ? n ormal (default) 1 ? l ow p ower s etting for m ono m ixer lp_lmix 1 0 ? n ormal (default) 1 ? l ow p ower s etting for l eft m ixer lp_rmix 0 0 ? n ormal (default) 1 ? l ow p ower s etting for r ight m ixer 6.3 dac setting 6.3.1 register 0 x0c ? left dac v olume , default 11 00 0 000 bit name bit description dac l vol 7:0 left dac v olume c ontrol 00000000 ? 0 db ? 0.5 db/step
everest semiconductor ES8155 v ersion 1.0 3/29/2011 20 11000000 ? - 127 db (default) 6.3.2 register 0 x0d ? right dac v olume , default 11 00 0000 bit name bit description dac r vol 7:0 right dac v olume c ontrol 00000000 ? 0 db ? 0.5 db/step 11000000 ? - 127 db (default) 6.3.3 register 0 x0e ? dac control 1 , default 01 0 1 0101 bit name bit description lp_dacl 7 0 ? n ormal (default) 1 ? l ow p ower s etting for l eft dac pdn_dacl 6 0 ? n ot p ower d own 1 ? p ower d own l eft dac (default) lp_dacr 5 0 ? n ormal (default) 1 ? l ow p ower s etting for r ight dac pdn_dacr 4 0 ? n ot p ower d own 1 ? p ower d own r ight dac (default) dac l mu 2 1 ? left dac m ute (default) 0 ? left dac not m ute dac r mu 0 1 ? right dac m ute (default) 0 ? right dac not m ute 6.3.4 register 0 x0f ? dac contro l 2 , default 1100 01 00 bit name bit description automute 7 auto mute function: long period of zero inputs (8k audio samples) will mute the analog output. any single non - zero input will un - mute. it is done per channel based. 0 ? disable 1 ? enable (default) clickfree 6 0 ? disable digital click free power up and down 1 ? enable digital click free power up and down (default) vppscale 5:4 reserved daclrboth 3 1 ? e nable s imultaneous l oad of daclvol and dacrvol set by dac l vol 0 ? d isable s imultaneous l oad (default) dacsoftramp 2 1 ? enable da c soft ramp at mute and volume change (default) 0 ? disable dacramprate 1:0 these bits define dac gain control ramp rate 00 ? 0.5 db per 4 lrcks (default) 01 ? 0.5 db per 8 lrcks 10 ? 0. 5 db per 16 lrcks 11 ? 0.5 db per 32 lrcks
everest semiconductor ES8155 v ersion 1.0 3/29/2011 21 6.3.5 register 0 x10 dac control 3 , default 0000 1 000 bit name bit description dacinv l 5 0 ? dac left channel output no phase inversion (default) 1 ? dac left output 180 degree phase inversion dacinv r 4 0 ? dac righ t channel output no phase inversion (default) 1 ? dac right channel output 180 degree phase inversion dactoen 3 reserved dacdat 2 0 ? disable dac data 6 db attenuate 1 ? - 6 db enable 6.3.6 register 0 x11 ? dac control 4 , default 0000 0 000 bit name bit descrip tion daczero l 5 0 ? normal (default) 1 ? set left c hannel dac output all zero daczero r 4 0 ? normal (default) 1 ? set right c hannel dac output all zero dacmono 3 0 ? stereo (default), and en able se function 1 ? mono ((l+r)/2) into dacl and dacr , and dis able se function dacse 2:0 stereo e nhancement gain 000 ? 0 (default) 001 ? 1/8 ? 111 ? 7/8 6.3.7 register 0 x12? shelving1_a[29:24] , default 000 1 1111 bit name bit description shev1_a[29:24] 5:0 30- bit a coefficient for shelving filter; d efault value is {5'h 0f, 5'h1f, 5'h0f, 5'h1f, 5'h0f, 5'h1f} 6.3.8 register 0 x13? shelving1_a[23:16] , default 1111 0 111 bit name bit description shev1_a[23:16] 7 : 0 30- bit a coefficient for shelving filter; d efault value is {5'h0f, 5'h1f, 5'h0f, 5'h1f, 5'h0f, 5'h1f} 6.3.9 register 0 x14 ? shelving1_a[15:8] , default 1111 1101 bit name bit description shev1_a [15:8] 7 : 0 30- bit a coefficient for shelving filter; d efault value is {5'h0f, 5'h1f, 5'h0f, 5'h1f, 5'h0f, 5'h1f} 6.3.10 register 0 x15? shelving1_a[7:0] , default 1111 1111 bit name bit d escription shev1_a [7:0] 7 : 0 30- bit a coefficient for shelving filter; d efault value is {5'h0f, 5'h1f, 5'h0f, 5'h1f, 5'h0f, 5'h1f} 6.3.11 register 0 x16? shelving1_b[29:24] , default 0001 1111 bit name bit description shev1_b [29:24] 5 : 0 30- bit a coefficient for shelving filter; d efault value is {5'h0f, 5'h1f, 5'h0f, 5'h1f, 5'h0f, 5'h1f}
everest semiconductor ES8155 v ersion 1.0 3/29/2011 22 6.3.12 register 0 x17? shelving1_b[23:16] , default 1111 0111 bit name bit description shev1_b [23:16] 7 : 0 30- bit a coefficient for shelving filter; d efault value is {5'h0f, 5'h1f, 5'h 0f, 5'h1f, 5'h0f, 5'h1f} 6.3.13 register 0 x18? shelving1_b[15:8] , default 1111 1101 bit name bit description shev1_b [15:8] 7 : 0 30- bit a coefficient for shelving filter; d efault value is {5'h0f, 5'h1f, 5'h0f, 5'h1f, 5'h0f, 5'h1f} 6.3.14 register 0 x19? shelving1_b[7 :0] , default 1111 1111 bit name bit description shev1_b [7:0] 7 : 0 30- bit a coefficient for shelving filter; d efault value is {5'h0f, 5'h1f, 5'h0f, 5'h1f, 5'h0f, 5'h1f} 6.3.15 register 0 x1a ? shelving2_a[29:24] , default 000 1 1111 bit name bit description shev2 _a[29:24] 5:0 30- bit a coefficient for shelving filter; d efault value is {5'h0f, 5'h1f, 5'h0f, 5'h1f, 5'h0f, 5'h1f} 6.3.16 register 0 x1b shelving2_a[23:16] , default 1111 0 111 bit name bit description shev2_a[23:16] 7 : 0 30- bit a coefficient for shelving filter ; d efault value is {5'h0f, 5'h1f, 5'h0f, 5'h1f, 5'h0f, 5'h1f} 6.3.17 register 0 x1c ? shelving2_a[15:8] , default 1111 1101 bit name bit description shev2_a [15:8] 7 : 0 30- bit a coefficient for shelving filter; d efault value is {5'h0f, 5'h1f, 5'h0f, 5'h1f, 5'h0f, 5'h1f} 6.3.18 register 0 x1d ? shelving2_a[7:0] , default 1111 1111 bit name bit description shev2_a [7:0] 7 : 0 30- bit a coefficient for shelving filter; d efault value is {5'h0f, 5'h1f, 5'h0f, 5'h1f, 5'h0f, 5'h1f} 6.3.19 register 0 x1e ? shelving2_b[29:24] , default 0001 1111 bit name bit description shev2_b [29:24] 5 : 0 30- bit a coefficient for shelving filter; d efault value is {5'h0f, 5'h1f, 5'h0f, 5'h1f, 5'h0f, 5'h1f} 6.3.20 register 0 x1f? shelving2_b[23:16] , default 1111 0111 bit name bit description shev2_b [23:16] 7 : 0 3 0 - bit a coefficient for shelving filter; d efault value is {5'h0f, 5'h1f, 5'h0f, 5'h1f, 5'h0f, 5'h1f} 6.3.21 register 0 x20? shelving2_b[15:8] , default 1111 1101 bit name bit description shev2_b [15:8] 7 : 0 30- bit a coefficient for shelving filter; d efault value is {5'h0f, 5'h1f, 5'h0f, 5'h1f, 5'h0f, 5'h1f} 6.3.22 register 0 x21 ? shelving2_b[7:0] , default 1111 1111 bit name bit description shev2_b [7:0] 7 : 0 30- bit a coefficient for shelving filter; d efault value is {5'h0f, 5'h1f, 5'h0f, 5'h1f, 5'h0f, 5'h1f}
everest semiconductor ES8155 v ersion 1.0 3/29/2011 23 6.3.23 register 0 x22 ? shelving3_a[29:24] , default 000 1 1111 bit name bit description shev3_a[29:24] 5:0 30- bit a coefficient for shelving filter; d efault value is {5'h0f, 5'h1f, 5'h0f, 5'h1f, 5'h0f, 5'h1f} 6.3.24 register 0 x23 ? shelving3_a[23:16] , default 1111 0 111 bit na me bit description shev3_a[23:16] 7 : 0 30- bit a coefficient for shelving filter; d efault value is {5'h0f, 5'h1f, 5'h0f, 5'h1f, 5'h0f, 5'h1f} 6.3.25 register 0 x24 ? shelving3_a[15:8] , default 1111 1101 bit name bit description shev3_a [15:8] 7 : 0 30- bit a coef ficient for shelving filter; d efault value is {5'h0f, 5'h1f, 5'h0f, 5'h1f, 5'h0f, 5'h1f} 6.3.26 register 0 x25 ? shelving3_a[7:0] , default 1111 1111 bit name bit description shev3_a [7:0] 7 : 0 30- bit a coefficient for shelving filter; d efault value is {5'h0f, 5' h1f, 5'h0f, 5'h1f, 5'h0f, 5'h1f} 6.3.27 register 0 x26 ? shelving3_b[29:24] , default 0001 1111 bit name bit description shev3_b [29:24] 5 : 0 30- bit a coefficient for shelving filter; d efault value is {5'h0f, 5'h1f, 5'h0f, 5'h1f, 5'h0f, 5'h1f} 6.3.28 register 0 x27 ? s helving3_b[23:16] , default 1111 0111 bit name bit description shev3_b [23:16] 7 : 0 30- bit a coefficient for shelving filter; d efault value is {5'h0f, 5'h1f, 5'h0f, 5'h1f, 5'h0f, 5'h1f} 6.3.29 register 0 x28 ? shelving3_b[15:8] , default 1111 1101 bit name bit de scription shev3_b [15:8] 7 : 0 30- bit a coefficient for shelving filter; d efault value is {5'h0f, 5'h1f, 5'h0f, 5'h1f, 5'h0f, 5'h1f} 6.3.30 register 0 x29 ? shelving3_b[7:0] , default 1111 1111 bit name bit description shev3_b [7:0] 7 : 0 30- bit a coefficient for sh elving filter; d efault value is {5'h0f, 5'h1f, 5'h0f, 5'h1f, 5'h0f, 5'h1f} 6.4 d igital audio interface setting 6.4.1 register 0 x2a ? digital audio interface 1 , default 0000 0000 bit name bit description dacformat 7:6 audio d ata f ormat 00 ? i2s format (default) 0 1 ? l eft j ustify 10 ? r ight j ustify, 11 ? dsp m ode daclrswp 5:4 00 ? left data = left dac, right data = right dac (default)
everest semiconductor ES8155 v ersion 1.0 3/29/2011 24 01 ? left data = left dac, right data = left dac 10 ? left data = right dac, right data = right dac 11 ? left dat a = right dac, rig ht data = left dac daclrp 3 i2s/left justified/right justified case: 0 ? l/r normal polarity (default) left / right = high level / low level (left justified, right justified) left / right = low level / high level (i2s) 1 ? l/r invert polarity left / right = low level / high level (left justified, right justified) left / right = high level / low level (i2s) dsp mode case: 0 ? mode a, msb is available on 2 nd s clk rising edge after lrc k rising edge 1 ? mode b, msb is available on 1 st s clk rising edge after lr c k rising edge dacwl 2:0 data w ord l ength 000 ? 24 - bit (default) 001 ? 20 - bit 010 ? 18 - bit 011 ? 16 - bit 100 ? 32 - bit 6.4.2 register 0 x2b ? d igital audio interface 2 , default 00 00 0001 bit name bit description mclkdiv2 4 0 ? chip clock is mclk (default) 1 ? chip clock is mclk divide by 2 sclkinv 2 0 ? normal (default) 1 ? sclk inverted fsmode 1 0 ? s ingle s peed m ode (default) 1 ? d ouble s peed m ode dacmsc 0 1 ? master mode s erial port (default) 0 ? slave mode s erial port 6.4.3 register 0 x2c ? d igital audio samp le rate , default 00 00 0 11 0 bit name bit description dacsr 4:0 dac s ample r ate, mclk frequency/lrck frequency
everest semiconductor ES8155 v ersion 1.0 3/29/2011 25 00000 ? 128 00001 ? 192 00010 ? 256 00011 ? 384 00100 ? 512 00101 ? 576 00110 ? 768 (default) 00111 ? 1024 01000 ? 1152 01001 ? 1408 01010 ? 1 536 01011 ? 2112 01100 ? 2304 10000 ? 125 10001 ? 136 10010 ? 250 10011 ? 272 10100 ? 375 10101 ? 500 10110 ? 544 10111 ? 750 11000 ? 1000 11001 ? 1088 11010 ? 1496 11011 ? 1500 other ? reserved 6.4.4 register 0 x2d ? sclk divider , default 00 00 0 000 bit name bi t description sclkdiv 4:0 sclk divider 0 ? divide depend on dacsr and clock frequency 1 ? divide by 1 2 ? divide by 2 3 ? divide by 3 4 ? divide by 4 5 ? divide by 6 6 ? divide by 8 7 ? divide by 9 8 ? divide by 11 9 ? divide by 12 10 ? divide by 16 11 ? divide by 18 12 ? divide by 22 13 ? divide by 24 14 ? divide by 33 15 ? divide by 36 16 ? divide by 44 17 ? divide by 48 18 ? divide by 66 19 ? divide by 72 other ? divide by 4 6.5 reference setting 6.5.1 register 0 x2e ? control port registers reset , default 00 00 0 000 bit name bit description rst_cp 7 0 ? n ot reset (default)
everest semiconductor ES8155 v ersion 1.0 3/29/2011 26 1 ? r eset all registers of c ontrol p ort 6.5.2 register 0 x2f ? power down control , default 00 00 1 1 00 bit name bit description pdn_ana 3 0 ? n ot p ower d own 1 ? p ower d own analog blocks (default) pdn_dig 2 0 ? n ot p ower d own 1 ? p ower d own d igital b locks (default) pdn_fsm 1 0 ? n ot p ower d own (default) 1 ? p ower d own fsm pdn_dll 0 0 ? n ot p ower d own (default) 1 ? p ower d own dll 6.5.3 register 0 x30 ? reference 1 , default 00 00 0 000 bit name bit descr iption seq_en 0 0 ? internal power up/down sequence disable (default) 1 ? internal power up/down sequence enable 6.5.4 register 0 x31 ? reference 2 , default 00 1 0 1 000 bit name bit description enrefr 5 0 ? disable reference 1 ? enable reference (default) vro i 4 0 ? 1.5k ? vref to analog output resistance (default) 1 ? 40k ? vref to analog output resistance vmidsel 3:2 00 ? vmid disabled (off mode) 01 ? 50k ? divider enabled (playback/record mode) 10 ? 500k ? divider enabled (standby mode, default) 11 ? 5 k ? divi der enabled (fast start - up mode) vmidlow 1:0 reserved 6.5.5 register 0 x32 ? reference 3 , default 00 11 0 1 00 bit name bit description pdn_vrefgen 5 0 ? n ot p ower d own 1 ? p ower d own vrefgen (default) pdn_ibiasgen 4 0 ? n ot p ower d own 1 ? p ower d own ibiasgen (default) lp_dacvrp 3 0 ? n ormal (default) 1 ? l ow p ower mode for dacvrp lp_vrefbuf 2 0 ? normal 1 ? low power for vrefbuf (def a ult) pdn_vrefbuf 1 0 ? n ot p ower d own (default) 1 ? p ower d own vrefbuf vrefr_lo 0 0 ? normal (def a ult)
everest semiconductor ES8155 v ersion 1.0 3/29/2011 27 1 ? low power for vr efr 6.5.6 register 0 x33 ? reference 4 , default 1111 11 00 bit name bit description ibiassw 7 reserved vsel 6:0 reserved 6.5.7 register 0 x34 ? reference 5 , default 0 1 0 1 0 1 0 1 bit name bit description mout_ref2 7 reserved mout_ref1 6 reserved out3_ref2 5 reserv ed out3_ref1 4 reserved out2_ref2 3 reserved out2_ref1 2 reserved out1_ref2 1 reserved out1_ref1 0 reserved 6.5.8 register 0 x35 ? reference 6 , default 0000 0 1 0 1 bit name bit description mono_ref2 3 reserved mono_ref1 2 reserved mix_ref2 1 reserved mi x_ref1 0 reserved 6.6 pll setting 6.6.1 register 0 x36 ? pll control 1 , default 0000 1 000 bit name bit description pdn 7 0 ? n ot p ower d own (default) 1 ? p ower d own pll analog cp2 6 reserved cp1 5 reserved cp0 4 reserved supsel1 3 reserved supsel0 2 reserved kvco1 1 reserved kvco0 0 reserved 6.6.2 register 0 x37 ? pll control 2 , default 0000 0000 bit name bit description lp 4 0 ? n ormal m ode (default) 1 ? l ow p ower m ode for pll analog
everest semiconductor ES8155 v ersion 1.0 3/29/2011 28 mclksel 3 select internal master clock 0 ? from mclk pin (default) 1 ? from pll ( to use pll, make sure pllen=1 , pll_rb=1, otherwise, the setting will close chip clock ) pllout_div2 2 0 ? divide disabled , pll out clock is vcoout/4 (default) 1 ? divide enabled , pll out clock is vcoout/8 pll_rb 1 0 ? pll held in reset (default) 1 ? pll running (if pllen=1) pll_en 0 0 ? pll disabled (default) 1 ? pll enabled 6.6.3 register 0 x38 ? pll control 3 , default 0000 0000 bit name bit description dith_mag 6:4 reserved pll_n 3:0 integer part of pll input/output frequency ratio; use value great er than 5 and less than 13 6.6.4 register 0 x39 ? pll_k[21:16] , default 0000 0000 bit name bit description pll_k[21:16] 5:0 fractional part of pll input/output frequency ratio (treat as one 22 - digital binary number) 6.6.5 register 0 x3a ? pll_k[15:8] , default 000 0 0000 bit name bit description pll_k[15:8] 7:0 fractional part of pll input/output frequency ratio (treat as one 22 - digital binary number) 6.6.6 register 0 x3b ? pll_k[7:0] , default 0000 0000 bit name bit description pll_k[7:0] 7:0 fractional part of pll input/output frequency ratio (treat as one 22 - digital binary number) 7 d igital audio interface the device provides four formats of serial audio data interface to the input of the dac through lrck, sclk and sd in pins. the four formats are i 2 s, left justifi ed, right justified and dsp/pcm mode. dac input dsdin is sampled by ES8155 on the rising edge of dsclk. the relationship of sdata ( sd in), sclk and lrck with the three formats is shown through figure 3 to figure 7. n-2 n-1 n 3 2 1 1 sclk msb lsb left channel n-2 n-1 n 3 2 1 1 sclk msb lsb right channel sdata sclk lrck figure 3 i 2 s serial audio data format up to 24 - bit
everest semiconductor ES8155 v ersion 1.0 3/29/2011 29 n-2 n-1 n 3 2 1 msb lsb left channel n-2 n-1 n 3 2 1 msb lsb right channel sdata sclk lrck figure 4 left justified serial audio data format up to 24 - bit n-2 n-1 n 3 2 1 msb lsb left channel n-2 n-1 n 3 2 1 msb lsb right channel sdata sclk lrck figure 5 right justified serial audio data format up to 24 - bit figure 6 dsp /pcm mode a figure 7 dsp /pcm mode b 8 electrical character istics 8.1 absolute maximum ratings continuous operation at or beyond these condition s may permanent ly damage
everest semiconductor ES8155 v ersion 1.0 3/29/2011 30 the device. parameter min max analog supply voltage level - 0.3v +5.0v digital supply voltage level - 0. 3v +5.0v input voltage range dgnd - 0.3v dvdd+0.3v operating temperature range - 40 c +85 c storage temperature - 65 c +150 c 8.2 recommended operating conditions parameter min typ max unit analog supply voltage level 1.7 3.3 3.6 v digital supply voltage lev el 1.5 1.8 3.6 v 8.3 dac analog and filter characteristics and specifications test condition s are as the following unless otherwise specify: avdd=+ 3 . 3 v, dvdd=+ 1 . 8 v, agnd=0v, dgnd=0v, ambient temperature=+25 c , fs=48 khz , 96 khz or 192 khz , mclk/lrck=256. para meter min typ max unit dac performance dynamic range (note 1) 83 96 98 db thd + n - 85 - 83 - 75 db channel separation (1khz) 80 85 90 db sign al to noise ratio 83 96 98 db interchannel gain m ismatch 0. 0 5 db filter frequency response ? single speed pas sband 0 0.45 35 fs stopband 0.54 65 fs passband ripple 0.05 db stopband attenuation 40 db filter frequency response ? double speed passband 0 0.4167 fs stopband 0.5833 fs passband ripple 0.005 db stopband attenuation 40 db de - empha sis error at 1 khz (single speed mode only) fs = 32khz fs = 44.1khz fs = 48khz 0.002 0.013 0.0009 db analog output full scale output level avdd/3.3 vrms note 1. the value is measured used a - weighted filter.
everest semiconductor ES8155 v ersion 1.0 3/29/2011 31 8.4 power consumption characteristics parame ter min typ max unit normal operation mode dvdd=1.8v, avdd=1.8v: play back dvdd=3.3v, avdd=3.3v: play back 7 31 m w power down mode dvdd=1.8v, avdd=1.8v dvdd=3.3v, avdd=3.3v tbd tbd m w 8.5 serial audio port switching specifications parameter symbol min max unit mclk frequency 51.2 mhz mclk duty cycle 40 60 % lrck frequency 200 khz lrck duty cycle 40 60 % sclk frequency 26 mhz sclk pulse width low t sclkl 15 ns sclk pulse width high t sclkh 15 ns sclk falling to lrck edge t slr ?10 10 n s sdin valid to sclk rising setup time t sdis 10 ns sclk rising to sdin hold time t sdih 10 ns 8.6 serial control port switching specifications parameter symbol min max unit spi mode spi_clk clock frequency 10 mhz spi_clk edge to spi_csn falling t spics 5 ns figure 8 serial audio port timing
everest semiconductor ES8155 v ersion 1.0 3/29/2011 32 spi_csn high time between transmissions t spish 500 ns spi_csn falling to spi_clk edge t spisc 10 ns spi_clk low time t spicl 45 ns spi_clk high time t spich 45 ns spi_din to spi_clk rising setup time t spids 10 ns spi_clk rising to data h old time t spidh 15 ns 2 - wire mode scl clock frequency f scl 100 khz bus free time between transmissions t twid 4.7 us start condition hold time t twsth 4.0 us clock low time t twcl 4.0 us clock high time t twch 4.0 us setup time for repeated st art condition t twsts 4.7 us sda hold time from scl falling t twdh 0.1 us sda setup time to scl rising t twds 100 ns rise time of scl t twr 25 us fall time scl t twf 25 ns spi_din spi_clk spi_csn t spics t spisc t spids t spidh t spich t spicl t spish s p sda scl t twsts t twsth t twch t twcl t twdh t twds t twf t twr s t twid figure 10 serial control port 2 - wire timing figure 9 serial control port spi timing
everest semiconductor ES8155 v ersion 1.0 3/29/2011 33 9 package infor mation 10 corpoaration information everest semiconductor co., ltd. ??? 328 ?????? 6a ? 215028 email: salesinfo@everest - semi.com

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