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1 ES8311 low power mono audio codec features system ? high performance and low power multi - bit delta - sigma audio adc and dac ? i 2 s/pcm master or slave serial data port ? 256/384fs, usb 12/24 mhz and other non standard audio system clocks ? i 2 c interface adc ? 24- bit, 8 to 96 khz sampling frequency ? 100 db signal to noise ratio, -93 db thd+n ? one pair of analog input with differential input option ? low noise pre - amplifier ? noise reduction filters ? auto level control (alc) and noise gate ? support analog and digital microphone dac ? 24- bit, 8 to 96 khz sampling frequency ? 1 10 db signal to noise ratio, -80 db thd+n ? one pair of analog output with headphone driver and differential output option ? dynamic range compression ? pop and click noise suppression low power ? 1.8v to 3.3 v operation ? 1 4 mw playback and record ? low standby current applications ? automotive ? phone ? toy ? 2 - way radio ? dash cam ? ip camera ? dvr, nvr ? surveillance o rdering i nformation ES8311 -40 c ~ +105 c qfn -20
everest semiconductor confidential ES8311 revision 5 .0 2 march 2019 latest datasheet: www.everest - semi.com or info@everest - semi.com 1. block diagram dvdd pvdd dgnd avdd agnd adcvref dacvref vmid mclk cdata cclk ce dsdin asdout sclk lrck mic1p mic1n i 2 c hp driver pga power supply i 2 s/pcm adc alc dac drc noise filter mono dac mono adc analog reference clock mgr outp outn
everest semiconductor confidential ES8311 revision 5 .0 3 march 2019 latest datasheet: www.everest - semi.com or info@everest - semi.com ES8311 agnd dsdin lrck asdout sclk/dmic_scl 10 9 8 7 6 vmid mic1n mic1p/dmic_sda cdata ce 16 17 18 19 20 2. pin out and descript ion pin name pin number input or output pin description cclk , cdata , ce 1, 19, 20 i, i /o , i i 2 c clock, data , address mclk 2 i master clock sclk /dmic_scl 6 i/o serial data bit clock /dmic bit clock lrck 8 i/o serial data left and right channel frame clock a sdout 7 o adc s erial data output d s din 9 i dac s erial data in put mic1p/dmic_sda mic1n 18 17 i mic input outp , outn 12, 13 o differential analog output p vdd 3 analog power supply for the digital input and output dvdd , d gnd 4, 5 analog digital power supply a vdd , a gnd 11, 10 analog analog power supply v mid 16 analog filtering capacitor connection adcvref , dacv ref 15, 14 analog filtering capacitor connection cclk mclk pvdd dvdd dgnd 1 2 3 4 5 adcvref dacvref outn outp avdd 15 14 13 12 11
everest semiconductor confidential ES8311 revision 5 .0 4 march 2019 latest datasheet: www.everest - semi.com or info@everest - semi.com 3. typical application circuit 1uf va 0.1uf 0.1uf 1uf vd vp agnd agnd mcu/ dsp agnd 1uf cc lk 1 m c lk 2 p vd d 3 dgnd 5 lrc k 8 asdout 7 dsdin 9 avdd 11 vmid 16 adcvref 15 agnd 10 mi c1n 17 dacvref 14 ce 20 cd ata 19 dvdd 4 out p 12 out n 13 mi c1p /dmi c_s da 18 sclk/dm ic _scl 6 pg nd 21 ES8311 agnd agnd agnd 0r gnd(sys) 1uf 1uf 1uf * * mi c1p mi c1n 1uf 1uf out n out p for the best performance,decoupling and filtering capacitors should be located as close to the device package as possible additional paralle capacitors(typically 0.1 f) can be used, larger value capacitors(typically 10 f) would also help * * * * * in the layout, chip is treated as a analog device
everest semiconductor confidential ES8311 revision 5 .0 5 march 2019 latest datasheet: www.everest - semi.com or info@everest - semi.com 4. clock modes and samp ling frequencies the device supports standard audio clo cks ( 64f, 128fs, 256fs, 384fs, 512fs, etc), usb clocks (12/24 mhz) , and some common non standard audio clocks ( 16 mhz, 25 mhz, 26 mhz, etc). according to the serial audio data sampling frequency (fs), the device can work in two speed modes: single speed mode or double speed mode. in single speed mode, f s normally ranges from 8 khz to 48 khz, and in double speed mode, fs normally range from 64 khz to 96 khz. the device can work either in master clock mode or slave clock mode. in slave mode, lrck and sclk are supplied externally, and lrck and sclk must be synchronously derived from the system clock with specific rates. in master mode, lrck and sclk are derived internally from device master clock. 5. micro - controller configura tion interface the device supports standard i 2 c micro - controller configuration interface. external micro - controller can completely configure the device through writing to internal configuration registers. i 2 c interface is a bi - directional serial bus that uses a serial data line (cdata) and a serial clock line (cclk) for data transfer. the timing diagram for data transfer of this interface is given in figure 1a and figure 1b. data are transmitted synchronously to cclk clock on the cdata line on a byte - by - byte basis. each bit in a byte is sampled during cclk high with msb bit be ing transmitted firstly. each transferred byte is followed by an acknowledge bit from receiver to pull the cdata low. the transfer rate of this interface can be up to 400 kbps. a master controller initiates the transmission by sending a start signal, whi ch is defined as a high - to - low transition at cdata while cclk is high. the first byte transferred is the slave address. it is a seven - bit chip address followed by a rw bit. the chip address must be 0 0 11 0 0 x, where x equals ce . the rw bit indicates the slav e data transfer direction. once an acknowledge bit is received, the data transfer starts to proceed on a byte - by - byte basis in the direction specified by the rw bit. the master can terminate the communication by generating a stop signal, which is defined as a low -to - high transition at cdata while cclk is high. in i 2 c interface mode, the registers can be written and read. the formats of write and read instructions are shown in table 1 and table 2. please note that, to read data from a register, you mus t set r/w bit to 0 to access the register address and then set r/w to 1 to read data from the register. table 1 write data to register in i 2 c interface mode chip address r/w register address data to be written start 0 0 11 00 ce 0 ack ram ack data ack stop
everest semiconductor confidential ES8311 revision 5 .0 6 march 2019 latest datasheet: www.everest - semi.com or info@everest - semi.com figure 1a i 2 c write timing table 2 read data from register in i 2 c interface mode chip address r/w register address start 0 0 11 00 ce 0 ack ram ack chip address r/w data to be read start 0 0 11 00 ce 1 ack data nack stop figure 1b i 2 c read timing stop ack ack write ack chip addr start bit 1 to 7 bit 1 to 8 reg addr bit 1 to 8 write data cclk cdata stop ack write ack chip addr start bit 1 to 7 bit 1 to 8 reg addr bit 1 to 8 read data start read ack chip addr bit 1 to 7 no ack cclk cdata
everest semiconductor confidential ES8311 revision 5 .0 7 march 2019 latest datasheet: www.everest - semi.com or info@everest - semi.com 6. digital audio interf ace the device provides many formats of serial audio data interface to the input of the dac or out put from the adc through lrck, sclk and dsdin or asdout pins. these formats are i 2 s, left justified, right justified and dsp/pcm . dac input dsdin is sampled by the device on the rising edge of sclk. adc data is out at asdout on the falling edge of sclk. t he relationship of sdata (dsin/asdout ), sclk and lrck with these formats are shown through figure 2 a to figure 2d . figure 2a i 2 s serial audio data format figure 2b left justified serial audio data format figure 2c dsp/pcm mode a serial audio data format figure 2d dsp/pcm mode b serial audio data format sdata 1 sclk 1 sclk r channel l channel m sb lsb m sb l sb sclk lrck lsb 1 sclk r channel l channel m sb l sb msb sdata sclk lrck sdata r channel l channel m sb l sb m sb l sb sclk lrck lsb r channel l channel m sb l sb msb sdata sclk lrck
everest semiconductor confidential ES8311 revision 5 .0 8 march 2019 latest datasheet: www.everest - semi.com or info@everest - semi.com 7. electrical character istics absolute maximum rat ings continuous operation at or beyond these conditions may permanently damage the device. parameter min max analog supply voltage level - 0.3v +3.6 v digital supply voltage level - 0.3v +3.6 v analog input voltage range a gnd - 0.3v a vdd+0.3v digital input voltage range d gnd - 0.3v p vdd+0.3v operating temperature range - 40 c + 10 5 c storage temperature -65 c +150 c recommended operatin g conditions parameter min typ max unit d vdd 1.6 3.3 3.6 v p vdd 1.6 3.3 3.6 v a vdd 1. 7 3.3 3.6 v adc analog and filte r characteristics an d specifications test conditions are as the following unless otherwi se specify: a vdd =3.3v, d vdd=3.3 v, agnd=0v, dgnd=0v, ambient temperature=25 c, fs=48 khz , mclk/lrck=256. parameter min typ max unit adc performance signal to noise ratio (a - weigh) 9 5 100 10 2 db thd+n - 9 5 - 93 - 8 5 db gain error 5 % filter frequency response C single speed passband 0 0.4535 fs stopband 0.5465 fs passband ripple 0.05 db stopband attenuation 7 0 db filter frequency response C double speed passband 0 0.4167 fs stopband 0.5833 fs passband ripple 0.005 db stopband attenuation 7 0 db analog input full scale input level avdd/3.3 vrms input impedance 6 k dac analog and filte r characteristics an d specifications test conditions are as the following unless otherwise specify: a vdd=3.3v, d vdd=3.3v, agnd=0v, dgnd=0v, ambient temperature=25 c, fs=48 khz , mclk/lrck=256.
everest semiconductor confidential ES8311 revision 5 .0 9 march 2019 latest datasheet: www.everest - semi.com or info@everest - semi.com parameter min typ max unit dac performance signal to noise ratio (a - weigh) 100 1 10 11 5 db thd+n - 8 5 - 8 0 - 75 db gain error 5 % filter frequency response C single speed passband 0 0.4535 fs stopband 0.5465 fs passband ripple 0.05 db stopband attenuation 53 db filter frequency response C double speed passband 0 0.4167 fs stopband 0.5833 fs passband ripple 0.005 db stopband attenuation 56 db analog output full scale output level avdd/3.3 vrms dc characteristics parameter min typ max unit normal operation mode d vdd =1.8 v, pvdd=1.8 v, av dd=3.3v 8 ma power down mode d vdd =1.8 v, pvdd=1.8 v, av dd=3.3v 0 ua digital voltage level input high - level voltage 0.7*pvdd v input low - level voltage 0. 5 v output high - level voltage pvdd v output low - level voltage 0 v serial audio port sw itching specificatio ns parameter symbol min max unit mclk frequency 51.2 mhz mclk duty cycle 40 60 % lrck frequency 200 khz lrck duty cycle 40 60 % sclk frequency 26 mhz sclk pulse width low t sclkl 15 ns sclk pulse width high t sclkh 15 ns sclk falling to lrck edge t slr C 10 10 ns sclk falling to sdout valid t sdo 11 ns
everest semiconductor confidential ES8311 revision 5 .0 10 march 2019 latest datasheet: www.everest - semi.com or info@everest - semi.com figure 3 serial audio port timing i 2 c switching specific ations parameter symbol min max unit cclk clock frequency f cclk 400 khz bus free time between transmissions t twid 1.3 us start condition hold time t twsth 0.6 us clock low time t twcl 1.3 us clock high time t twch 0.4 us setup time for repeated start condition t twsts 0.6 us cdata hold time from cclk falling t twdh 900 ns cdata setup time to cclk rising t twds 100 ns rise time of cclk t twr 300 ns fall time cclk t twf 300 ns figure 4 i 2 c timing
everest semiconductor confidential ES8311 revision 5 .0 11 march 2019 latest datasheet: www.everest - semi.com or info@everest - semi.com 8. package
everest semiconductor confidential ES8311 revision 5 .0 12 march 2019 latest datasheet: www.everest - semi.com or info@everest - semi.com 9. corpo rate information everest semiconductor co., ltd. no. 1355 jinjihu drive, suzhou industrial park, jiangsu, p.r. china, zip code 215021 ????? 1355 ???? , ? 215021 email: info@everest - semi.com

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