features description/ordering information sn74alvch32374 32-bit edge-triggered d-type flip-flop with 3-state outputs sces283d ? october 1999 ? revised august 2004 latch-up performance exceeds 100 ma per jesd 78, class ii member of the texas instruments widebus+? family esd protection exceeds jesd 22 operates from 1.65 v to 3.6 v ? 2000-v human-body model (a114-a) max t pd of 4.2 ns at 3.3 v ? 200-v machine model (a115-a) 24-ma output drive at 3.3 v ? 1000-v charged-device model (c101) bus hold on data inputs eliminates the need for external pullup/pulldown resistors this 32-bit edge-triggered d-type flip-flop is designed for 1.65-v to 3.6-v v cc operation. the sn74alvch32374 is particularly suitable for implementing buffer registers, i/o ports, bidirectional bus drivers, and working registers. it can be used as four 8-bit flip-flops, two 16-bit flip-flops, or one 32-bit flip-flop. on the positive transition of the clock (clk) input, the q outputs of the flip-flop take on the logic levels at the data (d) inputs. the output-enable (oe) input can be used to place the eight outputs in either a normal logic state (high or low logic levels) or the high-impedance state. in the high-impedance state, the outputs neither load nor drive the bus lines significantly. the high-impedance state and the increased drive provide the capability to drive bus lines without need for interface or pullup components. oe does not affect internal operations of the flip-flop. old data can be retained or new data can be entered while the outputs are in the high-impedance state. to ensure the high-impedance state during power up or power down, oe should be tied to v cc through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. active bus-hold circuitry holds unused or undriven inputs at a valid logic state. use of pullup or pulldown resistors with the bus-hold circuitry is not recommended. ordering information t a package (1) orderable part number top-side marking lfbga - gke sn74alvch32374kr -40c to 85c tape and reel ach374 lfbga - zke (pb-free) 74alvch32374zker (1) package drawings, standard packing quantities, thermal data, symbolization, and pcb design guidelines are available at www.ti.com/sc/package. function table (each flip-flop) inputs output q oe clk d l - h h l - l l l h or l x q 0 h x x z please be aware that an important notice concerning availability, standard warranty, and use in critical applications of texas instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. widebus+ is a trademark of texas instruments. production data information is current as of publication date. copyright ? 1999?2004, texas instruments incorporated products conform to specifications per the terms of the texas instruments standard warranty. production processing does not necessarily include testing of all parameters. www .ti.com
logic diagram (positive logic) sn74alvch32374 32-bit edge-triggered d-type flip-flop with 3-state outputs sces283d ? october 1999 ? revised august 2004 2 www .ti.com gke or zke p ackage (t op view) ab c d e f g h j k l m n p r t 1 2 3 4 5 6 1q21q4 1q6 1q8 2q2 2q4 2q6 2q7 3q2 3q4 3q6 3q8 4q2 4q4 4q6 4q7 1q11q3 1q5 1q7 2q1 2q3 2q5 2q8 3q1 3q3 3q5 3q7 4q1 4q3 4q5 4q8 gndgnd gnd gnd gnd gnd gnd gnd 1clk gndgnd gnd gnd 2clk3clk gndgnd gnd gnd 4clk 1d11d3 1d5 1d7 2d1 2d3 2d5 2d8 3d1 3d3 3d5 3d7 4d1 4d3 4d5 4d8 1d21d4 1d6 1d8 2d2 2d4 2d6 2d7 3d2 3d4 3d6 3d8 4d2 4d4 4d6 4d7 1 2 3 4 5 6 ab c d e f g h j k l m n p r t 1oe v c c v c c 2oe 3oe v c c v c c 4oe v c c v c c v c c v c c terminal assignments 1oe 1clk 1d1 t o seven other channels 1q1 c11d a3a4 a5 a2 2oe 2clk 2d1 t o seven other channels 2q1 c11d h3h4 e5 e2 3oe 3clk 3d1 t o seven other channels 3q1 c11d j3j4 j5 j2 4oe 4clk 4d1 t o seven other channels 4q1 c11d t3t4 n5 n2
absolute maximum ratings (1) recommended operating conditions (1) sn74alvch32374 32-bit edge-triggered d-type flip-flop with 3-state outputs sces283d ? october 1999 ? revised august 2004 over operating free-air temperature range (unless otherwise noted) min max unit v cc supply voltage range -0.5 4.6 v v i input voltage range (2) -0.5 4.6 v v o output voltage range (2) (3) -0.5 v cc + 0.5 v i ik input clamp current v i < 0 -50 ma i ok output clamp current v o < 0 -50 ma i o continuous output current 50 ma continuous current through each v cc or gnd 100 ma q ja package thermal impedance (4) gke/zke package 40 c/w t stg storage temperature range -65 150 c (1) stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. these are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. (2) the input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed. (3) this value is limited to 4.6 v maximum. (4) the package thermal impedance is calculated in accordance with jesd 51-7. min max unit operating 1.65 3.6 v cc supply voltage v data retention only 1.5 v cc = 1.65 v to 1.95 v 0.65 v cc v ih high-level input voltage v cc = 2.3 v to 2.7 v 1.7 v v cc = 2.7 v to 3.6 v 2 v cc = 1.65 v to 1.95 v 0.35 v cc v il low-level input voltage v cc = 2.3 v to 2.7 v 0.7 v v cc = 2.7 v to 3.6 v 0.8 v i input voltage 0 v cc v v o output voltage 0 v cc v v cc = 1.65 v -4 v cc = 2.3 v -8 i oh high-level output current ma v cc = 2.7 v -12 v cc = 3 v -24 v cc = 1.65 v 4 v cc = 2.3 v 8 i ol low-level output current ma v cc = 2.7 v 12 v cc = 3 v 24 dt/dv input transition rise or fall rate 10 ns/v t a operating free-air temperature -40 85 c (1) all unused control inputs of the device must be held at v cc or gnd to ensure proper device operation. refer to the ti application report, implications of slow or floating cmos inputs, literature number scba004. 3 www .ti.com
electrical characteristics timing requirements sn74alvch32374 32-bit edge-triggered d-type flip-flop with 3-state outputs sces283d ? october 1999 ? revised august 2004 over recommended operating free-air temperature range (unless otherwise noted) parameter test conditions v cc min typ (1) max unit i oh = -100 ma 1.65 v to 3.6 v v cc - 0.2 i oh = -4 ma 1.65 v 1.2 i oh = -8 ma 2.3 v 1.7 v oh v 2.7 v 2.2 i oh = -12 ma 3 v 2.4 i oh = -24 ma 3 v 2.2 i ol = 100 ma 1.65 v to 3.6 v 0.2 i ol = 4 ma 1.65 v 0.45 v ol i ol = 8 ma 2.3 v 0.7 v i ol = 12 ma 2.7 v 0.4 i ol = 24 ma 3 v 0.55 i i v i = v cc or gnd 3.6 v 5 ma v i = 0.58 v 1.65 v 25 v i = 1.07 v 1.65 v -25 v i = 0.7 v 2.3 v 45 i i(hold) v i = 1.7 v 2.3 v -45 ma v i = 0.8 v 3 v 75 v i = 2 v 3 v -75 v i = 0 to 3.6 v (2) 3.6 v 500 i oz v o = v cc or gnd 3.6 v 10 ma i cc v i = v cc or gnd, i o = 0 3.6 v 80 ma di cc one input at v cc - 0.6 v, other inputs at v cc or gnd 3 v to 3.6 v 750 ma control inputs 3 c i v i = v cc or gnd 3.3 v pf data inputs 6 c o outputs v o = v cc or gnd 3.3 v 7 pf (1) all typical values are at v cc = 3.3 v, t a = 25c. (2) this is the bus-hold maximum dynamic current. it is the minimum overdrive current required to switch the input from one state to another. over recommended operating free-air temperature range (unless otherwise noted) (see figure 1) v cc = 1.8 v v cc = 2.5 v v cc = 3.3 v v cc = 2.7 v 0.15 v 0.2 v 0.3 v unit min max min max min max min max f clock clock frequency (1) 150 150 150 mhz t w pulse duration, clk high or low (1) 3.3 3.3 3.3 ns t su setup time, data before clk- (1) 2.1 2.2 1.9 ns t h hold time, data after clk- (1) 0.6 0.5 0.5 ns (1) this information was not available at the time of publication. 4 www .ti.com
switching characteristics operating characteristics sn74alvch32374 32-bit edge-triggered d-type flip-flop with 3-state outputs sces283d ? october 1999 ? revised august 2004 over recommended operating free-air temperature range (unless otherwise noted) (see figure 1) v cc = 1.8 v v cc = 2.5 v v cc = 3.3 v v cc = 2.7 v from to 0.15 v 0.2 v 0.3 v parameter unit (input) (output) min max min max min max min max f max (1) 150 150 150 mhz t pd clk q (1) (1) 1 5.3 4.9 1 4.2 ns t en oe q (1) (1) 1 6.2 5.9 1 4.8 ns t dis oe q (1) (1) 1 5.3 4.7 1.2 4.3 ns (1) this information was not available at the time of publication. t a = 25c v cc = 1.8 v v cc = 2.5 v v cc = 3.3 v parameter test conditions unit typ typ typ outputs enabled (1) 31 30 power dissipation c pd c l = 50 pf, f = 10 mhz pf capacitance outputs disabled (1) 16 18 (1) this information was not available at the time of publication. 5 www .ti.com
parameter measurement information sn74alvch32374 32-bit edge-triggered d-type flip-flop with 3-state outputs sces283d ? october 1999 ? revised august 2004 figure 1. load circuit and voltage waveforms 6 www .ti.com v m v m v m v m v m v m v m v m v o h v o l t h t s u from output under t est c l (see note a) load circuit s1 open gnd r l r l output control (low-level enabling) output w aveform 1 s1 at v l o a d (see note b) output w aveform 2 s1 at gnd (see note b) t p z l t p z h t p l z t p h z 0 v v o l + v d v o h ? v d 0 v v i 0 v0 v t w v i v i vol t age w a veforms setup and hold times vol t age w a veforms pulse dura tion vol t age w a veforms enable and disable times t iming input data input input t p d t p l z /t p z l t p h z /t p z h open v l o a d gnd test s1 notes: a. c l includes probe and jig capacitance. b. w aveform 1 is for an output with internal conditions such that the output is low , except when disabled by the output control. w aveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control. c. all input pulses are supplied by generators having the following characteristics: prr 10 mhz, z o = 50 w . d. the outputs are measured one at a time, with one transition per measurement. e. t p l z and t p h z are the same as t d i s . f. t p z l and t p z h are the same as t e n . g. t p l h and t p h l are the same as t p d . h. all parameters and waveforms are not applicable to all devices. 0 v v i v m t p h l v m v m v i 0 vv o h v o l input output vol t age w a veforms prop aga tion dela y times v m v m t p l h v l o a d v l o a d /2 1.8 v 0.15 v 2.5 v 0.2 v 2.7 v 3.3 v 0.3 v 1 k w 500 w 500 w 500 w v c c r l 2 v c c 2 v c c 6 v6 v v l o a d c l 30 pf30 pf 50 pf 50 pf 0.15 v0.15 v 0.3 v0.3 v v d v c c v c c 2.7 v2.7 v v i v c c /2 v c c /2 1.5 v1.5 v v m t r /t f 2 ns 2 ns 2.5 ns 2.5 ns input
package option addendum www.ti.com 11-apr-2013 addendum-page 1 packaging information orderable device status (1) package type package drawing pins package qty eco plan (2) lead/ball finish msl peak temp (3) op temp (c) top-side markings (4) samples 74alvch32374zker active lfbga zke 96 1000 green (rohs & no sb/br) snagcu level-3-260c-168 hr -40 to 85 ach374 SN74ALVCH32374GKE obsolete lfbga gke 96 tbd call ti call ti -40 to 85 sn74alvch32374kr nrnd lfbga gke 96 1000 tbd snpb level-2-235c-1 year -40 to 85 ach374 (1) the marketing status values are defined as follows: active: product device recommended for new designs. lifebuy: ti has announced that the device will be discontinued, and a lifetime-buy period is in effect. nrnd: not recommended for new designs. device is in production to support existing customers, but ti does not recommend using this part in a new design. preview: device has been announced but is not in production. samples may or may not be available. obsolete: ti has discontinued the production of the device. (2) eco plan - the planned eco-friendly classification: pb-free (rohs), pb-free (rohs exempt), or green (rohs & no sb/br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. tbd: the pb-free/green conversion plan has not been defined. pb-free (rohs): ti's terms "lead-free" or "pb-free" mean semiconductor products that are compatible with the current rohs requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. where designed to be soldered at high temperatures, ti pb-free products are suitable for use in specified lead-free processes. pb-free (rohs exempt): this component has a rohs exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. the component is otherwise considered pb-free (rohs compatible) as defined above. green (rohs & no sb/br): ti defines "green" to mean pb-free (rohs compatible), and free of bromine (br) and antimony (sb) based flame retardants (br or sb do not exceed 0.1% by weight in homogeneous material) (3) msl, peak temp. -- the moisture sensitivity level rating according to the jedec industry standard classifications, and peak solder temperature. (4) multiple top-side markings will be inside parentheses. only one top-side marking contained in parentheses and separated by a "~" will appear on a device. if a line is indented then it is a continuation of the previous line and the two combined represent the entire top-side marking for that device. important information and disclaimer: the information provided on this page represents ti's knowledge and belief as of the date that it is provided. ti bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. efforts are underway to better integrate information from third parties. ti has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. ti and ti suppliers consider certain information to be proprietary, and thus cas numbers and other limited information may not be available for release. in no event shall ti's liability arising out of such information exceed the total purchase price of the ti part(s) at issue in this document sold by ti to customer on an annual basis.
tape and reel information *all dimensions are nominal device package type package drawing pins spq reel diameter (mm) reel width w1 (mm) a0 (mm) b0 (mm) k0 (mm) p1 (mm) w (mm) pin1 quadrant 74alvch32374zker lfbga zke 96 1000 330.0 24.4 5.7 13.7 2.0 8.0 24.0 q1 sn74alvch32374kr lfbga gke 96 1000 330.0 24.4 5.7 13.7 2.0 8.0 24.0 q1 package materials information www.ti.com 27-jun-2013 pack materials-page 1
*all dimensions are nominal device package type package drawing pins spq length (mm) width (mm) height (mm) 74alvch32374zker lfbga zke 96 1000 336.6 336.6 41.3 sn74alvch32374kr lfbga gke 96 1000 336.6 336.6 41.3 package materials information www.ti.com 27-jun-2013 pack materials-page 2
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