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general description the max17582 is a 2-/1-phase-interleaved quick-pwm? step-down vid power-supply controller for notebook cpus. true out-of-phase operation reduces input-ripple-current requirements and output-voltage ripple, while easing component selection and layout dif- ficulties. the quick-pwm control provides instanta- neous response to fast load-current steps. active voltage positioning reduces power dissipation and bulk output capacitance requirements and allows ideal posi- tioning compensation for tantalum, polymer, or ceramic bulk output capacitors. a slew-rate controller allows controlled transitions among vid codes, controlled soft-start and shutdown, and con- trolled exit from suspend. a thermistor-based temperature sensor provides a programmable thermal-fault output ( vrhot ). a current-monitor output (imon) provides an analog current output proportional to the power consumed by the cpu. the max17582 includes output undervolt- age and thermal protection. when any of these protec-tion features detect a fault, the controller shuts down. a voltage-regulator power-ok (pwrgd) output indicates the output is in regulation. additionally, the max17582 features true differential current sense and a phase-good (phasegd) output that indicates a phase imbalance fault condition. the max17582 implements the intel imvp-6.5 vid code set. the max17582 is available in a 6mm x 6mm, 48-pin tqfn package. applications imvp-6.5 core supplymultiphase cpu core supply voltage-positioned, step-down converters notebook/desktop computers blade servers features ? single-/dual-phase, quick-pwm controller ? ?mv v out accuracy over line, load, and temperature ? 7-bit 0 to 1.50v vid control ? dynamic phase selection optimizes active/sleepefficiency ? transient phase overlap reduces outputcapacitance ? integrated boost switches ? active voltage positioning with adjustable gain ? programmable 200khz to 800khz switchingfrequency ? accurate current balance and current limit ? adjustable slew-rate control ? power-good, clock enable, and thermal-faultoutputs ? phase current imbalance fault output ? drives large synchronous rectifier mosfets ? 4v to 26v battery input-voltage range ? undervoltage and thermal-fault protection ? imvp-6.5 power sequencing and timingcompliant ? soft-startup and soft-shutdown max17582 dual-phase, quick-pwm controller for imvp-6.5 cpu core power supplies ________________________________________________________________ maxim integrated products 1 top view max17582 thin qfn (6mm x 6mm) 13 14 15 16 17 18 19 20 21 22 23 24 csn2 gnd csp2 shdn dprslpvr psi ton v3p3 clken pwrgd phasegd n.c. 48 47 46 45 44 43 42 41 40 39 38 37 1 2 34 5 678910 11 12 csn1 gnd csp1 d6 d5 d4 d3 d2 d1 d0 slow n.c. n.c. gnds fbac fb cci v cc gnd time ilim imon thrm pgdin 36 35 34 33 32 31 30 29 28 27 26 25 bst2 lx2 dh2 pgnd2 dl2 vrhot v dd dl1 pgnd1 dh1 lx1 bst1 *exposed pad. connected to gnd. + *epgnd pin configuration ordering information 19-4821; rev 0; 7/09 for pricing, delivery, and ordering information, please contact maxim direct at 1-888-629-4642, or visit maxim? website at www.maxim-ic.com. evaluation kit available + denotes a lead(pb)-free/rohs-compliant package. * ep = exposed pad. part temp range pin-package MAX17582GTM+ -40c to +105c 48 tqfn-ep* quick-pwm is a trademark of maxim integrated products, inc. downloaded from: http:///
max17582 dual-phase, quick-pwm controller for imvp-6.5 cpu core power supplies 2 _______________________________________________________________________________________ absolute maximum ratingselectrical characteristics (circuit of figure 1, v in = 10v, v cc = v dd = v shdn = v pgdin = v psi = v ilim = 5v, v3p3 = 3.3v, dprslpvr = gnds = gnd, v csp1 = v csn1 = v csp2 = v csn1 = 1.0000v, fb = fbac, r fbac = 3.57k from fbac to csn1, d6Cd0 = [0101000]; v slow = 5v; t a = 0? to +85? , unless otherwise noted. typical values are at t a = +25c.) stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. these are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. v cc , v dd, v3p3 to gnd ...........................................-0.3v to +6v d0Cd6 to gnd..........................................................-0.3v to +6v pgdin, dprslpvr, psi to gnd..............................-0.3v to +6v slow to gnd ..........................................................-0.3v to +6v csp1, csp2, csn1, csn2 to gnd..........................-0.3v to +6v thrm, ilim, phasegd to gnd...............................-0.3v to +6v pwrgd, vrhot to gnd .........................................-0.3v to +6v clken to gnd .........................................(-0.3v to v3p3) + 0.3v fb, fbac to gnd.......................................(-0.3v to v cc ) + 0.3v time, imon, cci to gnd ...........................(-0.3v to v cc ) + 0.3v pgnd, gnds to gnd ...........................................-0.3v to +0.3v shdn to gnd (note 1)...........................................-0.3v to +16v ton to gnd ...........................................................-0.3v to +30v dl1, dl2 to gnd .......................................-0.3v to (v dd + 0.3v) bst1, bst2 to gnd ...............................................-0.3v to +36v bst1, bst2 to v dd .................................................-0.3v to +30v lx1 to bst1..............................................................-6v to +0.3v lx2 to bst2..............................................................-6v to +0.3v dh1 to lx1 ..............................................(-0.3v to v bst1 ) + 0.3v dh2 to lx2 ..............................................(-0.3v to v bst2 ) + 0.3v continuous power dissipation 6mm x 6mm, 48-pin tqfn up to +70c ...................2105mw (derate above +70c) ...........................................26.3mw/c operating temperature range .........................-40c to +105c junction temperature ......................................................+150c storage temperature range .............................-65c to +165c lead temperature (soldering, 10s) .................................+300c parameter symbol conditions min typ max units pwm controller v cc , v dd 4.5 5.5 input-voltage range v3p3 3.0 3.6 v dac codes from 0.8125v to 1.5000v -0.5 +0.5 % dac codes from 0.3750v to 0.8000v -7 +7 dc output-voltage accuracy v out measured at fb with respect to gnds; includes load- regulation error (note 2) dac codes from 0 to 0.3625v -20 +20 mv boot voltage v boot 1.094 1.100 1.106 v line regulation error v cc = 4.5v to 5.5v, v in = 4.5v to 26v 0.1 % fb input bias current t a = +25c -0.1 +0.1 a gnds input range -200 +200 mv gnds gain a gnds v out / v gnds 0.97 1.00 1.03 v/v gnds input bias current i gnds t a = +25c -0.5 +0.5 a time regulation voltage v time r time = 71.5k 1.985 2.000 2.015 v note 1: shdn might be forced to 12v for the purpose of debugging prototype boards using the no-fault test mode, which disables fault protection and overlapping operation. downloaded from: http:///
max17582 dual-phase, quick-pwm controller for imvp-6.5 cpu core power supplies _______________________________________________________________________________________ 3 electrical characteristics (continued)(circuit of figure 1, v in = 10v, v cc = v dd = v shdn = v pgdin = v psi = v ilim = 5v, v3p3 = 3.3v, dprslpvr = gnds = gnd, v csp1 = v csn1 = v csp2 = v csn1 = 1.0000v, fb = fbac, r fbac = 3.57k from fbac to csn1, d6Cd0 = [0101000]; v slow = 5v; t a = 0? to +85? , unless otherwise noted. typical values are at t a = +25c.) parameter symbol conditions min typ max units r time = 71.5k (12.5mv/s nominal) -10 +10 r time = 35.7k (25mv/s nominal) to 178k (5mv/s nominal) -15 +15 soft-start and soft-shutdown: r time = 35.7k (3.125mv/s nominal) to 178k (0.625mv/s nominal) -25 +25 slow: v slow = 0v, 1/2 of nominal slew rate, r time = 71.5k (6.25mv/s nominal) -15 +15 time slew-rate accuracy slow: v slow = 0v, 1/2 of nominal slew rate, r time = 35.7k (12.5mv/s nominal) to 178k (2.5mv/s nominal) -15 +15 % r ton = 96.75k (600khz per phase), 167ns nominal -15 +15 r ton = 200k (300khz per phase), 333ns nominal -10 +10 on-time t on measured at dh_ (note 3) r ton = 303.25k (200khz per phase), 500ns nominal -15 +15 % minimum off-time t off(min) measured at dh_ (note 3) 300 350 ns ton shutdown input current i rton,sdn shdn = gnd, v in = 26v, v cc = v dd = 0v or 5v, t a = +25c 0.01 0.1 a bias currents quiescent supply current (v cc ) i cc measured at v cc , v dprslpvr = 5v, fb forced above the regulation point 2.5 5 ma quiescent supply current (v dd ) i dd measured at v dd , v dprslpvr = 0v, fb forced above the regulation point, t a = +25c 0.02 1 a quiescent supply current (v3p3) i 3p3 measured at v3p3, fb forced within the clken power-good window 2 4 a shutdown supply current (v cc ) i cc,sdn measured at v cc , shdn = gnd, t a = +25c 0.01 1 a shutdown supply current (v dd ) i dd,sdn measured at v dd , shdn = gnd, t a = +25c 0.01 1 a shutdown supply current (v3p3) i 3p3,sdn measured at v3p3, shdn = gnd, t a = +25c 0.01 1 a downloaded from: http:///
max17582 dual-phase, quick-pwm controller for imvp-6.5 cpu core power supplies 4 _______________________________________________________________________________________ electrical characteristics (continued)(circuit of figure 1, v in = 10v, v cc = v dd = v shdn = v pgdin = v psi = v ilim = 5v, v3p3 = 3.3v, dprslpvr = gnds = gnd, v csp1 = v csn1 = v csp2 = v csn1 = 1.0000v, fb = fbac, r fbac = 3.57k from fbac to csn1, d6Cd0 = [0101000]; v slow = 5v; t a = 0? to +85? , unless otherwise noted. typical values are at t a = +25c.) parameter symbol conditions min typ max units fault protection output undervoltage- protection threshold v uvp measured at fb with respect to the voltage target set by the vid code; see table 4 -450 -400 -350 mv output undervoltage- propagation dela y t uvp fb forced 25mv below trip threshold 10 s clken startup delay and boot time period t boot measured from the time when fb reaches the boot target voltage (note 2) 20 60 100 s pwrgd startup delay measured at startup from the time when clken goes low 3 6.5 10 ms lower threshold, falling edge (undervoltage) -350 -300 -250 clken and pwrgd threshold measured at fb with respect to the voltage target set by the vid code; see table 4, 20mv hysteresis (typ) upper threshold, rising edge (overvoltage) +150 +200 +250 mv clken and pwrgd delay fb forced 25mv outside the pwrgd trip thresholds 10 s phasegd delay v (cci,fb) forced 25mv outside trip thresholds 10 s clken , pwrgd, and phasegd transition blanking time (vid transitions) t blank measured from the time when fb reaches the target voltage (note 2) 20 s phasegd transition blanking time (phase 2 enable transitions) number of dh2 pulses for which phasegd is blanked after phase 2 is enabled 32 pulses clken output low voltage low state, i sink = 3ma 0.4 v clken output high voltage high state, i source = 3ma v3p3 - 0.4 v pwrgd, phasegd output low voltage low state, i sink = 3ma 0.4 v pwrgd, phasegd leakage current high-impedance state, pwrgd, phasegd forced to 5v, t a = +25c 1 a csn1 pulldown resistance in shutdown shdn = 0, measured after soft-shutdown completed (dl_ = low) 10 v cc undervoltage lockout (uvlo) threshold v uvlo(vcc) rising edge, 65mv typical hysteresis, controller disabled below this level 4.05 4.27 4.48 v downloaded from: http:///
max17582 dual-phase, quick-pwm controller for imvp-6.5 cpu core power supplies _______________________________________________________________________________________ 5 electrical characteristics (continued)(circuit of figure 1, v in = 10v, v cc = v dd = v shdn = v pgdin = v psi = v ilim = 5v, v3p3 = 3.3v, dprslpvr = gnds = gnd, v csp1 = v csn1 = v csp2 = v csn1 = 1.0000v, fb = fbac, r fbac = 3.57k from fbac to csn1, d6Cd0 = [0101000]; v slow = 5v; t a = 0? to +85? , unless otherwise noted. typical values are at t a = +25c.) parameter symbol conditions min typ max units thermal protection vrhot trip threshold measured at thrm as a percentage of v cc , falling edge, typical hysteresis = 75mv 29 30 31 % vrhot delay t vrhot thrm forced 25mv below the vrhot trip threshold, falling edge 10 s vrhot output on-resistance r on( vrhot ) low state 2 10 vrhot leakage current high-impedance state, vrhot forced to 5v, t a = +25c 1 a thrm input leakage i thrm v thrm = 0 to 5v, t a = +25c -0.1 +0.1 a thermal-shutdown threshold t shdn typical hysteresis = 15c 160 c valley current limit, droop, and current balance v time - v ilim = 100mv 7 10 13 v time - v ilim = 500mv 45 50 55 current-limit threshold voltage (positive) v limit v csp_ - v csn_ ilim = v cc 20 22.5 25 mv current-limit threshold voltage (negative) accuracy v limit(neg) v csp_ - v csn_ , nominally -125% of v limit -4 +4 mv current-limit threshold voltage (zero crossing) v zero v gnd - v lx_ , dprslpvr = 5v 1 mv csp_, csn_ common- mode input range 0 2 v phase 2 disable threshold measured at csp2 3 v cc - 1 v cc - 0.4 v csp_, csn_ input current i csp_ , i csn_ t a = +25c -0.2 +0.2 a ilim input current i ilim t a = +25c -0.1 +0.1 a t a = +25 o c -0.5 +0.5 droop amplifier offset (1/n) x (v csp_ - v csn_ ) at i fbac = 0; indicates summation over all phases from 1 to n, n = 2 t a = 0 o c to +85 o c -0.75 +0.75 mv/ phase droop amplifier transconductance g m(fbac) i fbac / [ (v csp_ - v csn_ )]; indicates summation over all phases from 1 to n, n = 2, v fbac = v csn- = 0.45v to 2v 590 600 608 s current-balance amplifier offset (v csp1 - v csn1 ) - (v csp2 - v csn2 ) at i cci = 0v -1.0 +1.0 mv current-balance amplifier transconductance g m(cci) i cci /[(v csp1 - v csn1 ) - (v csp2 - v csn2 )] 200 s downloaded from: http:///
max17582 dual-phase, quick-pwm controller for imvp-6.5 cpu core power supplies 6 _______________________________________________________________________________________ electrical characteristics (continued)(circuit of figure 1, v in = 10v, v cc = v dd = v shdn = v pgdin = v psi = v ilim = 5v, v3p3 = 3.3v, dprslpvr = gnds = gnd, v csp1 = v csn1 = v csp2 = v csn1 = 1.0000v, fb = fbac, r fbac = 3.57k from fbac to csn1, d6Cd0 = [0101000]; v slow = 5v; t a = 0? to +85? , unless otherwise noted. typical values are at t a = +25c.) parameter symbol conditions min typ max units current monitor current-monitor output current at full load condition i imon v csp1 - v csn1 = v csp2 - v csn2 = 20mv, v csn_ = 0.45v to 2.0v 93.12 96 98.88 a current-monitor transconductance g m(imon) i imon / [ (v csp_ - v csn_ )]; indicates summation over all phases from 1 to n, n = 2, csn_ = 0.45v to 2v 2.2 2.4 2.6 ms imon clamp voltage v imon,max i sink = 10ma 1.05 1.10 1.15 v imon pulldown resistance in shutdown shdn = 0, measured after soft-shutdown completed (dl_ = low) 10 gate drivers high state (pullup) 0.9 2.5 dh_ gate driver on-resistance r on(dh_) bst_ - lx_ forced to 5v low state (pulldown) 0.7 2.0 high state (pullup) 0.7 2.0 dl_ gate driver on-resistance r on(dl_) low state (pulldown) 0.25 0.7 dh_ gate driver source current i dh_(source) dh_ forced to 2.5v, bst_ - lx_ forced to 5v 2.2 a dh_ gate driver sink current i dh_(sink) dh_ forced to 2.5v, bst_ - lx_ forced to 5v 2.7 a dl_ gate driver source current i dl_(source) dl_ forced to 2.5v 2.7 a dl_ gate driver sink current i dl_(sink) dl_ forced to 2.5v 8 a internal bst_ switch on-resistance r on(bst_) 10 20 logic and i/o logic input high voltage v ih shdn , pgdin 2.3 v logic input low voltage v il shdn , pgdin 1.0 v shdn no-fault level to enable no-fault mode 11 13 v low-voltage logic input high voltage v ihlv psi , d0Cd6; dprslpvr, slow 0.67 v low-voltage logic input low voltage v illv psi , d0Cd6; dprslpvr, slow 0.33 v logic input current t a = +25c, shdn , dprslpvr, pgdin, psi , slow , d0Cd6 = 0 or 5v -1 +1 a downloaded from: http:///
max17582 dual-phase, quick-pwm controller for imvp-6.5 cpu core power supplies _______________________________________________________________________________________ 7 electrical characteristics(circuit of figure 1, v in = 10v, v cc = v dd = v shdn = v pgdin = v psi = v ilim = 5v, v3p3 = 3.3v, dprslpvr = gnds = gnd, v csp1 = v csn1 = v csp2 = v csn2 = 1.0000v, fb = fbac, r fbac = 3.57k from fbac to csn1, d6Cd0 = [0101000]; v slow = 5v; t a = -40? to +105? , unless otherwise noted.) (note 4) parameter symbol conditions min typ max units pwm controller v cc , v dd 4.5 5.5 input-voltage range v3p3 3.0 3.6 v dac codes from 0.8125v to 1.5000v -0.75 +0.75 % dac codes from 0.3750v to 0.8000v -10 +10 dc output-voltage accuracy v out measured at fb with respect to gnds; includes load- regulation error (note 2) dac codes from 0 to 0.3625v -25 +25 mv boot voltage v boot 1.09 1.11 v gnds input range -200 +200 mv gnds gain a gnds v out / v gnds 0.97 1.03 v/v time regulation voltage v time r time = 71.5k 1.985 2.015 v r time = 71.5k (12.5mv/s nominal) -10 +10 r time = 35.7k (25mv/s nominal) to 178k (5mv/s nominal) -15 +15 soft-start and soft-shutdown: r time = 35.7k (3.125mv/s nominal) to 178k (0.625mv/s nominal) -25 +25 slow: v slow = 0v, 1/2 of nominal slew rate, r time = 71.5k (6.25mv/s nominal) -15 +15 time slew-rate accuracy slow: v slow = 0v, 1/2 of nominal slew rate, r time = 35.7k (12.5mv/s nominal) to 178k (2.5mv/s nominal) -17 +17 % r ton = 96.75k (600khz per phase), 167ns nominal -15 +15 r ton = 200k (300khz per phase), 333ns nominal -15 +15 on-time t on measured at dh_ (note 3) r ton = 303.25k (200khz per phase), 500ns nominal -15 +15 % minimum off-time t off(min) measured at dh_ (note 3) 350 ns bias currents quiescent supply current (v cc ) i cc measured at v cc , v dprslpvr = 5v, fb forced above the regulation point 5 ma quiescent supply current (v3p3) i 3p3 measured at v3p3, fb forced within the clken power-good window 4 a downloaded from: http:///
max17582 dual-phase, quick-pwm controller for imvp-6.5 cpu core power supplies 8 _______________________________________________________________________________________ electrical characteristics (continued)(circuit of figure 1, v in = 10v, v cc = v dd = v shdn = v pgdin = v psi = v ilim = 5v, v3p3 = 3.3v, dprslpvr = gnds = gnd, v csp1 = v csn1 = v csp2 = v csn2 = 1.0000v, fb = fbac, r fbac = 3.57k from fbac to csn1, d6Cd0 = [0101000]; v slow = 5v; t a = -40? to +105? , unless otherwise noted.) (note 4) parameter symbol conditions min typ max units fault protection output undervoltage- protection threshold v uvp measured at fb with respect to the voltage target set by the vid code; see table 4 -450 -350 mv clken startup delay and boot time period t boot measured from the time when fb reaches the boot target voltage (note 3) 20 100 s pwrgd startup delay measured at startup from the time when clken goes low 3 10 ms lower threshold, falling edge (undervoltage) -350 -250 clken and pwrgd threshold measured at fb with respect to the voltage target set by the vid code; see table 4, 20mv hysteresis (typ) upper threshold, rising edge (overvoltage) +150 +250 mv clken output low voltage low state, i sink = 3ma 0.4 v clken output high voltage high state, i source = 3ma v3p3 - 0.4 v pwrgd, phasegd output low voltage low state, i sink = 3ma 0.4 v v cc undervoltage-lockout threshold (uvlo) v uvlo(vcc) rising edge, 65mv typical hysteresis, controller disabled below this level 4.0 4.5 v thermal protection vrhot trip threshold measured at thrm as a percentage of v cc , falling edge, typical hysteresis = 75mv 28 32 % vrhot output on-resistance r on( vrhot ) low state 10 valley current limit, droop, and current balance v time - v ilim = 100mv 7 13 v time - v ilim = 500mv 40 60 current-limit threshold voltage (positive) v limit v csp_ - v csn_ ilim = v cc 19 26 mv csp_, csn_ common-mode input range 0 2 v droop amplifier transconductance g m(fbac) i fbac / [ (v csp_ - v csn_ )], indicates summation over all phases from 1 to n, n = 2, v fbac = v csn- = 0.45v to 2v 585 610 s current-balance amplifier offset (v csp1 - v csn1 ) - (v csp2 - v csn2 ) at i cci = 0v -1.25 +1.25 mv downloaded from: http:///
max17582 dual-phase, quick-pwm controller for imvp-6.5 cpu core power supplies _______________________________________________________________________________________ 9 electrical characteristics (continued)(circuit of figure 1, v in = 10v, v cc = v dd = v shdn = v pgdin = v psi = v ilim = 5v, v3p3 = 3.3v, dprslpvr = gnds = gnd, v csp1 = v csn1 = v csp2 = v csn2 = 1.0000v, fb = fbac, r fbac = 3.57k from fbac to csn1, d6Cd0 = [0101000]; v slow = 5v; t a = -40? to +105? , unless otherwise noted.) (note 4) parameter symbol conditions min typ max units current monitor current-monitor transconductance g m(imon) i imon / [ (v csp_ - v csn_ )], indicates summation over all phases from 1 to n, n = 2, v csn_ = 0.45v to 2v 2.2 2.6 ms imon clamp voltage v imon,max i sink = 10ma 1.05 1.15 v gate drivers high state (pullup) 2.5 dh_ gate driver on-resistance r on(dh_) bst_ - lx_ forced to 5v low state (pulldown) 2.0 high state (pullup) 2.0 dl_ gate driver on-resistance r on(dl_) low state (pulldown) 0.7 logic and i/o logic input high voltage v ih shdn , pgdin 2.3 v logic input low voltage v il shdn , pgdin 1.0 v low-voltage logic input high voltage v ihlv psi , d0Cd6: dprslpvr, slow 0.67 v low-voltage logic input low voltage v illv psi , d0Cd6: dprslpvr, slow 0.33 v note 2: when pulse skipping, the output rises by approximately 1.5% when transitioning from continuous conduction to no load. note 3: on-time and minimum off-time specifications are measured from 50% to 50% at the dh_ and dl_ pins, with lx_ forced tognd, bst_ forced to 5v, and a 500pf capacitor from dh_ to lx_ to simulate external mosfet gate capacitance. actual in- circuit times might be different due to mosfet switching speeds. note 4: specifications to t a = -40c and +105c are guaranteed by design and are not production tested. downloaded from: http:///
output voltage vs. load current (v out(hfm) = 1.075v) max17582 toc01 load current (a) output voltage (v) 40 30 20 10 1.00 1.05 1.10 1.150.95 05 0 efficiency vs. load current (v out(hfm) = 1.075v) max17582 toc02 load current (a) efficiency (%) 10.0 1.0 9080 70 60 100 50 0.1 100.0 7v 12v 20v output voltage vs. load current (v out(lfm) = 0.875v) max17582 toc03 load current (a) output voltage (v) 10 15 5 0.890.88 0.87 0.85 0.84 0.86 0.900.83 02 0 pwm mode skip mode efficiency vs. load current (v out(lfm) = 0.875v) max17582 toc04 load current (a) efficiency (%) 10.0 1.0 8070 60 9050 0.1 100.0 7v 12v 20v skip modepwm mode output voltage vs. load current (v out(c4) = 0.4v) max17582 toc05 load current (a) output voltage (v) 4 3 2 1 0.40 0.410.39 05 efficiency vs. load current (v out(c4) = 0.4v) max17582 toc06 load current (a) efficiency (%) 1.00 0.10 80 7060 50 40 9030 0.01 10.00 7v 12v 20v dprslpvr = v cc switching frequency vs. load current max17582 toc07 load current (a) switching frequency (khz) 30 40 10 20 350 300250 200 150 100 50 400 0 05 0 v out(lfm) = 0.875v v out(hfm) = 1.075v dprslpvr = v cc dprslpvr = gnd no-load supply current vs. input voltage (v out(hfm ) = 1.075v) max17582 toc08 input voltage (v) no-load supply current (ma) 15 21 18 912 7550 25 100 0 62 4 i in i cc + i dd dprslpvr = gnd no-load supply current vs. input voltage at skip mode (v out(hfm ) = 1.075v) max17582 toc09 input voltage at skip mode (v) no-load supply current (ma) 15 21 18 912 1.00.1 10.0 0 62 4 i in i cc + i dd dprslpvr = v cc typical operating characteristics (circuit of figure 1. v in = 12v, v cc = v dd = 5v, shdn = v cc , d0Cd6 set for 1.075v, t a = +25c, unless otherwise specified.) max17582 dual-phase, quick-pwm controller for imvp-6.5 cpu core power supplies 10 ______________________________________________________________________________________ downloaded from: http:///
max17582 dual-phase, quick-pwm controller for imvp-6.5 cpu core power supplies ______________________________________________________________________________________ 11 0.8125v output-voltage distribution max17582 toc10 output voltage (v) sample percentage (%) 6050 40 30 20 10 70 0 0.80750.8085 0.8095 0.8105 0.8115 0.8125 0.8135 0.8145 0.8155 0.8165 0.8175 +85 c +25 c sample size = 100 g m(fb) transconductance distribution max17582 toc11 transconductance ( s) sample percentage (%) 5040 30 20 10 60 0 590592 594 596 598 600 602 604 606 608 610 +85 c +25 c sample size = 100 current balance vs. load current max17582 toc12 load current (a) v csp_ - v csn_ (mv) v cspn1 - v cspn2 (mv) 40 45 35 15 20 25 30 50 4030 20 10 60 0 0.5 0.40.3 0.2 0.1 0.60 0510 50 v out = 1.075v max17582 toc13 200 s/div a. shdn, 10v/divb. clken, 10v/div c. v out , 500mv/div d. i lx1 , 10a/div e. i lx2 , 10a/div i out = 15a 5v5v 1.075v 00 0 0 0 ab c d e soft-start waveform (up to clken) max17582 toc14 1ms/div a. shdn, 10v/divb. pwrgd, 10v/div c. phasegd, 10v/div d. clken, 10v/div e. v out , 1v/div f. i lx1 , 10a/div g. i lx2 , 10a/div i out = 15a 5v5v 5v 00 5v 1.075v 00 0 0 0 ab c d e f g soft-start waveform (up to pwrgd) max17582 toc15 100 s/div a. shdn, 10v/divb. clken, 10v/div c. pwrgd, 10v/div d. dl_, 10v/div e. v out , 500mv/div f. i lx1 , 10a/div g. i lx2 , 10a/div 5v5v 5v 00 5v 1.075v 00 0 0 0 ab c d e f g shutdown waveform downloaded from: http:///
max17582 dual-phase, quick-pwm controller for imvp-6.5 cpu core power supplies 12 ______________________________________________________________________________________ max17582 toc16 20 s/div a. i out = 10a to 50a b. v out , 50mv/div c. i lx1 , 10a/div d. i lx2 , 10a/div 50a 1.075v 10a 1v 25a 5a 5a ab c d load-transient response (hfm mode) max17582 toc17 20 s/div a. i out = 5a to 20a b. v out , 50mv/div c. inductor current, 10a/div 20a 0.875v 5a5a 20a ab c load-transient response (lfm mode) max17582 toc18 20 s/div a. vid3, 5v/divb. v out , 50mv/div c. i lx1 , 10a/div d. i lx2 , 10a/div 5v 1.075v0.975v 00 0 ab c d vid code change (slow = gnd) max17582 toc19 20 s/div a. vid3, 5v/divb. v out , 50mv/div c. i lx1 , 10a/div d. i lx2 , 10a/div 5v 1.075v0.975v 00 0 ab c d vid code change (slow = v dd ) max17582 toc20 20 s/div a. d0, 5v/divb. v out , 20mv/div i out = 10a c. i lx1 , 10a/div d. i lx2 , 10a/div 5v 1.075v 1.0625v 0 5a 5a ab c d dynamic vid code change (d0 = 12.5mv) max17582 toc21 100 s/div a. v out , 500mv/div b. pwrgd, 10v/div c. dl_, 10v/divd. i lx1 , 15a/div 5v 1.075v 5v 00 0 0 30a ab c d output undervoltage fault v imon vs. load current max17582 toc22 v cspn1 + v cspn2 (mv) v imon ( a) 30 40 50 10 20 160 140120 100 8060 20 40 180 0 08 0 60 70 v out = 1.075v dprslpvr = v cc dprslpvr = gnd typical operating characteristics (continued) (circuit of figure 1. v in = 12v, v cc = v dd = 5v, shdn = v cc , d0Cd6 set for 1.075v, t a = +25c, unless otherwise specified.) max17582 toc23 40 s/div a. 5v bias supply, 5v/divb. v out , 500mv/div c. pwrgd, 5v/div d. dl_, 5v/dive. i lx1 , 10a/div i out = 10a 5v 5v 0.875v 5v 10a 00 0 0 ab c d e bias supply removal (uvlo response) downloaded from: http:///
max17582 dual-phase, quick-pwm controller for imvp-6.5 cpu core power supplies ______________________________________________________________________________________ 13 pin description pin name function 1 pgdin system power-good logic input. pgdin indicates the power status of other system rai ls and is used for power-supply sequencing. after power-up to the boot voltage, the output voltage remai ns at v boot , clken remains high, and pwrgd remains low as long as pgdin stays low. w hen pgdin is pulled high, the output transitions to the selected vid voltage, and clken is pulled low. if the system pulls pgdin low during normal operation, the max17582 immediately drives clken high, pulls pwrgd low, and slews the output to the boot voltage (using two-phase pulse-skipping mode). the controller remain s at the boot voltage until pgdin goes high again, shdn is toggled, or the v cc input power supply is cycled. 2 thrm input of internal comparator. connect the output of a resistor- and thermistor-divider (between v cc and gnd) to thrm. select the components such that the voltage at thrm falls b elow 1.5v (30% of v cc ) at the desired high temperature. 3 imon current-monitor output. the max17582 imon output sources a current that is directly p roportional to the current-sense voltage as defined by: i imon = g m(imon) x (v csp_ - v csn_ ) where g m(imon) = 5ms (typ). the imon current is unidirectional (sources current out of imon only) for positive current-sense values. for negative current-sense voltages, the imon current is zero. connect an external resistor between imon and gnds to create the desired imon gain based on the following equation: r imon = 0.9v/(imax x r sense(min) x g m(imon_min) ) where imax is defined in the crrent monitor section of the intel imvp-6.5 specification and based on discrete increments (20a, 30a, 40a, etc.), r sense(min) is the minimum effective value of the current- sense element (sense resistor or inductor dcr) that is used to provi de the current-sense voltage, and g m(imon_min) is the minimum transconductance amplifier gain as defined in the electrical characteristics table. the imon voltage is internally clamped to a maximum of 1.1v (typ). the transconductance amplifier and voltage clamp are internally compensated, so imon cannot dir ectly drive large capacitance values. to filter the imon signal, use an rc filter as shown i n figure 1. imon is pulled to ground when the max17582 is in shutdown. 4 ilim valley current-limit adjustment input. the valley current-limit threshold voltage at csp_ to csn_ equals precisely 1/10 of the differential time to ilim voltage over a 0.1v to 0.5v range (10mv to 50mv current-sense range). the negative current-limit threshold is nominally - 125% of the corresponding valley current-limit threshold. connect ilim directly to v cc to set the default current-limit threshold setting of 22.5mv (typ) nominal. 5 time slew-rate adjustment. time regulates to 2.0v and the load current determines the slew rate of the i nternal error-amplifier target. the sum of the resistance between time and gnd (r time ) determines the nominal slew-rate: slew rate = (12.5mv/s) x (71.5k /r time ) the guaranteed r time range is between 35.7k and 178k . this nominal slew rate applies to vid transitions and to the transition from boot mode to vid. if the vid dac inputs are clock ed, the slew rate for all other vid transitions is set by the rate at which they are clocked, up to a maximum slew rate equal to the nominal slew rate defined above. the startup and shutdown slew rates are always 1/8 of nominal slew rate in ord er to minimize surge currents. if slow is low, then the slew rate is reduced to 1/2 of nominal. 6, 14, 47 gnd analog ground 7 v cc controller analog bias supply voltage. connect to a 4.5v to 5.5v so urce. bypass to gnd with 1f minimum. 8 cci current-balance compensation. connect a 470pf capacitor between cci and the positive side of the feedback remote sense. cci is internally forced low in shutdown. downloaded from: http:///
max17582 dual-phase, quick-pwm controller for imvp-6.5 cpu core power supplies 14 ______________________________________________________________________________________ pin description (continued) pin name function 9 fb remote feedback-sense input. normally shorted to fbac and conne cted to the vcc_sense pin of the cpu socket through the load-line gain resistor (see the fbac pin desc ription). fb internally connects to the error amplifier and integrator. 10 fbac voltage-positioning transconductance amplifier output. connect a resistor r fb between fbac and the positive side of the feedback remote sense to set the dc steady- state droop based on the voltage- positioning gain requirement: r fb = r droop /(r sense x g m(fbac) ) where r droop is the desired voltage-positioning slope and g m(fbac) = 600s (typ). r sense is the value of the current-sense resistors that are used to provide the (csp_, csn_) current-sense voltages. if lossless sensing is used, r sense = r l . in this case, consider making r fb a resistor network that includes an ntc thermistor to minimize the temperature dependence of the vo ltage-positioning slope. fbac is high impedance in shutdown. 11 gnds remote ground-sense input. normally connected to the vss_sense pin o f the cpu socket. gnds internally connects to a transconductance amplifier that fine tunes the output voltagecompensating for voltage drops from the regulator ground to the load ground. 12, 24, 37 n.c. internally not connected 13 csn2 negative current-sense input for phase 2. connect csn2 to the negativ e terminal of the inductor current-sensing resistor or directly to the negative terminal of th e inductor if the lossless dcr sensing method is used (see figure 3). 15 csp2 positive current-sense input for phase 2. connect csp2 to the positive te rminal of the inductor current- sensing resistor or directly to the positive terminal of the fi ltering capacitor used when the lossless dcr sensing method is used (see figure 3). short csp2 to v cc for dedicated 1-phase operation. 16 shdn shutdown control input. this input cannot withstand the battery voltage. co nnect to v cc for normal operation. connect to ground to put the ic into its 1a max shutdown s tate. during startup, the output voltage is ramped up to the boot voltage slowly at a slew rate that is 1/8 t he slew rate set by the time resistor. during the transition from normal operation to shutdown, the outp ut voltage is ramped down at the same slow slew rate. forcing shdn to 11v~13v disables undervoltage protection, clears the fault latch, disables transient phase overlap, and disables the bst_ ch arging switches. do not connect shdn to > 13v. 17 dprslpvr pulse-skipping control input. this 1.0v logic input signal ind icates power usage and sets the operating mode of the max17582. when dprslpvr is forced high, the controller immediately ente rs the automatic pulse-skipping mode. the controller returns to forced-pwm mode when dprs lpvr is forced low and the output is in regulation. the pwrgd upper threshold is blanked durin g any downward output-voltage transition that occurs when the controller is in pulse-skipping mode, and stay s blanked until the transition- related pwrgd blanking period is complete and the output reaches regulation. the max17582 is in 2-phase pulse-skipping mode during startup an d while in boot mode, but is in forced-pwm mode during the transition from boot mode to vid mode plus 20s, and dur ing soft- shutdown, irrespective of the drpslpvr logic level. dprslpvr and psi together determine the operating mode and the number of active phases as shown in the following truth table: dprslpvr psi mode and phases 1 0 very low current (1-phase pulse skipping) 1 1 low current (approximately 3a) (1-phase pulse skipping) 0 0 intermediate power potential (1-phase pwm) 0 1 max power potential (2- or 1-phase pwm as configured at csp2) downloaded from: http:///
max17582 dual-phase, quick-pwm controller for imvp-6.5 cpu core power supplies ______________________________________________________________________________________ 15 pin description (continued) pin name function 18 psi power-state indicator input. dprslpvr and psi together determine the operating mode and the number of active phases as shown in the truth table included under the psi pin description. 19 ton switching frequency setting input. an external resistor between the input po wer source and ton sets the switching period (t sw = 1/f sw ) per phase according to the following equation: t sw = 16.3pf x (r ton + 6.5k ) ton becomes high impedance in shutdown to reduce the input qui escent current. if the ton current is less than 10a, the max17582 disables the controller, sets the ton open fault latch, and pulls dl_ and dh_ low. 20 v3p3 3.3v clken input supply. v3p3 input supplies the clken cmos push-pull logic output. connect to the systems standard 3.3v supply voltage before shdn is pulled high for proper imvp-6.5 operation. 21 clken clock enable push-pull logic output. this inverted logic output indicates wh en the output voltage sensed at fb is in regulation. during soft-start, shutdown, and when the fb is out of regu lation, the max17582 pulls clken up to v3p3. during vid transitions, the controller forces clken low. except during the power-up sequence, clken is the inverse of pwrgd. see the startp timing diagram (figure 9). when in pulse-skipping mode (dprslpvr high), the upper clken threshold is disabled. 22 pwrgd open-drain power-good output. after output-voltage transitions, except during power-up and power- down; if fb is in regulation then pwrgd is high impedance. during startup, pwrgd is held low and continues to be low whi le the part is in boot mode and until 5ms (typ) after clken goes low. pwrgd is forced low in shutdown. pwrgd is forced high impedance whenever the slew-rate controller is active (output-voltag e transitions). when in pulse-skipping mode (dprslpvr high), the upper pwrgd thre shold comparator is blanked during downward transitions. a pullup resistor on pwrgd causes additional finite shutdown curr ent. 23 phasegd phase-good current-balance open-drain output. used to sig nal the system that one of the two phases either has a fault condition or is not matched with the other. detection is done by identifying the need for a large on-time difference between phases in order to achieve or mo ve towards current balance. phasegd is low in shutdown. phasegd is forced high impedance whenever the slew-rate controlle r is active (output-voltage transitions). phasegd is forced high impedance while in 1-phase operation (dp rslpvr = high or psi = low). 25 bst2 boost flying-capacitor connection for phase 2. bst2 provides t he upper supply rail for the dh2 high- side gate driver. an internal switch between v dd and bst2 charges the flying capacitor while the low- side mosfet is on (dl2 pulled high and lx2 pulled to ground). 26 lx2 inductor connection for phase 2. lx2 is the internal lower supply rai l for the dh2 high-side gate driver. also used as an input to the controllers zero-crossing comparat or for phase 2. 27 dh2 high-side gate-driver output for phase 2. dh2 swings from lx2 to bst2. th e controller pulls dh2 low in shutdown. 28 pgnd2 power ground 29 dl2 low-side gate-driver output for phase 2. dl2 swings from gnd to v dd . dl2 is forced low in skip mode after detecting an inductor current zero crossing. dl2 is forced low during 1- phase operation ( psi = gnd or csp2 = v cc ). 30 vrhot open-drain output of internal comparator. vrhot is pulled low when the voltage at thrm goes below 1.5v (30% of v cc ). vrhot is high impedance in shutdown. 31 v dd driver supply voltage input. v dd is the supply voltage used to internally power the low-side gate drivers and refresh the bst_ flying capacitors during the off-times. connect v dd to the 4.5v to 5.5v system supply voltage. bypass v dd to the system power ground with a 1f each or greater ceramic capacitor. downloaded from: http:///
max17582 dual-phase, quick-pwm controller for imvp-6.5 cpu core power supplies 16 ______________________________________________________________________________________ pin description (continued) pin name function 32 dl1 low-side gate-driver output for phase 1. dl1 swings from gnd to v dd . dl1 is forced low after soft- shutdown or in skip mode after detecting an inductor current zero crossing. 33 pgnd1 power ground 34 dh1 high-side gate-driver output for phase 1. dh1 swings from lx1 to bst1. th e controller pulls dh1 low in shutdown. 35 lx1 inductor connection for phase 1. lx1 is the internal lower supply rai l for the dh1 high-side gate driver. also used as an input to the controllers zero-crossing comparat or for phase 1. 36 bst1 boost flying-capacitor connection for phase 1. bst1 provides t he upper supply rail for the dh1 high- side gate driver. an internal switch between v dd and bst1 charges the flying capacitor while the low- side mosfet is on (dl1 is pulled high and lx1 is pulled to ground). 38 slow imvp-6.5 slew-rate select input. this 1.0v logic input signal s elects between the nominal and slow (half of nominal rate) slew rates. when slow is forced high, the selected nominal slew rate is set by the time resistance as defined above. when slow is forced low, the slew rate is reduced to half the nominal slew rate. 39C45 d0Cd6 low-voltage vid dac code input. the d0Cd6 inputs do not have i nternal pullups. these 1.0v logic inputs are designed to interface directly with the cpu. the output voltage is set by the vid code indicated by the logic-level voltages on d0Cd6 (see table 4). 46 csp1 positive current-sense input for phase 1. connect csp1 to the positive te rminal of the inductor current- sensing resistor or directly to the positive terminal of the fi ltering capacitor used when the lossless dcr sensing method is used (see figure 3). 48 csn1 negative current-sense input for phase 1. connect csn1 to the negativ e terminal of the inductor current-sensing resistor or directly to the negative terminal of th e inductor if the lossless dcr sensing method is used (see figure 3). under v cc uvlo conditions and after soft-shutdown is completed, csn1 is inte rnally pulled to gnd through a 10 fet to discharge the output. ep exposed pad. internally connected to gnd. connect to the gr ound plane through a thermally enhanced via. detailed description table 1 lists the component selection for standardapplications. table 2 lists component suppliers for the max17582. free-running, constant-on-time pwm controller with input feed-forward the quick-pwm control architecture is a pseudo-fixed-frequency, constant-on-time, current-mode regulator with voltage feed-forward (figure 2). this architecture relies on the output filter capacitors esr to act as the current-sense resistor, so the output ripple voltage pro- vides the pwm ramp signal. the control algorithm is simple: the high-side switch on-time is determined sole-ly by a one-shot whose period is inversely proportional to input voltage and directly proportional to output volt- age, or the difference between the main and secondary inductor currents (see the on-time one-shot section). another one-shot sets a minimum off-time. the on-timeone-shot triggers when the error comparator goes low, the inductor current of the selected phase is below the valley current-limit threshold, and the minimum off-time one-shot times out. the controller maintains 180 out-of- phase operation by alternately triggering the main and secondary phases after the error comparator drops below the output-voltage set point. downloaded from: http:///
max17582 dual-phase, quick-pwm controller for imvp-6.5 cpu core power supplies ______________________________________________________________________________________ 17 design parameters imvp-6.5 auburndale sv core imvp-6.5 auburndale lv core circuit figure 1 figure 1 input-voltage range 7v to 20v 7v to 20v maximum load current (tdc current) 50a (37a) 28a (19a) transient load current 35a (10a/s) 23a (10a/s) load line -1.9mv/a -3mv/a components ton resistance (r ton ) 200k (f sw = 300khz) 200k (f sw = 300khz) inductance (l) nec/tokin mpc1055lr36 0.36h, 32a, 0.8m nec/tokin mpc1055lr36 0.36h, 32a, 0.8m high-side mosfet (n h ) siliconix 1x si4386dy 7.8m /9.5m (typ/max) siliconix 1x si4386dy 7.8m /9.5m (typ/max) low-side mosfet (n l ) siliconix 2x si4642dy 3.9m /4.7m (typ/max) siliconix 2x si4642dy 3.9m /4.7m (typ/max) output capacitors (c out ) 4x 330f, 6m , 2.5v panasonic eefsx0d0d331xr 28x 10f, 6v ceramic (0805) 3x 330f, 6m , 2.5v panasonic eefsx0d0d331xr 28x 10f, 6v ceramic (0805) input capacitors (c in ) 4x 10f, 25v ceramic (1210) 4x 10f, 25v ceramic (1210) time-ilim resistance (r1) 10k 10k ilim-gnd resistance (r2) 59k 59k fb resistance (r fb ) 4.02k 6.34k imon resistance 9.09k 18.2k lx_-csp_ resistance (r5) 1.21k 1.21k csp_-csn_ series resistance (r6) 1.50k 1.50k parallel ntc resistance 20k 20k dcr sense ntc (ntc1) 10k ntc b = 3380 tdk ntcg163jh103f 10k ntc b = 3380 tdk ntcg163jh103f dcr sense capacitance (c sense ) 2x 0.22f, 6v ceramic (0805) 2x 0.22f, 6v ceramic (0805) table 1. component selection for standard applications supplier website avx corp. www.avxcorp.com bi technologies www.bitechnologies.com central semiconductor corp. www.centralsemi.com fairchild semiconductor www.fairchildsemi.com international rectifier www.irf.com kemet corp www.kemet.com nec/tokin america, inc. www.nec-tokin.com panasonic corp. www.panasonic.com table 2. component suppliers supplier website pulse engineering www.pulseeng.com renesas technology corp. www.renesas.com sanyo electric co, ltd. www.sanyodevice.com siliconix (vishay) www.vishay.com sumida corp. www.sumida.com taiyo yuden www.t-yuden.com tdk corp. www.component.tdk.com toko america, inc. www.tokoam.com downloaded from: http:///
max17582 dual-phase, quick-pwm controller for imvp-6.5 cpu core power supplies 18 ______________________________________________________________________________________ max17582 c11.0 f c2 1.0 f 5v bias input agnd agnd c4 0.22 f c70.22 f c90.22 f r11 1.50k r1 12.1k r2 59.0k ntc1 10k b = 3380 r12 20k 7 v cc r ton 200k 19 ton r9 0 36 bst1 c in n hi shdn 16 dprslpvr 17 slow 38 psi 18 pgdin 1 d0 valley current limit set to ilimv limit = 0.2v x r1/(r1 + r2) slew rate set by time bias currentdv/dt = 12.5mv/ s x 71.5k /(r1 + r2) switching frequency (f sw = 1/t sw ): t sw = 16.3pf x (r ton + 6.5k ) 39 d1 40 d2 41 d3 42 d4 43 d5 44 d6 45 31 v dd pwr pwr pwr input 7v to 24v core output on off (vron) v3p3 20 phasegd 23 3.3v 1.1v v cc vss_sense vid inputs 34 dh1 35 lx1 c8 0.22 f c15 0.1 f r13 0 25 bst2 n lo n hi 32 dl1 33 pgnd1 l1 dcr thermal compensation d1 26 lx2 r101.21k pwr pwr n lo 29 dl2 l2 d1 27 dh2 r15 1.50k r16 20k ntc2 10k b = 3380 r141.21k r2225 r2325 48 csn1 c50.22 f c101000pf 46 csp1 agnd agnd agnd c6open 8 cci 15 csp2 c110.22 f 13 csn2 agnd c12open c out pwr c out pwr ilim 4 time 5 r6 13k thrm 2 r5 10k r4 1.9k r3 56 pwrgd 22 vrhot 30 clken 21 r7 1k r fb 4.02k 1% load-line adjustment:r fb = r droop /(r sense x 600 s) r20 10 r21 10 r8 9.09k imongnd 3 ntc3 100k b = 4250 gnd (ep) 6, 14, 47 fb 9 fbac 10 gnds 11 agnd c131000pf remote-sense filters agnd c14 1000pf vcc_sensevss_sense remote-senseinputs catch resistorsrequired when cpu not populated r19 10 28 pgnd2 figure 1. standard 2-phase imvp-6.5 (calpella) application circuit downloaded from: http:///
max17582 dual-phase, quick-pwm controller for imvp-6.5 cpu core power supplies ______________________________________________________________________________________ 19 sr q rs q trig q one-shot gnd dl1 bst1 dh1 lx1 ton csp1csn1 minimum off-time ilim gnd pwrgd 5ms startup delay target - 300mv target + 200mv ref (2.0v) 10x 10x shdn trig q one-shot phase 1 on-time csp2csn2 trig en2 q one-shot phase 2 on-time mode/phase/ slew-rate control fb (slow) pgdin v dd csp2 csn2csn1 csp1 cci fb blank qq t bst2 dh2 lx2 dl2 gnd lx1 1mv skip main phase drivers psi dprslpvr en2 slew skip g m (cci) 200k csp_csn_ g m(fb) d0?6 x2 csp_ csn_ g m(imon) x2 vrhot thrm 0.3 x v cc gnds phasegd current- balance fault gnd 60 s startup delay g m (cci) dac r-to-i converter pgdin fault target slew 5ms startup delay blank secondary phase drivers max17582 imon fbac clken max17582 v3p3 time v cc figure 2. functional diagram downloaded from: http:///
max17582 dual-phase, quick-pwm controller for imvp-6.5 cpu core power supplies 20 ______________________________________________________________________________________ dual 180 out-of-phase operation the two phases in the max17582 operate 180 out-of- phase to minimize input and output filtering requirements, reduce electromagnetic interference (emi), and improve efficiency. this effectively lowers component count reducing cost, board space, and component power requirementsmaking the max17582 ideal for high- power, cost-sensitive applications. typically, switching regulators provide power using only one phase instead of dividing the power among several phases. in these applications, the input capaci- tors must support high instantaneous current require- ments. the high rms ripple current can lower efficiency due to i 2 r power loss associated with the input capacitors effective series resistance (esr).therefore, the system typically requires several low- esr input capacitors in parallel to minimize input-volt- age ripple, to reduce esr-related power losses, and to meet the necessary rms ripple current rating. with the max17582, the controller shares the current between two phases that operate 180 out-of-phase, so the high-side mosfets never turn on simultaneously during normal operation. the instantaneous input cur- rent of either phase is effectively halved, resulting in reduced input-voltage ripple, esr power loss, and rms ripple current (see the input capacitor selection sec- tion). therefore, the same performance can beachieved with fewer or less-expensive input capacitors. +5v bias supply (v cc and v dd ) the quick-pwm controller requires an external +5vbias supply in addition to the battery. typically, this +5v bias supply is the notebooks 95% efficient +5v system supply. keeping the bias supply external to the ic improves efficiency and eliminates the cost associat- ed with the +5v linear regulator that would otherwise be needed to supply the pwm circuit and gate drivers. if stand-alone capability is needed, the +5v bias supply can be generated with an external linear regulator. the +5v bias supply must provide v cc (pwm con- troller) and v dd (gate-drive power), so the maximum current drawn is: i bias = i cc + f sw (q g(low) + q g(high) ) where i cc is provided in the electrical characteristics table, f sw is the switching frequency, and q g(low) and q g(high) are the mosfet data sheets total gate- charge specification limits at v gs = 5v. v in and v dd can be connected together if the input power source is a fixed +4.5v to +5.5v supply. if the +5v biassupply is powered up prior to the battery supply, the enable signal ( shdn going from low to high) must be delayed until the battery voltage is present to ensure startup. switching frequency (ton) connect a resistor (r ton ) between ton and v in to set the switching period t sw = 1/f sw , per phase: t sw = 16.3pf x (r ton + 6.5k ) a 96.75k to 303.25k corresponds to switching peri- ods of 167ns (600khz) to 500ns (200khz), respectively.high-frequency (600khz) operation optimizes the appli- cation for the smallest component size, trading off effi- ciency due to higher switching losses. this might be acceptable in ultra-portable devices where the load currents are lower and the controller is powered from a lower voltage supply. low-frequency (200khz) opera- tion offers the best overall efficiency at the expense of component size and board space. ton open-circuit protection the ton input includes open-circuit protection to avoidlong, uncontrolled on-times that could result in an over- voltage condition on the output. the max17582 detects an open-circuit fault if the ton current drops below10a for any reasonthe ton resistor (r ton ) is unpopulated, a high resistance value is used, the inputvoltage is low, etc. under these conditions, the max17582 stops switching (dh_ and dl_ pulled low) and immediately sets the fault latch. toggle shdn or cycle the v cc power supply below 0.5v to clear the fault latch and reactivate the controller. on-time one-shot the core of each phase contains a fast, low-jitter,adjustable one-shot that sets the high-side mosfets on-time. the one-shot for the main phase varies the on- time in response to the input and feedback voltages. the main high-side switch on-time is inversely propor- tional to the input voltage as measured by the ton input, and proportional to the feedback voltage (v fb ): where the switching period (t sw = 1/f sw ) is set by the resistor at the ton pin, and 0.075v is an approximationto accommodate the expected drop across the low- side mosfet switch. the one-shot for the secondary phase varies the on- time in response to the input voltage and the difference between the main and secondary inductor currents. two identical transconductance amplifiers integrate the difference between the master and slave current-sense signals. the summed output is internally connected to cci, allowing adjustment of the integration time con- stant with a compensation network connected between t tv v v on main sw fb in () . = + () 0 075 downloaded from: http:///
max17582 dual-phase, quick-pwm controller for imvp-6.5 cpu core power supplies ______________________________________________________________________________________ 21 cci and fb. the resulting compensation current andvoltage are determined by the following equations: i cci = g m (v csp1 - v csn1 ) - g m (v csp2 - v csn2 ) v cci = v fb + i cci z cci where z cci is the impedance at the cci output. the secondary on-time one-shot uses this integrated signal(v cci ) to set the secondary high-side mosfets on- time. when the main and secondary current-sense sig-nals (v cm = v csp1 - v csn1 and v cs = v csp2 - v csn2 ) become unbalanced, the transconductance amplifiersadjust the secondary on-time, which increases or decreases the secondary inductor current until the cur- rent-sense signals are properly balanced: this algorithm results in a nearly constant switching fre- quency and balanced inductor currents despite the lack of a fixed-frequency clock generator. the benefits of a constant switching frequency are twofold: first, the frequency can be selected to avoid noise-sensitive regions such as the 455khz if band; second, the inductor ripple-current operating point remains relative- ly constant, resulting in easy design methodology and predictable output-voltage ripple. the on-time one- shots have good accuracy at the operating points specified in the electrical characteristics table. on- times at operating points far removed from the condi-tions specified in the electrical characteristics table can vary over a wider range.on-times translate only roughly to switching frequen- cies. the on-times guaranteed in the electrical characteristics table are influenced by switching delays in the external high-side mosfet. resistivelosses, including the inductor, both mosfets, output capacitor esr, and pcb copper losses in the output and ground tend to raise the switching frequency at higher output currents. also, the dead-time effect increases the effective on-time, reducing the switching frequency. it occurs only during forced-pwm operation and dynamic output-voltage transitions when the induc- tor current reverses at light- or negative-load currents. with reversed inductor current, the inductors emf causes lx_ to go high earlier than normal, extendingthe on-time by a period equal to the dh_-rising dead time. for loads above the critical conduction point, where the dead-time effect is no longer a factor, the actual switching frequency (per phase) is: where v drop1 is the sum of the parasitic voltage drops in the inductor discharge path, including synchronous recti-fier, inductor, and pcb resistances; v drop2 is the sum of the parasitic voltage drops in the inductor charge path,including high-side switch, inductor, and pcb resis- tances; and t on is the on-time as determined above. current sense the output current of each phase is sensed. low-offsetamplifiers are used for current balance, voltage-posi- tioning gain, and current limit. sensing the current at the output of each phase offers advantages, including less noise sensitivity, more accurate current sharing between phases, and the flexibility of using either a cur- rent-sense resistor or the dc resistance of the output inductor. using the dc resistance (r dcr ) of the output inductor allows higher efficiency. in this configuration, the initialtolerance and temperature coefficient of the inductors dcr must be accounted for in the output-voltage droop-error budget and power monitor. this current- sense method uses an rc filtering network to extract the current information from the output inductor (see figure 3). the resistive divider used should provide a current-sense resistance (r cs ) low enough to meet the current-limit requirements, and the time constant of therc network should match the inductors time constant (l/r cs ): and:where r cs is the required current-sense resistance and r dcr is the inductors series dc resistance. r l crr cs eq =+ ? ? ? ? ? ? 1 1 1 2 r r rr r cs dcr = + ? ? ? ? ? ? 2 12 f vv tvv v sw out drop on in drop drop = + () + () 1 12 - tt vv v t v on sec sw cci in sw fb () . . = + ? ? ? ? ? ? = + 0 075 00 7 75v v t iz v in sw cci cci in ? ? ? ? ? ? + ? ? ? ? ? ? = main on-t time secondary current balance correctio () + nn () downloaded from: http:///
max17582 dual-phase, quick-pwm controller for imvp-6.5 cpu core power supplies 22 ______________________________________________________________________________________ use the worst-case inductance and r dcr values pro- vided by the inductor manufacturer, adding some mar-gin for the inductance drop over temperature and load. to minimize the current-sense error due to the current- sense inputs bias current (i csp _ and i csn _), choose r1||r2 to be less than 2k and use the previous equa- tion to determine the sense capacitance (c eq ). choose capacitors with 5% tolerance and resistors with 1% tol-erance specifications. temperature compensation is recommended for this current-sense method. see the voltage positioning and loop compensation section for detailed information.when using a current-sense resistor for accurate output- voltage positioning, the circuit requires a differential rc filter to eliminate the ac voltage step caused by the equivalent series inductance (l esl ) of the current-sense resistor (see figure 3). the esl induced-voltage stepdoes not affect the average current-sense voltage, but results in a significant peak current-sense voltage error that results in unwanted offsets in the regulation voltage and results in early current-limit detection. similar to the inductor dcr sensing method above, the rc filters time constant should match the l/r time constant formed by the current-sense resistors parasitic inductance: where l esl is the equivalent series inductance of the current-sense resistor, r sense is current-sense resis- tance value, and c eq and r1 are the time-constant matching components. l r cr esl sense eq = 1 a) output series resistor sensing dh_ input (v in ) dl_ lx_ pgnd c in n l n h d l csp_ csn_ l b) lossless inductor sensing dh_ input (v in ) dl_ lx_ pgnd c in n l n h d l csp_ csn_ c out inductor r1 c eq l r dcr sense resistor l esl r sense c out r1 c eq r2 r sense l sense c eq r1 = ( ) r dcr r1 + r2 r2 r cs = 11 r1 r2 c eq l r dcr = [ + ] for thermal compensation: r2 should consist of an ntc resistor in series with a standard thin-film resistor. max17582max17582 figure 3. current-sense methods downloaded from: http:///
current balance the max17582 integrates the difference between thecurrent-sense voltages and adjusts the on-time of the secondary phase to maintain current balance. the cur- rent balance now relies on the accuracy of the current- sense resistors instead of the inaccurate, thermally sensitive on-resistance of the low-side mosfets. with active current balancing, the current mismatch is deter- mined by the current-sense resistor values and the offset voltage of the transconductance amplifiers: where r sense is the effective sense resistance seen at the current-sense pins and v os(ibal) is the current-bal- ance offset specification in the electrical characteris- tics table. the worst-case current mismatch occurs immediatelyafter a load transient due to inductor value mismatches resulting in different di/dt for the two phases. the time it takes the current-balance loop to correct the transient imbalance depends on the mismatch between the inductor values and switching frequency. current limit the current-limit circuit employs a unique valley cur-rent-sensing algorithm that uses current-sense resistors between the current-sense inputs (csp_ to csn_) as the current-sensing elements. if the current-sense sig- nal of the selected phase is above the current-limit threshold, the pwm controller does not initiate a new cycle until the inductor current of the selected phase drops below the valley current-limit threshold. when either phase trips the current limit, both phases are effectively current limited since the interleaved con- troller does not initiate a cycle with either phase. since only the valley current is actively limited, the actu- al peak current is greater than the current-limit thresh- old by an amount equal to the inductor ripple current. therefore, the exact current-limit characteristic and maximum load capability are a function of the current- sense resistance, inductor value, and battery voltage. when combined with the undervoltage-protection cir- cuit, this current-limit method is effective in almost every circumstance. the positive valley current-limit threshold voltage atcsp_ to csn_ equals precisely 1/10 of the differential time to ilim voltage over a 0.1v to 0.5v range (10mv to 50mv current-sense range). connect ilim directly to v cc to set the default current-limit threshold setting of 22.5mv (typ).the negative current-limit threshold (forced-pwm mode only) is nominally -125% of the corresponding valley current-limit threshold. when the inductor current drops below the negative current limit, the controller immedi- ately activates an on-time pulsedl_ turns off and dh_ turns onallowing the inductor current to remain above the negative-current threshold. carefully observe the pcb layout guidelines to ensure that noise and dc errors do not corrupt the current-sense signals seen by the current-sense inputs (csp_, csn_). feedback adjustment amplifiers voltage-positioning amplifier (steady-state droop) the max17582 includes a transconductance amplifierfor adding gain to the voltage-positioning sense path. the amplifiers input is generated by summing the cur- rent-sense inputs, which differentially sense the voltage across either current-sense resistors or the inductors dcr. the amplifiers output connects directly to the reg- ulators voltage-positioned feedback input (fb), so the resistance between fb and the output-voltage sense point determines the voltage-positioning gain: v out = v target - r fb | fb where the target voltage (v target ) is defined in the nominal output-voltage selection section, and the fb amplifiers output current (i fb ) is determined by the sum of the current-sense voltages:where v cs = v csp_ - v csn_ is the differential current- sense voltage, and g m(fb) is typically 600s as defined in the electrical characteristics table. ig v fb m fb csx x ph = = () 1 iii v r os ibal lmain lsec os ibal sense () () == - max17582 dual-phase, quick-pwm controller for imvp-6.5 cpu core power supplies ______________________________________________________________________________________ 23 downloaded from: http:///
max17582 differential remote sense the max17582 includes differential, remote-senseinputs to eliminate the effects of voltage drops along the pcb traces and through the processors power pins. the feedback-sense node connects to the voltage-position- ing resistor (r fb ). the ground-sense (gnds) input con- nects to an amplifier that adds an offset directly to thetarget voltage, effectively adjusting the output voltage to counteract the voltage drop in the ground path. connect the voltage-positioning resistor (r fb ) and ground-sense (gnds) input directly to the processors remote-senseoutputs, as shown in figure 1. integrator amplifier an integrator amplifier forces the dc average of the fbvoltage to equal the target voltage. this transconduc- tance amplifier integrates the feedback voltage and pro- vides a fine adjustment to the regulation voltage (figure 2), allowing accurate dc output-voltage regulation regardless of the output ripple voltage. the integrator amplifier can shift the output voltage by 100mv (typ). the differential input-voltage range is at least 60mv total, including dc offset and ac ripple. the max17582 disables the integrator by connecting the amplifier inputs together at the beginning of all vid transitions done in pulse-skipping mode (dprslpvr = high). the integrator remains disabled until 20s after the transition is completed (the internal target settles) and the output is in regulation (edge detected on the error comparator). transient-overlap operation when a transient occurs, the response time of the con-troller depends on how quickly it can slew the inductor current. multiphase controllers that remain 180 out-of- phase when a transient occurs actually respond slower than an equivalent single-phase controller. to provide fast-transient response, the max17582 supports a phase-overlap mode, which allows the dual regulators to operate in-phase when heavy load transients are detected, effectively reducing the response time. after either high-side mosfet turns off, if the output voltage does not exceed the regulation voltage when the mini- mum off-time expires, the controller simultaneously turns on both high-side mosfets during the next on-time cycle. this maximizes the total inductor current slew rate. the phases remain overlapped until the out- put voltage exceeds the regulation voltage after the minimum off-time expires. after the phase-overlap mode ends, the controller automat- ically begins with the opposite phase. for example, if the secondary phase provided the last on-time pulse before overlap operation began, the controller starts switching with the main phase when overlap operation ends. table 3 is the operating mode truth table. nominal output-voltage selection the nominal no-load output voltage (v target ) is defined by the selected voltage reference (vid dac)plus the remote ground-sense adjustment (v gnds ) as defined in the following equation: v target = v fb = v dac + v gnds where v dac is the selected vid voltage. on startup, the max17582 slews the target voltage from ground to thepreset boot voltage. dac inputs (d0?6) the digital-to-analog converter (dac) programs the out-put voltage using the d0Cd6 inputs. d0Cd6 are low- voltage (1.0v) logic inputs, designed to interface directly with the cpu. do not leave d0Cd6 unconnected. changing d0Cd6 initiates a transition to a new output- voltage level. change d0Cd6 together, avoiding greater than 20ns skew between bits. otherwise, incorrect dac readings might cause a partial transition to the wrong volt- age level followed by the intended transition to the correct voltage level, lengthening the overall transition time. the available dac codes and resulting output voltages are compatible with the imvp-6.5 (table 4) specifications. dual-phase, quick-pwm controller for imvp-6.5 cpu core power supplies 24 ______________________________________________________________________________________ downloaded from: http:///
max17582 dual-phase, quick-pwm controller for imvp-6.5 cpu core power supplies ______________________________________________________________________________________ 25 inputs shdn slow dprslpvr psi phase operation* operating mode gnd x x x disabled low-power shutdown mode. dl1 and dl2 forced low, and the controller is disabled. the supply current drops to 1a (max). rising x x x multiphase pulse-skipping 1/8 r time slew rate startup/boot. when shdn is pulled high, the max17582 begins the startup sequence. the controller enables the pwm regulator and ramps the output voltage up to the boot voltage. see figure 9. high high low high multiphase forced-pwm nominal r time slew rate full power. the no-load output voltage is determined by the selected vid dac code (d0Cd6, table 4). high high low low 1-phase forced- pwm nominal r time slew rate intermediate power. the no-load output voltage is determined by the selected vid dac code (d0Cd6, table 4). when psi is pulled low, the max17582 immediately disables phase 2. dh2 and dl2 are pulled low. high high high x 1-phase pulse- skipping nominal r time slew rate deeper sleep mode. the no-load output voltage is determined by the selected vid dac code (d0Cd6, table 4). when dprslpvr is pulled high, the max17582 immediately enters 1-phase pulse-skipping operation, allowing automatic pwm/ pfm switchover under light loads. the pwrgd and clken upper thresholds are blanked during downward transitions. dh2 and dl2 are pulled low. high low high x 1-phase pulse- skipping deeper sleep slow exit mode. the no-load output voltage is determined by the selected vid dac code (d0Cd6, table 4). when slow is pulled low, the max17582 reduces its slew rate to 1/2 of normal. the pwrgd and clken upper thresholds are blanked. dh2 and dl2 are pulled low. falling x x x multiphase forced-pwm 1/8 r time slew rate shutdown. when shdn is pulled low, the max17582 immediately pulls pwrgd and phasegd low, clken becomes high, all enabled phases are activated, and the output voltage is ramped down to ground. once the output reaches 0v, the controller enters the low-power shutdown state. see figure 9. high x x x disabled fault mode. the fault latch has been set by the max17582 uvp or thermal-shutdown protection. the controller remains in fault mode until v cc power is cycled or shdn toggled. table 3. operating mode truth table *multiphase operationall enabled phases active. downloaded from: http:///
max17582 dual-phase, quick-pwm controller for imvp-6.5 cpu core power supplies 26 ______________________________________________________________________________________ d6 d5 d4 d3 d2 d1 d0 output voltage (v) d6 d5 d4 d3 d2 d1 d0 output voltage (v) 0 0 0 0 0 0 0 1.5000 1 0 0 0 0 0 0 0.7000 0 0 0 0 0 0 1 1.4875 1 0 0 0 0 0 1 0.6875 0 0 0 0 0 1 0 1.4750 1 0 0 0 0 1 0 0.6750 0 0 0 0 0 1 1 1.4625 1 0 0 0 0 1 1 0.6625 0 0 0 0 1 0 0 1.4500 1 0 0 0 1 0 0 0.6500 0 0 0 0 1 0 1 1.4375 1 0 0 0 1 0 1 0.6375 0 0 0 0 1 1 0 1.4250 1 0 0 0 1 1 0 0.6250 0 0 0 0 1 1 1 1.4125 1 0 0 0 1 1 1 0.6125 0 0 0 1 0 0 0 1.4000 1 0 0 1 0 0 0 0.6000 0 0 0 1 0 0 1 1.3875 1 0 0 1 0 0 1 0.5875 0 0 0 1 0 1 0 1.3750 1 0 0 1 0 1 0 0.5750 0 0 0 1 0 1 1 1.3625 1 0 0 1 0 1 1 0.5625 0 0 0 1 1 0 0 1.3500 1 0 0 1 1 0 0 0.5500 0 0 0 1 1 0 1 1.3375 1 0 0 1 1 0 1 0.5375 0 0 0 1 1 1 0 1.3250 1 0 0 1 1 1 0 0.5250 0 0 0 1 1 1 1 1.3125 1 0 0 1 1 1 1 0.5125 0 0 1 0 0 0 0 1.3000 1 0 1 0 0 0 0 0.5000 0 0 1 0 0 0 1 1.2875 1 0 1 0 0 0 1 0.4875 0 0 1 0 0 1 0 1.2750 1 0 1 0 0 1 0 0.4750 0 0 1 0 0 1 1 1.2625 1 0 1 0 0 1 1 0.4625 0 0 1 0 1 0 0 1.2500 1 0 1 0 1 0 0 0.4500 0 0 1 0 1 0 1 1.2375 1 0 1 0 1 0 1 0.4375 0 0 1 0 1 1 0 1.2250 1 0 1 0 1 1 0 0.4250 0 0 1 0 1 1 1 1.2125 1 0 1 0 1 1 1 0.4125 0 0 1 1 0 0 0 1.2000 1 0 1 1 0 0 0 0.4000 0 0 1 1 0 0 1 1.1875 1 0 1 1 0 0 1 0.3875 0 0 1 1 0 1 0 1.1750 1 0 1 1 0 1 0 0.3750 0 0 1 1 0 1 1 1.1625 1 0 1 1 0 1 1 0.3625 0 0 1 1 1 0 0 1.1500 1 0 1 1 1 0 0 0.3500 0 0 1 1 1 0 1 1.1375 1 0 1 1 1 0 1 0.3375 0 0 1 1 1 1 0 1.1250 1 0 1 1 1 1 0 0.3250 0 0 1 1 1 1 1 1.1125 1 0 1 1 1 1 1 0.3125 0 0 1 1 1 1 1 1.1125 1 0 1 1 1 1 1 0.3125 table 4. imvp-6.5 output-voltage vid dac codes note: the max17582 enters the shutdown sequence if the off code is set, forcing pwrgd and phasegd low and forcing clken high. exit from the off code follows the startup sequence. if the off code is present when shdn is pulled high, the max17582 remains off. downloaded from: http:///
max17582 dual-phase, quick-pwm controller for imvp-6.5 cpu core power supplies ______________________________________________________________________________________ 27 d6 d5 d4 d3 d2 d1 d0 output voltage (v) d6 d5 d4 d3 d2 d1 d0 output voltage (v) 0 1 0 0 0 0 0 1.1000 1 1 0 0 0 0 0 0.3000 0 1 0 0 0 0 1 1.0875 1 1 0 0 0 0 1 0.2875 0 1 0 0 0 1 0 1.0750 1 1 0 0 0 1 0 0.2750 0 1 0 0 0 1 1 1.0625 1 1 0 0 0 1 1 0.2625 0 1 0 0 1 0 0 1.0500 1 1 0 0 1 0 0 0.2500 0 1 0 0 1 0 1 1.0375 1 1 0 0 1 0 1 0.2375 0 1 0 0 1 1 0 1.0250 1 1 0 0 1 1 0 0.2250 0 1 0 0 1 1 1 1.0125 1 1 0 0 1 1 1 0.2125 0 1 0 1 0 0 0 1.0000 1 1 0 1 0 0 0 0.2000 0 1 0 1 0 0 1 0.9875 1 1 0 1 0 0 1 0.1875 0 1 0 1 0 1 0 0.9750 1 1 0 1 0 1 0 0.1750 0 1 0 1 0 1 1 0.9625 1 1 0 1 0 1 1 0.1625 0 1 0 1 1 0 0 0.9500 1 1 0 1 1 0 0 0.1500 0 1 0 1 1 0 1 0.9375 1 1 0 1 1 0 1 0.1375 0 1 0 1 1 1 0 0.9250 1 1 0 1 1 1 0 0.1250 0 1 0 1 1 1 1 0.9125 1 1 0 1 1 1 1 0.1125 0 1 1 0 0 0 0 0.9000 1 1 1 0 0 0 0 0.1000 0 1 1 0 0 0 1 0.8875 1 1 1 0 0 0 1 0.0875 0 1 1 0 0 1 0 0.8750 1 1 1 0 0 1 0 0.0750 0 1 1 0 0 1 1 0.8625 1 1 1 0 0 1 1 0.0625 0 1 1 0 1 0 0 0.8500 1 1 1 0 1 0 0 0.0500 0 1 1 0 1 0 1 0.8375 1 1 1 0 1 0 1 0.0375 0 1 1 0 1 1 0 0.8250 1 1 1 0 1 1 0 0.0250 0 1 1 0 1 1 1 0.8125 1 1 1 0 1 1 1 0.0125 0 1 1 1 0 0 0 0.8000 1 1 1 1 0 0 0 0 0 1 1 1 0 0 1 0.7875 1 1 1 1 0 0 1 0 0 1 1 1 0 1 0 0.7750 1 1 1 1 0 1 0 0 0 1 1 1 0 1 1 0.7625 1 1 1 1 0 1 1 0 0 1 1 1 1 0 0 0.7500 1 1 1 1 1 0 0 0 0 1 1 1 1 0 1 0.7375 1 1 1 1 1 0 1 0 0 1 1 1 1 1 0 0.7250 1 1 1 1 1 1 0 0 0 1 1 1 1 1 1 0.7125 1 1 1 1 1 1 1 off table 4. imvp-6.5 output-voltage vid dac codes (continued) note: the max17582 enters the shutdown sequence if the off code is set, forcing pwrgd and phasegd low and forcing clken high. exit from the off code follows the startup sequence. if the off code is present when shdn is pulled high, the max17582 remains off. downloaded from: http:///
max17582 dual-phase, quick-pwm controller for imvp-6.5 cpu core power supplies 28 ______________________________________________________________________________________ suspend mode when the processor enters low-power deeper sleepmode, the cpu sets the vid dac code to a lower out- put voltage and drives dprslpvr high. the max17582 responds by slewing the internal target voltage to the new dac code, switching to single-phase operation, and letting the output voltage gradually drift down to the deeper sleep voltage. during the transition, the max17582 blanks both the upper and lower pwrgd and clken thresholds until 20s after the internal tar- get reaches the deeper sleep voltage. once the 20stimer expires, the max17582 reenables the lower pwrgd and clken threshold, but keeps the upper threshold blanked until the output voltage reaches theregulation level. phasegd remains blanked high impedance while dprslpvr is high. output-voltage-transition timing the max17582 performs mode transitions in a con-trolled manner, automatically minimizing input surge cur- rents. this feature allows the circuit designer to achieve nearly ideal transitions, guaranteeing just-in-time arrival at the new output-voltage level with the lowest possible peak currents for a given output capacitance. at the beginning of an output-voltage transition, the max17582 blanks both pwrgd thresholds, preventing the pwrgd open-drain output from changing states during the transition. the controller enables the lower pwrgd threshold approximately 20s after the slew- rate controller reaches the target output voltage, but the upper pwrgd threshold remains blanked until the out- put voltage reaches the regulation level if the controller enters pulse-skipping operation. the slew rate (set by resistor r time ) must be set fast enough to ensure that the transition can be completed within the maximumallotted time. the max17582 automatically controls the current to the minimum level required to complete the transition in the calculated time. the slew-rate controller uses an inter- nal capacitor and current source programmed by r time to transition the output voltage. the total transi- tion time depends on r time , the voltage difference, and the accuracy of the slew-rate controller (c slew accura- cy). the slew rate is not dependent on the total outputcapacitance, as long as the surge current is less than the current limit. for all dynamic vid transitions, the transition time (t tran ) is given by: where dv target /dt = 12.5mv/s x 71.5k /r time is the slew rate, v old is the original output voltage, and v new is the new target voltage. see time slew rateaccuracy in the electrical characteristics for slew-rate limits. for soft-start and shutdown, the controller auto-matically reduces the slew rate to 1/8. the output voltage tracks the slewed target voltage, making the transitions relatively smooth. the average inductor current per phase required to make an output- voltage transition is: where dv target /dt is the required slew rate, c out is the total output capacitance, and total is the number of active phases. deeper sleep transitions when dprslpvr goes high, the max17582 immediatelydisables phase 2 (dh2 and dl2 forced low), blanks phasegd high impedance, and enters pulse-skipping operation (see figures 4 and 5). if the vids are set to a lower voltage setting, the output drops at a rate deter- mined by the load and the output capacitance. the inter- nal target still ramps as before, and pwrgd remains blanked high impedance until 20s after the output volt- age reaches the internal target. ? fast c4e deeper sleep exit: when exiting deeper sleep (dprslpvr pulled low) while the output volt-age still exceeds the deeper sleep voltage, the max17582 quickly slews (50mv/s min regardless of r time setting) the internal target voltage to the dac code provided by the processor as long as theoutput voltage is above the new target. the con- troller remains in skip mode until the output voltage equals the internal target. once the internal target reaches the output voltage, phase 2 is enabled. the controller blanks pwrgd, phasegd, and clken until 20s after the transition is completed. seefigure 4. i c dv dt l out total target ? () t vv dv dt tran new old target = - () downloaded from: http:///
max17582 dual-phase, quick-pwm controller for imvp-6.5 cpu core power supplies ______________________________________________________________________________________ 29 dprslpvr internal pwm control dh1 cpu core voltage internal target actual v out psi vid (d0?6) dh2 no pulses: v out > v target t blank 20 s typ t blank 20 s typ 1-phase skip (dh1 active, dh2 = dl2 = forced low) forced-pwm deeper sleep vid pwrgd phasegd clken blank low blank high threshold only blank high threshold only do not care (dprslpvr dominates state) blank high impedance blank high impedance blank high impedance (1-phase operation) blank low figure 4. c4e (c4 early exit) transition downloaded from: http:///
max17582 dual-phase, quick-pwm controller for imvp-6.5 cpu core power supplies 30 ______________________________________________________________________________________ dprslpvr internal pwm control dh1 cpu core voltage internal target actual v out psi vid (d0?6) active vid lfm viddprslp vid dh2 no pulses: v out > v target 1-phase skip (dh1 active, dh2 = dl2 = forced low) do not care (dprslpvr dominates state) 1-phase forced-pwm deeper sleep vid lfm vid pwrgd phasegd clken blank low blank high threshold only blank high threshold only blank high impedance blank low blank high impedance blank high impedance (1-phase operation) t blank 20 s typ t blank 20 s typ figure 5. standard c4 transition ? standard c4 deeper sleep exit: when exiting deeper sleep (dprslpvr pulled low) while the out-put voltage is regulating to the deeper sleep voltage, the max17582 immediately activates all enabled phases and ramps the output voltage to the lfm dac code provided by the processor at theslew rate set by r time . the controller blanks pwrgd, phasegd, and clken until 20s after the transition is completed. see figure 5. downloaded from: http:///
max17582 dual-phase, quick-pwm controller for imvp-6.5 cpu core power supplies ______________________________________________________________________________________ 31 pwrgd t blank 20 s typ internal pwm control cpu core voltage psi vid (d0?6) clken cpu freq cpu load phasegd t blank 20 s typ 32 switching cycles on dh2 blank low blank low blank high impedance blank high impedance 1-phase pwm blank high impedance 2-phase pwm 2-phase pwm figure 6. psi transition p p s s i i transitions when psi is pulled low, the max17582 immediately dis- ables phase 2 (dh2 and dl2 forced low), blanksphasegd high impedance, and enters single-phase pwm operation (see figure 6). when psi is pulled high, the max17582 enables phase 2. phasegd is blanked high impedance for 32 switching cycles on dh2, allow-ing sufficient time/cycles for phases 1 and 2 to achieve current balance. in a typical imvp-6.5 application, the vid is reduced by 1 lsb (12.5mv) when psi is pulled low, and is increased by 1 lsb when psi is pulled high. downloaded from: http:///
forced-pwm operation (normal mode) during soft-shutdown and normal operationwhen thecpu is actively running (dprslpvr = low)the max17582 operates with the low-noise, forced-pwm control scheme. forced-pwm operation disables the zero-crossing comparators of all active phases, forcing the low-side gate-drive waveforms to constantly be the complement of the high-side gate-drive waveforms. this keeps the switching frequency constant and allows the inductor current to reverse under light loads, pro- viding fast, accurate negative output-voltage transitions by quickly discharging the output capacitors. forced-pwm operation comes at a cost: the no-load 5v bias supply current remains between 10ma to 50ma per phase, depending on the external mosfets and switching frequency. to maintain high efficiency under light-load conditions, the processor can switch the con- troller to a low-power pulse-skipping control scheme after entering suspend mode. psi determines how many phases are active when operating in forced-pwm mode (dprslpvr = low).when psi is pulled low, the main phase remains active but the secondary phase is disabled (dh2 and dl2forced low). light-load pulse-skipping operation (deeper sleep) when dprslpvr is pulled high, the max17582 operateswith a single-phase pulse-skipping mode. the pulse- skipping mode enables the drivers zero-crossing com- parator, so the controller pulls dl1 low when it detects zero inductor current. this keeps the inductor from dis- charging the output capacitors and forces the controller to skip pulses under light-load conditions to avoid over- charging the output. the max17582 automatically uses forced-pwm operation during soft-shutdown, regardless of the dprslpvr and psi configuration. automatic pulse-skipping switchover in skip mode (dprslpvr = high), an inherent automaticswitchover to pfm takes place at light loads (figure 7). this switchover is affected by a comparator that trun- cates the low-side switch on-time at the inductor cur- rents zero crossing. the zero-crossing comparator senses the inductor current across the low-side mosfets. once v lx drops below the zero-crossing comparator threshold (see the electrical characteristics table), the comparator forces dl_ low. this mechanismcauses the threshold between pulse-skipping pfm and nonskipping pwm operation to coincide with the boundary between continuous and discontinuous inductor-current operation. the pfm/pwm crossoveroccurs when the load current of each phase is equal to 1/2 the peak-to-peak ripple current, which is a function of the inductor value (figure 7). for a battery input range of 7v to 20v, this threshold is relatively constant, with only a minor dependence on the input voltage due to the typically low duty cycles. the total load current at the pfm/pwm crossover threshold (i load(skip) ) is approximately:where total is the number of active phases. the switching waveforms might appear noisy and asyn-chronous when light loading activates pulse-skipping operation, but this is a normal operating condition that results in high light-load efficiency. trade-offs between pfm noise and light-load efficiency are made by vary- ing the inductor value. generally, low inductor values produce a broader efficiency vs. load curve, while higher values result in higher full-load efficiency (assuming that the coil resistance remains fixed) and less output-voltage ripple. penalties for using higher inductor values include larger physical size and degraded load-transient response, especially at low input-voltage levels. i tv l vv v load skip total sw out in out in () = ? ? ? ? ? ? - ?? ? ? ? ? ? max17582 dual-phase, quick-pwm controller for imvp-6.5 cpu core power supplies 32 ______________________________________________________________________________________ i peak i load = i peak /2 inductor current time 0 l v batt - v out t i on-time figure 7. pulse-skipping/discontinuous crossover point downloaded from: http:///
max17582 dual-phase, quick-pwm controller for imvp-6.5 cpu core power supplies ______________________________________________________________________________________ 33 power-up sequence (por, uvlo) the max17582 is enabled when shdn is driven high (figure 8). the internal reference powers up first. oncethe reference exceeds its uvlo threshold, the internal analog blocks are turned on and masked by a 50s one-shot delay. the pwm controller is then enabled. power-on reset (por) occurs when v cc rises above approximately 2v, resetting the fault latch and prepar-ing the controller for operation. the v cc uvlo circuitry inhibits switching until v cc rises above 4.25v. the con- troller powers up the reference once the systemenables the controller, v cc is above 4.25v, and shdn is driven high. with the reference in regulation, the con-troller ramps the output voltage to the boot voltage at 1/8 the slew rate set by r time : where dv target /dt = 12.5mv/s x 71.5k /r time is the slew rate. the soft-start circuitry does not use a variable current limit, so full output current is available immedi-ately. clken is pulled low approximately 60s after the max17582 reaches the boot voltage if pgdin is high.at the same time, the max17582 slews the output to the voltage set at the vid inputs at the programmed slew rate. pwrgd and phasegd become high impedance approximately 5ms after clken is pulled low. the max17582 automatically uses forced-pwm operationduring soft-start and soft-shutdown, regardless of the dprslpvr and psi configuration. for automatic startup, the battery voltage should bepresent before v cc . if the controller attempts to bring the output into regulation without the battery voltagepresent, the fault latch trips. the controller remains shut down until the fault latch is cleared by toggling shdn or cycling the v cc power supply below 0.5v. if the v cc voltage drops below 4.25v, the controller assumes that there is not enough supply voltage tomake valid decisions. to protect the output from over- voltage faults, the controller shuts down immediately and forces a high-impedance output. t v dv dt tran start boot target () = () 8 forced-pwm t blank 20 s typ t blank 60 s typ t blank 5ms typ t blank 60 s typ vid (d0?6) v core v boot pwrgd internal pwm control phasegd v cc soft-start = 1/8 slew rate set by r time shdn invalid code invalid code skip forced-pwm clken soft-shutdown = 1/8 slew rate set by r time figure 8. power-up and shutdown sequence timing diagram downloaded from: http:///
shutdown when shdn goes low, the max17582 enters low-power shutdown mode. pwrgd is pulled low immediately,and the output voltage ramps down at 1/8 the slew rate set by r time : where dv target /dt = 12.5mv/s x 71.5k /r time is the slew rate. slowly discharging the output capacitors byslewing the output over a long period of time keeps the average negative inductor current low (damped response), thereby eliminating the negative output-volt- age excursion that occurs when the controller dis- charges the output quickly by permanently turning on the low-side mosfet (underdamped response). this eliminates the need for the schottky diode normally con- nected between the output and ground to clamp the negative output-voltage excursion. after the controller reaches the zero target, the max17582 shuts down completelythe drivers are disabled (dl1 and dl2 dri- ven low) and the supply current drops below 1a. when a fault conditionoutput uvlo or thermal shut- downactivates the shutdown sequence, the protection circuitry sets the fault latch to prevent the controller from restarting. to clear the fault latch and reactivate the con- troller, toggle shdn or cycle v cc power below 0.5v. current monitor (imon) the max17582 includes a unidirectional transconduc-tance amplifier that sources current proportional to the positive current-sense voltage. the imon output cur- rent is defined by: i imon = g m(imon) x (v csp_ - v csn_ ) where g m(imon) = 2.4ms (typ) and the imon current is unidirectional (sources current out of imon only) forpositive current-sense values. for negative current- sense voltages, the imon current is zero. the current monitor allows the processor to accurately monitor the cpu load and quickly calculate the power dissipation to determine if the system is about to over- heat before the significantly slower temperature sensor signals an over-temperature alert. connect an external resistor between imon and gnds to create the desired imon gain based on the following equation: r imon = 0.9v/(imax x r sense(min) x g m(imon_min) ) where imax is defined in the current monitor section of the intel imvp-6.5 specification and based on discrete increments (10a, 20a, 30a, 40a, etc.), r sense(min) is the minimum effective value of the current-sense ele- ment (sense resistor or inductor dcr) that is used toprovide the current-sense voltage, and g m(imon _ min) is the minimum transconductance amplifier gain as defined in the electrical characteristics table. the imon voltage is internally clamped to a maximumof 1.1v (typ), preventing the imon output from exceed- ing the imon voltage rating even under overload or short-circuit conditions. when the controller is disabled, imon is pulled to ground. to filter the imon signal, use an rc filter as shown in figure 1. phase fault (phasegd) the max17582 includes a phase-fault output that signalsthe system that one of the two phases either has a fault condition or is not matched with the other. detection is done by identifying the need for a large on-time differ- ence between phases in order to achieve or move towards current balance. phasegd is high impedance when the controller oper- ates in 1-phase mode (dprslpvr high or psi low and dprslpvr low). on exit to 2-phase mode, phasegd isforced high impedance for 32 switching cycles on dh2. phasegd is low in shutdown. phasegd is forced high impedance whenever the slew-rate controller is active (output-voltage transitions). temperature comparator (vrhot) the max17582 also features an independent compara-tor with an accurate threshold (v hot ) that tracks the analog supply voltage (v hot = 0.3v cc ). this makes the thermal trip threshold independent of the v cc supply voltage tolerance. use a resistor- and thermistor-dividerbetween v cc and gnd to generate a voltage-regulator over-temperature monitor. place the thermistor as closeto the mosfets and inductors as possible. output undervoltage protection (uvp) the output uvp function is similar to foldback current lim-iting, but employs a timer rather than a variable current limit. if the max17582 output voltage is 400mv below the target voltage, the controller activates the shutdown sequence and sets the fault latch. once the controller ramps down to zero, it forces dl1 and dl2 high and pulls dh1 and dh2 low. toggle shdn or cycle the v cc power supply below 0.5v to clear the fault latch and reactivate the controller. uvp can be disabled through the no-fault test mode (see the no-fault test mode section). t v dv dt tran shdn out target () = () 8 max17582 dual-phase, quick-pwm controller for imvp-6.5 cpu core power supplies 34 ______________________________________________________________________________________ downloaded from: http:///
max17582 dual-phase, quick-pwm controller for imvp-6.5 cpu core power supplies ______________________________________________________________________________________ 35 thermal-fault protection the max17582 features a thermal-fault-protection cir-cuit. when the junction temperature rises above +160c, a thermal sensor sets the fault latch and acti- vates the soft-shutdown sequence. once the controller ramps down to zero, it forces dl1 and dl2 high and pulls dh1 and dh2 low. toggle shdn or cycle the v cc power supply below 0.5v to clear the fault latch andreactivate the controller after the junction temperature cools by 15c. thermal shutdown can be disabled through the no-fault test mode (see the no-fault test mode section). no-fault test mode the latched fault-protection features can complicate theprocess of debugging prototype breadboards since there are (at most) a few milliseconds in which to deter- mine what went wrong. therefore, a no-fault test mode is provided to disable the fault protectionundervoltage protection and thermal shutdown. additionally, the test mode clears the fault latch if it has been set. the no-fault test mode is entered by forcing 11v to 13v on shdn . mosfet gate drivers the dh_ and dl_ drivers are optimized for drivingmoderate-sized high-side and larger low-side power mosfets. this is consistent with the low duty factor seen in notebook applications, where a large v in - v out differential exists. the high-side gate drivers (dh_) source and sink 2.2a, and the low-side gate dri-vers (dl_) source 2.7a and sink 8a. this ensures robust gate drive for high-current applications. the dh_ floating high-side mosfet drivers are powered by internal boost switch charge pumps at bst_, while the dl_ synchronous-rectifier drivers are powered directly by the 5v bias supply (v dd ). adaptive dead-time circuits monitor the dl_ and dh_drivers and prevent either fet from turning on until the other is fully off. the adaptive driver dead time allows operation without shoot-through with a wide range of mosfets, minimizing delays and maintaining efficiency. there must be a low-resistance, low-inductance path from the dl_ and dh_ drivers to the mosfet gates for the adaptive dead-time circuits to work properly; other- wise, the sense circuitry in the max17582 interprets the mosfet gates as off while charge actually remains. use very short, wide traces (50 mils to 100 mils wide if the mosfet is 1in from the driver). the internal pulldown transistor that drives dl_ low isrobust, with a 0.25 (typ) on-resistance. this helps prevent dl_ from being pulled up due to capacitivecoupling from the drain to the gate of the low-side mosfets when the inductor node (lx_) quickly switches from ground to v in . applications with high input voltages and long inductive driver traces mightrequire that rising lx_ edges do not pull up the low- side mosfets gate, causing shoot-through currents. the capacitive coupling between lx_ and dl_ created by the mosfets gate-to-drain capacitance (c rss ), gate-to-source capacitance (c iss - c rss ), and addi- tional board parasitics should not exceed the followingminimum threshold: typically, adding a 4700pf capacitor between dl_ and power ground (c nl in figure 9), close to the low-side mosfets, greatly reduces coupling. do not exceed22nf of total gate capacitance to prevent excessive turn-off delays. vv c c gs th in rss iss () > ? ? ? ? ? ? bst_ dh_ lx_ (r bst_ )* input (v in ) c bst_ n h c byp l (r bst_ )* optional?he resistor lowers emi by decreasing the switching node rise time. (c nl )* optional?he capacitor reduces lx_ to dl_ capacitive coupling that can cause shoot-through currents. dl_ pgnd n l (c nl )* v dd figure 9. gate drive circuit downloaded from: http:///
alternatively, shoot-through currents can be caused bya combination of fast high-side mosfets and slow low- side mosfets. if the turn-off delay time of the low-side mosfets is too long, the high-side mosfets can turn on before the low-side mosfets have actually turned off. adding a resistor less than 5 in series with bst_ slows down the high-side mosfet turn-on time, elimi-nating the shoot-through currents without degrading the turn-off time (r bst_ in figure 9). slowing down the high-side mosfet also reduces the lx_ node rise time,thereby reducing emi and high-frequency coupling responsible for switching noise. multiphase quick-pwm design procedure firmly establish the input-voltage range and maximumload current before choosing a switching frequency and inductor operating point (ripple-current ratio). the primary design trade-off lies in choosing a good switch- ing frequency and inductor operating point, and the fol- lowing four factors dictate the rest of the design: ? input-voltage range: the maximum value (v in(max) ) must accommodate the worst-case high ac adapter voltage. the minimum value (v in(min) ) must account for the lowest input voltage after dropsdue to connectors, fuses, and battery selector switches. if there is a choice at all, lower input volt- ages result in better efficiency. ? maximum load current: there are two values to consider. the peak load current (i load(max) ) deter- mines the instantaneous component stresses and fil-tering requirements, and thus drives output capacitor selection, inductor saturation rating, and the design of the current-limit circuit. the continuous load current (i load ) determines the thermal stress- es and thus drives the selection of input capacitors,mosfets, and other critical heat-contributing com- ponents. modern notebook cpus generally exhibit i load = i load(max) x 80%. ? for multiphase systems, each phase supports afraction of the load, depending on the current bal- ancing. when properly balanced, the load current is evenly distributed among each phase: where total is the total number of active phases. ? switching frequency: this choice determines the basic trade-off between size and efficiency. theoptimal frequency is largely a function of maximum input voltage, due to mosfet switching losses that are proportional to frequency and v in 2 . the opti- mum frequency is also a moving target due to rapidimprovements in mosfet technology that are mak- ing higher frequencies more practical. ? inductor operating point: this choice provides trade-offs between size vs. efficiency and transientresponse vs. output noise. low inductor values pro- vide better transient response and smaller physical size, but also result in lower efficiency and higher output noise due to increased ripple current. the minimum practical inductor value is one that causes the circuit to operate at the edge of critical conduc- tion (where the inductor current just touches zero with every cycle at maximum load). inductor values lower than this grant no further size-reduction bene- fit. the optimum operating point is usually found between 20% and 50% ripple current. inductor selection the switching frequency and operating point (% ripplecurrent or lir) determine the inductor value as follows: where total is the total number of phases. find a low-loss inductor having the lowest possible dcresistance that fits in the allotted dimensions. ferrite cores are often the best choice, although powdered iron is inexpensive and can work well at 200khz. the core must be large enough not to saturate at the peak inductor current (i peak ): transient response the inductor ripple current impacts transient-responseperformance, especially at low v in - v out differentials. low inductor values allow the inductor current to slewfaster, replenishing charge removed from the output fil- ter capacitors by a sudden load step. the amount of output sag is also a function of the maximum duty fac- tor, which can be calculated from the on-time and mini- mum off-time. for a dual-phase controller, the worst-case output sag voltage can be determined by: i i lir peak load max total = ? ? ? ? ? ? + ? ? ? ? ? ? () 1 2 l vv fi lir v v total in out sw load max out = ? ? ? ? ? ? - () i in ? ? ? ? ? ? i i load phase load total () = max17582 dual-phase, quick-pwm controller for imvp-6.5 cpu core power supplies 36 ______________________________________________________________________________________ downloaded from: http:///
max17582 dual-phase, quick-pwm controller for imvp-6.5 cpu core power supplies ______________________________________________________________________________________ 37 where t off(min) is the minimum off-time (see the electrical characteristics table). the amount of overshoot due to stored inductor energy can be calculated as:where total is the total number of active phases. setting the current limit the minimum current-limit threshold must be highenough to support the maximum load current when the current limit is at the minimum tolerance value. the val- ley of the inductor current occurs at i load(max) minus half the ripple current, therefore:where total is the total number of active phases, and i limit(low) equals the minimum current-limit threshold voltage divided by the current-sense resistor (r sense ). output capacitor selection the output filter capacitor must have low-enough esrto meet output ripple and load-transient requirements, yet have high enough esr to satisfy stability require- ments. in cpu v core converters and other applications where the output is subject to large-load transients, the outputcapacitors size typically depends on how much esr is needed to prevent the output from dipping too low under a load transient. ignoring the sag due to finite capacitance: in non-cpu applications, the output capacitors size often depends on how much esr is needed to maintain an acceptable level of output ripple voltage. the output ripple voltage of a step-down controller equals the totalinductor ripple current multiplied by the output capaci- tors esr. when operating multiphase systems out-of- phase, the peak inductor currents of each phase are staggered, resulting in lower output ripple voltage by reducing the total inductor ripple current. for multi- phase operation, the maximum esr to meet ripple requirements is: where total is the total number of active phases, and f sw is the switching frequency per phase. the actual capacitance value required relates to the physical sizeneeded to achieve low esr, as well as to the chemistry of the capacitor technology. thus, the capacitor is usu- ally selected by esr and voltage rating rather than by capacitance value (this is true of polymer types). when using low-capacity ceramic filter capacitors, capacitor size is usually determined by the capacity needed to prevent v sag and v soar from causing problems during load transients. generally, onceenough capacitance is added to meet the overshoot requirement, undershoot at the rising load edge is no longer a problem (see the v sag and v soar equations in the transient response section). output capacitor stability considerations for quick-pwm controllers, stability is determined bythe value of the esr zero relative to the switching fre- quency. the boundary of instability is given by the fol- lowing equation: where: and: r eff = r esr + r droop + r pcb where c out is the total output capacitance, r esr is the total equivalent series resistance, r droop is the volt- age-positioning gain, and r pcb is the parasitic board resistance between the output capacitors and senseresistors. f rc esr eff out = 1 2 f f esr sw r vf l vv v v esr in sw in total out out ri () ? ? ? ? ? ? ? ? - p pple rr v i esr pcb step load max + () () i i lir limit low load max total () () > ? ? ? ? ? ? ? ? ? 1 2 - ?? ? ? v il cv soar load max total out out () () 2 2 v vt v t sag out sw in off = () ? ? ? ? ? ? + li load(max) 2 ( m min out out in out sw in cv vv t v ) ? ? ? ? ? ? () ? ? ? ? ? ? 2 2- - -2 2 t c vt off min out out () ? ? ? ? ? ? ? ? + i load(max) s sw in off min v t ? ? ? ? ? ? + ? ? ? ? ? ? ? ? () downloaded from: http:///
for a standard 300khz application, the esr zero fre-quency must be well below 95khz, preferably below 50khz. tantalum, sanyo poscap, and panasonic sp capacitors in widespread use at the time of publication have typical esr zero frequencies below 50khz. in the standard application circuit, the esr needed to support a 30mv p-p ripple is 30mv/(40a x 0.3) = 2.5m . four 330f/2.5v panasonic sp (type sx) capacitors in paral-lel provide 1.5m (max) esr. with a 2m droop and 0.5m pcb resistance, the typical combined esr results in a zero at 30khz.ceramic capacitors have a high-esr zero frequency, but applications with significant voltage positioning can take advantage of their size and low esr. do not put high-value ceramic capacitors directly across the out- put without verifying that the circuit contains enough voltage positioning and series pcb resistance to ensure stability. when only using ceramic output capacitors, output overshoot (v soar ) typically deter- mines the minimum output capacitance requirement.their relatively low capacitance value can cause output overshoot when stepping from full-load to no-load con- ditions, unless a small inductor value is used (high switching frequency) to minimize the energy transferred from inductor to capacitor during load-step recovery. unstable operation manifests itself in two related but distinctly different ways: double pulsing and feedback- loop instability. double pulsing occurs due to noise on the output or because the esr is so low that there is not enough voltage ramp in the output-voltage signal. this fools the error comparator into triggering a new cycle immediately after the minimum off-time period has expired. double pulsing is more annoying than harmful, resulting in nothing worse than increased output ripple. however, it can indicate the possible presence of loop instability due to insufficient esr. loop instability can result in oscillations at the output after line or load steps. such perturbations are usually damped, but can cause the output voltage to rise above or fall below the tolerance limits. the easiest method for checking stability is to apply a very fast zero-to-max load transient and carefully observe the output-voltage-ripple envelope for over- shoot and ringing. it can help to simultaneously monitor the inductor current with an ac current probe. do not allow more than one cycle of ringing after the initial step-response under/overshoot. input capacitor selection the input capacitor must meet the ripple currentrequirement (i rms ) imposed by the switching currents. the multiphase quick-pwm controllers operate out-of-phase while the quick-pwm slave controllers provide selectable out-of-phase or in-phase on-time triggering. out-of-phase operation reduces the rms input current by dividing the input current between several stag- gered stages. for duty cycles less than 100%/ outph per phase, the i rms requirements can be determined by the following equation:where total is the total number of out-of-phase switching regulators. the worst-case rms currentrequirement occurs when operating with v in = 2 total v out . at this point, the above equation simpli- fies to i rms = 0.5 x i load / total . for most applications, nontantalum chemistries (ceram-ic, aluminum, or os-con) are preferred due to their resistance to inrush surge currents typical of systems with a mechanical switch or connector in series with the input. if the quick-pwm controller is operated as the second stage of a two-stage power-conversion system, tantalum input capacitors are acceptable. in either con- figuration, choose an input capacitor that exhibits less than +10c temperature rise at the rms input current for optimal circuit longevity. power-mosfet selection most of the following mosfet guidelines focus on thechallenge of obtaining high load-current capability when using high-voltage (> 20v) ac adapters. low- current applications usually require less attention. the high-side mosfet (n h ) must be able to dissipate the resistive losses plus the switching losses at bothv in(min) and v in(max) . calculate both these sums. ideally, the losses at v in(min) should be approximately equal to losses at v in(max) , with lower losses in between. if the losses at v in(min) are significantly high- er than the losses at v in(max) , consider increasing the size of n h (reducing r ds(on) but with higher c gate ). conversely, if the losses at v in(max) are significantly higher than the losses at v in(min) , consider reducing the size of n h (increasing r ds(on) to lower c gate ). if v in does not vary over a wide range, the minimum power dissipation occurs where the resistive lossesequal the switching losses. i i v vv rms load total in total out in tot = ? ? ? ? ? ? ? - a al out v () max17582 dual-phase, quick-pwm controller for imvp-6.5 cpu core power supplies 38 ______________________________________________________________________________________ downloaded from: http:///
max17582 dual-phase, quick-pwm controller for imvp-6.5 cpu core power supplies ______________________________________________________________________________________ 39 choose a low-side mosfet that has the lowest possibleon-resistance (r ds(on) ), comes in a moderate-sized package (i.e., one or two 8-pin sos, dpak, or d 2 pak), and is reasonably priced. make sure that the dl_ gatedriver can supply sufficient current to support the gate charge and the current injected into the parasitic gate- to-drain capacitor caused by the high-side mosfet turning on; otherwise, cross-conduction problems might occur (see the mosfet gate drivers section). mosfet power dissipation worst-case conduction losses occur at the duty factorextremes. for the high-side mosfet (n h ), the worst- case power dissipation due to resistance occurs at theminimum input voltage: where total is the total number of phases. generally, a small high-side mosfet is desired toreduce switching losses at high input voltages. however, the r ds(on) required to stay within package power dissipation often limits how small the mosfetcan be. again, the optimum occurs when the switching losses equal the conduction (r ds(on) ) losses. high- side switching losses do not usually become an issueuntil the input is greater than approximately 15v. calculating the power dissipation in high-side mosfet (n h ) due to switching losses is difficult since it must allow for difficult quantifying factors that influence theturn-on and turn-off times. these factors include the internal gate resistance, gate charge, threshold volt- age, source inductance, and pcb layout characteris- tics. the following switching-loss calculation provides only a very rough estimate and is no substitute for breadboard evaluation, preferably including verification using a thermocouple mounted on n h : where c oss is the n h mosfets output capacitance, q g(sw) is the charge needed to turn on the n h mosfet, and i gate is the peak gate-drive source/sink current (2.2a typ).switching losses in the high-side mosfet can become an insidious heat problem when maximum ac adapter voltages are applied due to the squared term in the c x v in 2 x ? sw switching-loss equation. if the high-side mosfet chosen for adequate r ds(on) at low-battery voltages becomes extraordinarily hot when biased fromv in(max) , consider choosing another mosfet with lower parasitic capacitance.for the low-side mosfet (n l ), the worst-case power dissipation always occurs at maximum input voltage:the worst case for mosfet power dissipation occurs under heavy overloads that are greater than i load(max) , but are not quite high enough to exceed the current limit and cause the fault latch to trip. to pro-tect against this possibility, you can over design the cir- cuit to tolerate: where i valley(max) is the maximum valley current allowed by the current-limit circuit, including thresholdtolerance and on-resistance variation. the mosfets must have a good-size heatsink to handle the overload power dissipation. choose a schottky diode (d l ) with a forward voltage low enough to prevent the low-side mosfet bodydiode from turning on during the dead time. select a diode that can handle the load current per phase dur- ing the dead times. this diode is optional and can be removed if efficiency is not critical. boost capacitors the boost capacitors (c bst_ ) must be selected large enough to handle the gate-charging requirements ofthe high-side mosfets. typically, 0.1f ceramic capacitors work well for low-power applications driving medium-sized mosfets. however, high-current appli- cations driving large, high-side mosfets require boost capacitors larger than 0.1f. for these applications, select the boost capacitors to avoid discharging the capacitor more than 200mv while charging the high- side mosfets gates: where n is the number of high-side mosfets used for one regulator, and q gate is the gate charge specified in the mosfets data sheet. for example, assume (2)irf7811w n-channel mosfets are used on the high c nq mv bst gate _ = 200 ii i load total valley max inductor =+ ? ? ? ? ? ? () 2 () () =+ total valley max load max i i l lir 2 ? ? ? ? ? ? pd n sistive v v l out in max (re ) () = ? ? ? ? ? ? ? ? ? 1- ?? ? ? ? ? ? ? ? ? ? ? i r load total ds on 2 () pd n switching vif h in max load sw total () () = ? ?? ? ? ? ? ? ? ? ? ? ? + q i cvf gsw gate oss in sw () 2 2 pd n sistive v v i h out in load tota (re ) = ? ? ? ? ? ? ll ds on r ? ? ? ? ? ? 2 () downloaded from: http:///
side. according to the manufacturers data sheet, a sin-gle irf7811w has a maximum gate charge of 24nc (v gs = 5v). using the above equation, the required boost capacitance would be:selecting the closest standard value, this example requires a 0.22f ceramic capacitor. current-balance compensation (cci) the current-balance compensation capacitor (c cci ) integrates the difference between the main and sec-ondary current-sense voltages. the internal compensa- tion resistor (r cci = 200k ) improves transient response by increasing the phase margin. this allowsthe dynamics of the current-balance loop to be opti- mized. excessively large capacitor values increase the integration time constant, resulting in larger current dif- ferences between the phases during transients. excessively small capacitor values allow the current loop to respond cycle-by-cycle, but can result in small dc current variations between the phases. for most applications, a 470pf capacitor from cci to the switch- ing regulators output works well. connecting the compensation network to the output (v out ) allows the controller to feed-forward the output- voltage signal, especially during transients. voltage positioning and loop compensation voltage positioning dynamically lowers the output volt-age in response to the load current, reducing the out- put capacitance and processors power-dissipation requirements. the controller uses a transconductance amplifier to set the transient and dc output-voltage droop (figure 2) as a function of the load. this adjusta- bility allows flexibility in the selected current-sense resistor value or inductor dcr, and allows smaller cur- rent-sense resistance to be used, reducing the overall power dissipated. steady-state voltage positioning connect a resistor (r fb ) between fb and v out to set the dc steady-state droop (load line) based on therequired voltage-positioning slope (r droop ): where the effective current-sense resistance (r sense ) depends on the current-sense method (see the current sense section), and the voltage-positioning amplifiers transconductance (g m(fb) ) is typically 600s as defined in the electrical characteristics table. the con- troller sums together the input signals of the current-sense inputs (csp_, csn_). when the inductors dcr is used as the current-sense element (r sense = r dcr ), each current-sense input should include an ntc thermistor to minimize the tem-perature dependence of the voltage-positioning slope. minimum input-voltage requirements and dropout performance the output-voltage-adjustable range for continuous-conduction operation is restricted by the nonadjustable minimum off-time one-shot and the number of phases. for best dropout performance, use the slower (200khz) on-time settings. when working with low input voltages, the duty-factor limit must be calculated using worst- case values for on- and off-times. manufacturing toler- ances and internal propagation delays introduce an error to the on-times. this error is greater at higher fre- quencies. also, keep in mind that transient-response performance of buck regulators operated too close to dropout is poor, and bulk output capacitance must often be added (see the v sag equation in the multiphase quick-pwm design procedure section). the absolute point of dropout is when the inductor cur-rent ramps down during the minimum off-time ( i down ) as much as it ramps up during the on-time ( i up ). the ratio h = i up / i down is an indicator of the ability to slew the inductor current higher in response toincreased load, and must always be greater than 1. as h approaches 1, the absolute minimum dropout point, the inductor current cannot increase as much during each switching cycle and v sag greatly increases unless additional output capacitance is used.a reasonable minimum value for h is 1.5, but adjusting this up or down allows trade-offs between v sag , output capacitance, and minimum operating voltage. for agiven value of h, the minimum operating voltage can be calculated as: where total is the total number of out-of-phase switching regulators, v fb is the voltage-positioning droop, v drop1 and v drop2 are the parasitic voltage drops in the discharge and charge paths (see the on- time one-shot section), and t off(min) is from the electrical characteristics table. the absolute minimum input voltage is calculated with h = 1. v vv v ht in min total fb droop drop total () = + - - 1 1 o off min sw drop drop droop f vvv () ? ? ? ? ? ? ? ? + + 21 - r r rg fb droop sense m fb = () c nc mv f bst_ . = = 224 200 024 max17582 dual-phase, quick-pwm controller for imvp-6.5 cpu core power supplies 40 ______________________________________________________________________________________ downloaded from: http:///
max17582 dual-phase, quick-pwm controller for imvp-6.5 cpu core power supplies ______________________________________________________________________________________ 41 if the calculated v in(min) is greater than the required minimum input voltage, then reduce the operating fre-quency or add output capacitance to obtain an accept- able v sag . if operation near dropout is anticipated, calculate v sag to be sure of adequate transient response.dropout design example: v fb = 1.4v f sw = 300khz t off(min) = 400ns v droop = 3mv/a x 30a = 90mv v drop1 = v drop2 = 150mv (30a load) h = 1.5 and total = 2: calculating again with h = 1 gives the absolute limit ofdropout: therefore, v in must be greater than 4.1v, even with very large output capacitance, and a practical input voltagewith reasonable output capacitance would be 5.0v. applications information pcb layout guidelines careful pcb layout is critical to achieve low switchinglosses and clean, stable operation. the switching power stage requires particular attention. if possible, mount all the power components on the top side of the board with their ground terminals flush against one another. refer to the max17582 evaluation kit specifi- cation for a layout example and follow these guidelines for good pcb layout: ? keep the high-current paths short, especially at the ground terminals. this is essential for stable, jitter-free operation. ? connect all analog grounds to a separate solid cop- per plane, which connects to the gnd pin of thequick-pwm controller. this includes the v cc , fb, and gnds bypass capacitors. ? keep the power traces and load connections short. this is essential for high efficiency. the use of thick copper pcbs (2oz vs. 1oz) can enhance full-loadefficiency by 1% or more. correctly routing pcb traces is a difficult task that must be approached in terms of fractions of centimeters, where a single m of excess trace resistance causes a measurableefficiency penalty. ? keep the high-current, gate-driver traces (dl_, dh_, lx_, and bst_) short and wide to minimizetrace resistance and inductance. this is essential for high-power mosfets that require low-imped- ance gate drivers to avoid shoot-through currents. ? csp_ and csn_ connections for current limiting and voltage positioning must be made using kelvin-sense connections to guarantee the current-sense accuracy. ? when trade-offs in trace lengths must be made, it is preferable to allow the inductor charging path to bemade longer than the discharge path. for example, it is better to allow some extra distance between the input capacitors and the high-side mosfet than to allow distance between the inductor and the low- side mosfet or between the inductor and the out- put filter capacitor. ? route high-speed switching nodes away from sen- sitive analog areas (cci, fb, csp_, csn_, etc.). layout procedure 1) place the power components first, with ground ter- minals adjacent (low-side mosfet source, c in , c out , and d1 anode). if possible, make all these connections on the top layer with wide, copper-filled areas. 2) mount the controller ic adjacent to the low-side mosfet. the dl_ gate traces must be short andwide (50 mils to 100 mils wide if the mosfet is 1in from the controller ic). 3) group the gate-drive components (bst_ diodes and capacitors, v dd bypass capacitor) together near the controller ic. 4) make the dc-dc controller ground connections as shown in figure 1. this diagram can be viewed ashaving four separate ground planes: input/output ground, where all the high-power components go; the power ground plane, where the gnd pin and v dd bypass capacitor go; the masters analog ground plane, where sensitive analog componentsgo, and the masters gnd pin and v cc bypass capacitor go; and the slaves analog ground plane,where the slaves gnd pin and v cc bypass capaci- tor go. the masters gnd plane must meet the gndplane only at a single point directly beneath the ic. v vm v m v s in min () . (. . = + 2 1 4 90 150 1 2 04 10 - - 3 300 150 150 90 4 07 khz mv mv mv v ) . ? ? ? ? ? ? + += - v vm v m v s in min () . (. . = + 2 1 4 90 150 1 2 04 15 - - 3 300 150 150 90 4 96 khz mv mv mv v ) . ? ? ? ? ? ? + += - downloaded from: http:///
max17582 dual-phase, quick-pwm controller for imvp-6.5 cpu core power supplies maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim product. no circuit patent licenses are implied. maxim reserves the right to change the circuitry and specifications without notice at any time. 42 ____________________maxim integrated products, 120 san gabriel drive, sunnyvale, ca 94086 408-737-7600 ? 2009 maxim integrated products maxim is a registered trademark of maxim integrated products, inc. similarly, the slaves gnd plane must meet thegnd plane only at a single point directly beneath the ic. the respective master and slave ground planes should connect to the high-power output ground with a short metal trace from gnd to the source of the low-side mosfet (the middle of the star ground). this point must also be very close to the output capacitor ground terminal. 5) connect the output power planes (v core and sys- tem ground planes) directly to the output filtercapacitor positive and negative terminals with multi- ple vias. place the entire dc-dc converter circuit as close to the cpu as is practical. package information for the latest package outline information and land patterns, goto www.maxim-ic.com/packages . package type package code document no. 48 tqfn-ep t4866+2 21-014 1 chip information process: bicmos downloaded from: http:///

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