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max9266 hdcp gigabit multimedia serial link deserializer with lvds system interface _________________________________________________________________ maxim integrated products 1 19-5800; rev 0; 3/11 for related parts and recommended products to use with this part, refer to: www.maxim-ic.com/max9266.related blu-ray is a trademark of blu-ray disc association. ordering information appears at end of data sheet. general description the max9266 gigabit multimedia serial link (gmsl) deserializer features an lvds system interface and high- bandwidth digital content protection (hdcp) decryption for content protection of dvd and blu-ray k video and audio data. the deserializer pairs with any hdcp-gmsl serializer to form a digital serial link for the transmission of control data and hdcp-encrypted video and audio data. gmsl is an interface approved by digital content protection, llc (dcp). the deserializer features 3-channel and 4-channel modes. the 3-channel mode outputs three lanes of lvds data (21 bits), uart control signals, and three audio outputs. the 4-channel mode outputs four lanes of lvds data (28 bits), uart control signals, three audio outputs, and auxiliary control signals. the three audio outputs are for i 2 s audio, supporting an 8khz to 192khz sampling frequency and a sample depth of 4 to 32 bits. the embedded control channel forms a full-duplex differ- ential 9.6kbps to 1mbps uart link between the serializer and the deserializer. an electronic control unit (ecu) or microcontroller ( f c) can be located on the serializer side of the link (typical for video display), on the deserializer side of the link (typical for image sensing), or on both sides. the control channel enables ecu/ f c control of peripherals on the remote side, providing such functions as backlight control, touch-screen input, and hdcp- related operations. the serial link signaling is ac-coupled current-mode logic (cml) with scrambled 8b/10b coding. for driving longer cables, gmsl serializers have programmable pre/ deemphasis, and the deserializer has a programmable channel equalizer. for reduced emi, the deserializer has programmable spread spectrum on the lvds and con- trol outputs. the serial link inputs and the lvds output meet iso 10605 and iec 61000-4-2 esd standards. the deserializer?s core supply is 3.3v and the i/o supply is 1.8v to 3.3v. the device is available in a 48-pin tqfp package with an exposed pad and is specified over the -40 n c to +105 n c automotive temperature range. features s hdcp encryption enable/disable programmable through control channel s control channel handles all hdcp protocol transactions?separate control bus not required s hdcp keys preprogrammed in secure on-chip nonvolatile memory s 2.5gbps payload data rate (3.125gbps with overhead) s ac-coupled serial link with scrambled 8b/10b line coding s 8.33mhz to 104mhz (3-channel lvds) or 6.25mhz to 78mhz (4-channel lvds) pixel clock s 4-bit to 32-bit word length, 8khz to 192khz i 2 s audio channel supports high-definition audio s embedded half-/full-duplex bidirectional control channel s 9.6kbps to 1mbps base mode and bypass mode s interrupt supports touch-screen displays s remote-end i 2 c master for peripherals s programmable channel equalizer for 15m cable drive at 3.125gbps s programmable spread spectrum on serial outputs reduces emi s serial-data clock recovery eliminates external reference clock s auto data-rate detection allows on-the-fly data- rate change s built-in prbs checker for ber testing of the serial link s iso 10605 and iec 61000-4-2 esd tolerance applications high-resolution automotive navigation rear-seat infotainment e v a l u a t i o n k i t a v a i l a b l e for pricing, delivery, and ordering information, please contact maxim direct at 1-888-629-4642, or visit maxim?s website at www.maxim-ic.com. downloaded from: http:///
_________________________________________________________________ maxim integrated products 2 max9266 hdcp gigabit multimedia serial link deserializer with lvds system interface avdd to agnd ....................................................-0.5v to +3.9v dvdd to gnd ......................................................-0.5v to +3.9v iovdd to gnd .....................................................-0.5v to +3.9v any ground to any ground .................................-0.5v to +0.5v in+, in- to agnd .................................................-0.5v to +1.9v txout_, txclkout_ to agnd ..........................-0.5v to +3.9v all other pins to gnd ......................... -0.5v to (v iovdd + 0.5v) txout_, txclkout_ short circuit to agnd or avdd ..................................................continuous continuous power dissipation (t a = +70 n c) 48-pin tqfp (derate 36.2mw/ n c above +70 n c) ....2898.6mw operating temperature range ........................ -40 n c to +105 n c junction temperature .....................................................+150 n c storage temperature range ............................ -65 n c to +150 n c lead temperature (soldering, 10s) ................................+300 n c soldering temperature (reflow) ......................................+260 n c junction-to-case thermal resistance ( b jc ) ....................2 n c/w junction-to-ambient thermal resistance ( b ja ) ...........27.6 n c/w absolute maximum ratings note 1: package thermal resistances were obtained using the method described in jedec specification jesd51-7, using a four- layer board. for detailed information on package thermal considerations, refer to www.maxim-ic.com/thermal-tutorial . stresses beyond those listed under ?absolute maximu m ratings? may cause permanent damage to the device . these are stress ratings only, and functional ope ra- tion of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. package thermal characteristics (note 1) dc electrical characteristics (v avdd = v dvdd = 3.0v to 3.6v, v iovdd = 1.7v to 3.6v, r l = 100 q 1% (differential), t a = -40 n c to +105 n c, unless otherwise noted. typical values are at v avdd = v dvdd = v ovdd = 3.3v, t a = +25 n c.) parameter symbol conditions min typ max units single-ended inputs (bws, int, cds, eqs, ms, pwdn , ssen, drs) high-level input voltage v ih1 0.65 x v iovdd v low-level input voltage v il1 0.35 x v iovdd v input current i in1 v in = 0v to v iovdd -10 +10 f a input clamp voltage v cl i cl = -18ma -1.5 v single-ended outputs (ws, sck, sd/cntl0, cntl1, cntl2/mclk) high-level output voltage v oh1 i out = -2ma dcs = 0 v iovdd - 0.3 v dcs = 1 v iovdd - 0.2 low-level output voltage v ol1 i out = 2ma dcs = 0 0.3 v dcs = 1 0.2 output short-circuit current i os v out = v gnd , dcs = 0 v iovdd = 3.0v to 3.6v 15 25 39 ma v iovdd = 1.7v to 1.9v 3 7 13 v out = v gnd , dcs = 1 v iovdd = 3.0v to 3.6v 20 35 63 v iovdd = 1.7v to 1.9v 5 10 21 * the parametric values (min, typ, max limits) shown in the electrical characteristics table supersede v alues quoted elsewhere in this data sheet. downloaded from: http:///
_________________________________________________________________ maxim integrated products 3 max9266 hdcp gigabit multimedia serial link deserializer with lvds system interface dc electrical characteristics* (continued) (v avdd = v dvdd = 3.0v to 3.6v, v iovdd = 1.7v to 3.6v, r l = 100 q 1% (differential), t a = -40 n c to +105 n c, unless otherwise noted. typical values are at v avdd = v dvdd = v ovdd = 3.3v, t a = +25 n c.) parameter symbol conditions min typ max units i 2 c and uart i/o, open-drain outputs (rx/sda, tx/scl, lock, err , gpio_) high-level input voltage v ih2 0.7 x v iovdd v low-level input voltage v il2 0.3 x v iovdd v input current i in2 v in = 0v to v iovdd (note 2) rx/sda, tx/scl -110 +1 f a lock, err , gpio_ -80 +1 low-level output voltage v ol2 i out = 3ma v iovdd = 1.7v to 1.9v 0.4 v v iovdd = 3.0v to 3.6v 0.3 differential output for reverse control channel (in+, in-) differential high output peak voltage, (v in+ ) - (v in- ) v roh no high-speed data transmission (figure 1) 30 60 mv differential low output peak voltage, (v in+ ) - (v in- ) v rol no high-speed data transmission (figure 1) -60 -30 mv differential inputs (in+, in-) differential high input threshold (peak) voltage, (v in+ ) - (v in- ) v idh(p) figure 2 40 90 mv differential low input threshold (peak) voltage, (v in+ ) - (v in- ) v idl(p) figure 2 -90 -40 mv input common-mode voltage ((v in+ ) + (v in- ))/2 v cmr 1 1.3 1.6 v differential input resistance (internal) r i 80 100 130 i three-level logic inputs (add0, add1) high-level input voltage v ih 0.7 x v iovdd v low-level input voltage v il 0.3 x v iovdd v midlevel input current i inm add0 and add1 open or connected to a driver with output in high impedance (note 3) -10 +10 f a input current i in add0 and add1 = high or low, pwdn = high or low -150 +150 f a input clamp voltage v cl i cl = -18ma -1.5 v lvds outputs (txout__, txclkout_) differential output voltage v od figure 3 250 450 mv change in v od between complementary output states d v od figure 3 25 mv * the parametric values (min, typ, max limits) shown in the electrical characteristics table supersede v alues quoted elsewhere in this data sheet. downloaded from: http:///
_________________________________________________________________ maxim integrated products 4 max9266 hdcp gigabit multimedia serial link deserializer with lvds system interface dc electrical characteristics* (continued) (v avdd = v dvdd = 3.0v to 3.6v, v iovdd = 1.7v to 3.6v, r l = 100 q 1% (differential), t a = -40 n c to +105 n c, unless otherwise noted. typical values are at v avdd = v dvdd = v ovdd = 3.3v, t a = +25 n c.) parameter symbol conditions min typ max units output offset voltage v os figure 3 1.125 1.375 v change in v os between complementary output states d v os figure 3 25 mv output short-circuit current i os v out = 0v or 3.6v 3.5ma lvds output -7.5 +7.5 ma 7ma lvds output -15 +15 magnitude of differential output short-circuit current i osd 3.5ma lvds output 7.5 ma 7ma lvds output 15 output high-impedance current i oz add0 and add1 = high or low, pwdn = high or low -0.5 +0.5 f a power supply worst-case supply current (figure 4) (note 4) i wcs bws = low, f txclkout_ = 16.6mhz 149 190 ma bws = low, f txclkout_ = 33.3mhz 159 212 bws = low, f txclkout_ = 66.6mhz 190 255 bws = low, f txclkout_ = 104mhz 228 295 sleep-mode supply current i ccs 80 248 f a power-down current i ccz pwdn = gnd 25 178 f a esd protection in+, in- v esd human body model, r d = 1.5k i , c s = 100pf (note 5) q 8 kv iec 61000-4-2, r d = 330 i , c s = 150pf (note 6) contact discharge q 10 air-gap discharge q 12 iso 10605, r d = 2k i , c s = 330pf (note 6) contact discharge q 8 air-gap discharge q 15 tx0ut_, txclkout_ v esd human body model, r d = 1.5k i , c s = 100pf (note 5) q 8 kv iec 61000-4-2, r d = 330 i , c s = 150pf (note 6) contact discharge q 8 air-gap discharge q 20 iso 10605, r d = 2k i , c s = 330pf (note 6) contact discharge q 8 air-gap discharge q 30 all other pins v esd human body model, r d = 1.5k i , c s = 100pf (note 5) q 4 kv * the parametric values (min, typ, max limits) shown in the electrical characteristics table supersede v alues quoted elsewhere in this data sheet. downloaded from: http:///
_________________________________________________________________ maxim integrated products 5 max9266 hdcp gigabit multimedia serial link deserializer with lvds system interface ac electrical characteristics (v avdd = v dvdd = 3.0v to 3.6v, v iovdd = 1.7v to 3.6v, r l = 100 q 1% (differential), t a = -40 n c to +105 n c, unless otherwise noted. typical values are at v avdd = v dvdd = v ovdd = 3.3v, t a = +25 n c.) parameter symbol conditions min typ max units lvds clock outputs (txclkout+, txclkout-) clock frequency f txclkout_ bws = gnd, v drs = v iovdd 8.33 16.66 mhz bws = gnd, drs = gnd 16.66 104 v bws = v iovdd , v drs = v iovdd 6.25 12.5 v bws = v iovdd , drs = gnd 12.5 78 i 2 c/uart port timing output rise time t r 30% to 70%, c l = 10pf to 100pf, 1k i pullup to iovdd (figure 5) 20 150 ns output fall time t f 70% to 30%, c l = 10pf to 100pf, 1k i pullup to iovdd (figure 5) 20 150 ns input setup time t set i 2 c only (figure 5) (note 7) 100 ns input hold time t hold i 2 c only (figure 5) (note 7) 0 ns switching characteristics (note 7) cntl_ output rise-and-fall time t r , t f 20% to 80%, c l = 10pf, dcs = 1 (figure 6) v iovdd = 1.7v to 1.9v 0.5 3.1 ns v iovdd = 3.0v to 3.6v 0.3 2.2 20% to 80%, c l = 5pf, dcs = 0 (figure 6) v iovdd = 1.7v to 1.9v 0.6 3.8 v iovdd = 3.0v to 3.6v 0.4 2.4 lvds output rise time t r 20% to 80%, r l = 100 i (figure 3) 200 350 ps lvds output fall time t f 80% to 20%, r l = 100 i (figure 3) 200 350 ps lvds output pulse position t pposn n = 0 to 6, t clk = 1/f txclkout_ , f txclkout_ = 104mhz (figure 7) f txclkout_ = 12.5mhz n/7 x t clk - 250 n/7 x t clk n/7 x t clk + 250 ps f txclkout_ = 33mhz n/7 x t clk - 200 n/7 x t clk n/7 x t clk + 200 f txclkout_ = 78mhz n/7 x t clk - 125 n/7 x t clk n/7 x t clk + 125 f txclkout_ = 104mhz n/7 x t clk - 100 n/7 x t clk n/7 x t clk + 100 lvds output enable time t lven from the last bit of the enable uart packet to v os = 1125mv 100 f s lvds output disable time t lvds from the last bit of the enable uart packet to v os = 0v 100 f s deserializer delay t sd figure 8 (note 8) 3660 bits reverse control-channel output rise time t r no forward-channel data transmission (figure 1) 180 400 ns reverse control-channel output fall time t f no forward-channel data transmission (figure 1) 180 400 ns lock time t lock figure 9 3.6 ms power-up time t pu figure 10 9.4 ms * the parametric values (min, typ, max limits) shown in the electrical characteristics table supersede v alues quoted elsewhere in this data sheet. downloaded from: http:///
_________________________________________________________________ maxim integrated products 6 max9266 hdcp gigabit multimedia serial link deserializer with lvds system interface ac electrical characteristics* (continued) (v avdd = v dvdd = 3.0v to 3.6v, v iovdd = 1.7v to 3.6v, r l = 100 q 1% (differential), t a = -40 n c to +105 n c, unless otherwise noted. typical values are at v avdd = v dvdd = v ovdd = 3.3v, t a = +25 n c.) note 2: minimum i in due to voltage drop across the internal pullup resistor. note 3: to provide a midlevel, leave the input unconnected, or, if driven, put driver in high impedance. high-impedance leakage current must be less than q 10 f a. note 4: hdcp enabled. note 5: tested terminal to all grounds. note 6: tested terminal to agnd. note 7: guaranteed by design and not production tested. note 8: measured in cml bit times. bit time = 1/(30 x f txclkout_ ) for bws = gnd. bit time = 1/(40 x f txclkout_ ) for v bws = v iovdd . parameter symbol conditions min typ max units i 2 s output timing (note 7) ws jitter t aj-ws t ws = 1/f ws , rising (falling) edge to falling (rising) edge (note 5) f ws = 48khz or 44.1khz 0.4e -3 x t ws 0.5e -3 x t ws ns f ws = 96khz 0.8e -3 x t ws 1e -3 x t ws f ws = 192khz 1.6e -3 x t ws 2e -3 x t ws sck jitter t aj-sck t sck = 1/f sck , rising edge to rising edge n ws = 16 bits, f ws = 48khz or 44.1khz 13e -3 x t sck 16e -3 x t sck ns n ws = 24 bits, f ws = 96khz 39e -3 x t sck 48e -3 x t sck n ws = 32 bits, f ws = 192khz 0.1 x t sck 0.13 x t sck audio skew relative to video t ask video and audio synchronized 3 x t ws 4 x t ws f s sck, sd, ws rise-and-fall time t r, t f 20% to 80% c l = 10pf, dcs = 1 0.3 3.1 ns c l = 5pf, dcs = 0 0.4 3.8 sd, ws valid time before sck t dvb t sck = 1/f sck (figure 11) 0.35 x t sck 0.5 x t sck ns sd, ws valid time after sck t dva t sck = 1/f sck (figure 11) 0.35 x t sck 0.5 x t sck ns * the parametric values (min, typ, max limits) shown in the electrical characteristics table supersede v alues quoted elsewhere in this data sheet. downloaded from: http:///
_________________________________________________________________ maxim integrated products 7 max9266 hdcp gigabit multimedia serial link deserializer with lvds system interface typical operating characteristics (v avdd = v dvdd = v iovdd = 3.3v, t a = +25 n c, unless otherwise noted.) max9266 toc01 total supply current (ma) 150 160 170 180 190 200 210 220140 txclkout_ frequency (mhz) 85 65 45 25 5 105 prbs pattern, hdcp onall equalizer modes all spread modes total supply current vs. txclkout_ frequency (3-channel mode) max9266 toc02 txclkout_ frequency (mhz) total supply current (ma) 65 50 35 20 150 160 170 180 190 200 210140 5 80 total supply current vs. txclkout_ frequency (4-channel mode) prbs pattern, hdcp onall equalizer modes all spread modes output power spectrum vs. txclkout_ frequency (various spread) max9266 toc03 txclkout_ frequency (mhz) 34.5 33.5 32.5 31.5 30.5 35.5 output power spectrum (dbm) -80 -70 -60 -50 -40 -30 -20 -10 0 10 -90 f txclkout_ = 33mhz 2% spread 4% spread 0% spread max9266 toc04 txclkout_ frequency (mhz) 69 67 65 63 -80 -70 -60 -50 -40 -30 -20 -10 0 -90 61 71 output power spectrum vs. txclkout_ frequency (various spread) output power spectrum (dbm) f txclkout_ = 66mhz 2% spread 4% spread 0% spread maximum txclkout_ frequency vs. stp cable length (ber < 10 -9 ) max9266 toc05 stp cable length (m) maximum txclkout_ frequency (mhz) 15 10 5 20 40 60 80 100 120 0 0 20 optimumpe/eq settings no pe, 10.7dbequalization no pe, 5.2db equalization ber can be as low as 10 -12 for cable lengths less than 10m max9266 toc06 additional differential load capacitance (pf) 8 6 4 2 0 10 maximum txclkout_ frequency vs. additional differential c l (ber < 10 -9 ) maximum txclkout_ frequency (mhz) 20 40 60 80 100 120 0 optimumpe/eq settings no pe, 10.7dbequalization 10m stp cable ber can be as low as 10 -12 for c l < 4pf for optimum pe/eq settings no pe, 5.2db equalization downloaded from: http:///
_________________________________________________________________ maxim integrated products 8 max9266 hdcp gigabit multimedia serial link deserializer with lvds system interface pin description pin configuration pin name function 1 bws bus-width select. bws requires external pulldown or pullup resistor. set bws = low for 3-channel mode. set bws = high for 4-channel mode. 2 int interrupt input. int requires external pullup or pulldown resistor. a transition on the deserializer?s int input toggles the gmsl serializer?s int output. 3 cds control direction selection. control link direction selection input requires external pulldown or pullup resistor. set cds = high for uart connection of a f c as control-channel master. set cds = low for peripheral connection as a control-channel i 2 c or uart slave. 4 gpio0 general-purpose i/o 0. open-drain gpio with internal 60k i pullup resistor to iovdd. gpio0 is high impedance during power-up and when pwdn = low. 5, 23, 32, 47 avdd 3.3v analog power supply. bypass avdd to agnd with 0.1 f f and 0.001 f f capacitors as close as possible to the device with the smaller capacitor closest to avdd. 6, 7 in+, in- differential cml input +/- . differential inputs of the serial link. 8, 24, 31, 37, 48 agnd analog ground tqfp top view + 11 1098765432 12 1 max9266 gpio0 avdd in+ in- agnd eqs gpio1 dvdd gnd bws int cds 33 32 31 30 29 28 27 26 25 ep 36 35 34 agndavdd gnd iovdd cntl2/mclk cntl1 sd/cntl0 sck ws pwdn tx/scl rx/sda agnd gnd iovdd add0add1 lock err ms ssen drs avdd agnd 3738 39 40 41 42 43 44 45 46 47 48 2423 22 21 20 19 18 17 16 15 14 13 txout1+avdd agnd txout2- txout2+ txclkout- txclkout+ txout3- txout3+ txout0-txout0+ txout1- downloaded from: http:///
_________________________________________________________________ maxim integrated products 9 max9266 hdcp gigabit multimedia serial link deserializer with lvds system interface pin description (continued) pin name function 9 eqs equalizer select input. eqs requires external pulldown or pullup resistor. the state of eqs latches upon power-up or when resuming from power-down mode ( pwdn = low). set eqs = low for 10.7db equalizer boost (eqtune = 1001). set eqs = high for 5.2db equalizer boost (eqtune = 0100). 10 gpio1 general-purpose i/o 1. open-drain gpio with an internal 60k i pullup resistor to iovdd. gpio1 is high impedance during power-up and when pwdn = low. 11 dvdd 3.3v digital power supply. bypass dvdd to dgnd with 0.1 f f and 0.001 f f capacitors as close as possible to the device with the smaller capacitor closest to dvdd. 12, 22, 38 gnd digital and i/o ground 13 rx/sda receive/serial data. uart receive or i 2 c serial-data input/output with internal 30k i pullup to iovdd. in uart mode, rx/sda is the rx input of the deserializer?s uart. in i 2 c mode, rx/sda is the sda input/output of the deserializer?s i 2 c master. rx/sda has an open-drain driver and requires a pullup resistor. 14 tx/scl transmit/serial clock. uart transmit or i 2 c serial-clock output with internal 30k i pullup to iovdd. in uart mode, tx/scl is the tx output of the deserializer?s uart. in i 2 c mode, tx/scl is the scl output of the deserializer?s i 2 c master. tx/scl is an open-drain driver and requires a pullup resistor. 15 pwdn active-low, power-down input. pwdn requires external pulldown or pullup resistor. 16 ws i 2 s word-select output 17 sck i 2 s serial-clock output 18 sd/cntl0 i 2 s serial-data output/control output 0. disable i 2 s to use sd/cntl0 as an additional control output. sd/cntl0 is encrypted when hdcp is enabled. 19 cntl1 control output 1. cntl1 is active in 3-channel mode and remains low. to use cntl1, set bws = high (4-channel mode) and set discntl = 0. cntl1 is mapped from dout27. cntl1 is not encrypted when hdcp is enabled (see table 3). 20 cntl2/mclk control output 2/data output 28/mclk. cntl2/mclk is not active in 3-channel mode and remains low. to use cntl2/mclk, set bws = high (4-channel mode). cntl2/mclk is not encrypted when hdcp is enabled (see table 3). cntl2/mclk can be used to output mclk (see the additional mclk output for audio applications section). 21, 39 iovdd i/o supply voltage. 1.8v to 3.3v logic i/o power supply. bypass iovdd to gnd with 0.1 f f and 0.001 f f capacitors as close as possible to the device with the smaller capacitor closest to iovdd. 25, 26, 29, 30, 33?36 txout_+, txout_- differential lvds data outputs. set bws = low (3-channel mode) to use txout0_ to txout2_. set bws = high (4-channel mode) to use txout0_ to txout3_. 27, 28 txclkout+, txclkout- differential lvds output for the lvds clock 40 add0 address selection input 0. three-level input to select the deserializer?s device address (see table 2). the state of add0 latches upon power-up or when resuming from power-down mode ( pwdn = low). downloaded from: http:///
________________________________________________________________ maxim integrated products 10 max9266 hdcp gigabit multimedia serial link deserializer with lvds system interface pin description (continued) pin name function 41 add1 address selection input 1. three-level input to select the deserializer?s device address (see table 2). the state of add1 latches upon power-up or when resuming from power-down mode ( pwdn = low). 42 lock open-drain lock output with internal 60k i pullup to iovdd. lock = high indicates that plls are locked with correct serial-word-boundary alignment. lock = low indicates that plls are not locked or an incorrect serial-word-boundary alignment. lock remains low when the configuration link is active. lock is high impedance when pwdn = low. lock is an open-drain driver and requires a pullup resistor. 43 err active-low, open-drain video data error output with internal 60k i pullup to iovdd. err goes low when the number of decoding errors during normal operation exceeds a programmed error threshold, or when at least one prbs error is detected during a prbs test. err is high impedance when pwdn = low. err is an open-drain driver and requires a pullup resistor. 44 ms mode select. control-channel mode-selection input requires external pulldown or pullup resistor. ms sets the control-link mode when cds = high (see the control channel and register programming section). ms sets autostart mode when cds = low (see table 9). 45 ssen spread-spectrum enable input. serial link spread-spectrum enable input requires external pulldown or pullup resistor. the state of ssen latches upon power-up or when resuming from power-down mode ( pwdn = low). set ssen = high for q 2% spread spectrum on the lvds and control outputs. set ssen = low to use the lvds and control outputs without spread spectrum. 46 drs data-rate select. data-rate range-selection input requires external pulldown or pullup resistor. the state of drs latches upon power-up or when resuming from power-down mode ( pwdn = low). set drs = high for txclkout_ frequencies of 8.33mhz to 16.66mhz (3-channel mode) or 6.25mhz to 12.5mhz (4-channel mode). set drs = low for txclkout_ frequencies of 16.66mhz to 104mhz (3-channel mode) or 12.5mhz to 78mhz (4-channel mode). ? ep exposed pad. ep is internally connected to agnd. must externally connect ep to the agnd plane for proper thermal and electrical performance. downloaded from: http:///
________________________________________________________________ maxim integrated products 11 max9266 hdcp gigabit multimedia serial link deserializer with lvds system interface functional diagram parallel to lvds video fifo audio rgb[17:0] rgb hs hs vs de cntl1/res (4-ch) 8b/10b decode/ unscramble serial to parallel reverse control channel uart/i 2 c cntl2 (4-ch) fcc acb vsde rgb[23:18] (4-ch) res/cntl1 (4-ch) txout0+/- txclkout+/- in+in- txout1+/- txout2+/- txout3+/- (4-ch) cntl1 (4-ch) cntl2/mclk (4-ch) sd/cntl0 tx/scl rx/sda add0 add1 sck ws tx 7x pll sspll clkdiv hdcp decrypt hdcp decrypt hdcp keys hdcp contol cdrpll cml rx and eq max9266 downloaded from: http:///
________________________________________________________________ maxim integrated products 12 max9266 hdcp gigabit multimedia serial link deserializer with lvds system interface figure 1. reverse control-channel output parameters figure 2. test circuit for differential input measurement max9266 reverse control-channel transmitter in+ in- in- in+ in+ in- v od r l /2 r l /2 v cmr v cmr v roh (in+) - (in-) t r 0.1 x v rol 0.9 x v rol t f v rol 0.9 x v roh 0.1 x v roh v in+ r l /2 r l /2 c in c in v id(p) in+ in- v id(p) = | v in+ - v in- | v cmr = (v in+ + v in- )/2 v in- _ + _ _ + downloaded from: http:///
________________________________________________________________ maxim integrated products 13 max9266 hdcp gigabit multimedia serial link deserializer with lvds system interface figure 3. lvds output parameters figure 4. worst-case pattern output figure 5. i 2 c timing parameters txout_-, txclkout- v od v os gnd r l /2 r l /2 txout_+ txclkout+ txout_+ txclkout+ (txout_+) - (txout_-) (txclkout+) - (txclkout-) v os(-) v os(+) ((txclkout+) + (txclkout-))/2 ((txout_+) + (txout_-))/2 v os(-) v od(-) v od(-) t r v od = 0v d v os = |v os(+) - v os(-) | d v od = |v od(+) - v od(-) | v od (+) txout_- txclkout- t f txclkout+ txclkout- txout0+ to txout3+ txout0- to txout3- cntl_ p t r p s s t hold t f t set tx/ scl rx/ sda downloaded from: http:///
________________________________________________________________ maxim integrated products 14 max9266 hdcp gigabit multimedia serial link deserializer with lvds system interface figure 6. single-ended output high and low times figure 7. lvds output pulse position measurement figure 8. deserializer delay figure 10. power-up delay figure 9. lock time figure 11. output i 2 s timing parameters ws t dva t dvb t dva t f t dvb t r sck sd 0.8 x v i0vdd 0.2 x v i0vdd t f t r c l single-ended output load max9266 (txclkout+) - (txclkout-) (txout_+) - (txout_-) t ppos0 t ppos1 t ppos2 t ppos3 t ppos4 t ppos5 t ppos6 expanded time scale n first bit in+/in- txout_+/ txout_- txclkout+/- n+1 n-1 n first bit t sd n+2... in+ - in-lock t lock pwdn must be high v oh in+/- lock t pu pwdn v oh v ih1 downloaded from: http:///
________________________________________________________________ maxim integrated products 15 max9266 hdcp gigabit multimedia serial link deserializer with lvds system interface detailed description the max9266 gmsl deserializer with lvds inter- face utilizes maxim?s gigabit multimedia serial lin k (gmsl) technology and high-bandwidth digital content protection (hdcp). when hdcp is enabled, the deserial- izer decrypts video and audio data on the serial link. the deserializer is backward compatible with the max9268 lvds output deserializer. the deserializer has a maximum serial payload data rate of 2.5gbps for 15m or more of shielded twisted-pair (stp) cable. the deserializer operates up to a maximum input clock of 104mhz for 3-channel mode, or 78mhz for 4-channel mode, respectively. this serial link supports a wide range of display panels from qvga (320 x 240) to wxga (1280 x 800) and higher with 24-bit color. the 3-channel mode handles three lanes of lvds data (21 bits), uart control signals, and three audio signals. the 4-channel mode handles four lanes of lvds data (28 bits), uart control signals, three audio signals, and aux- iliary control outputs. the audio outputs form a standard i 2 s interface, supporting 8khz to 192khz sample rates and audio word lengths of 4 to 32 bits. the embedded control channel forms a full-duplex, differential 9.6kbps to 1mbps uart link between the serializer and the dese- rializer for hdcp-related control operations. in addition, the control channel enables electronic control unit (ecu) or microcontroller ( f c) control of peripherals on the remote side, such as backlight control, grayscale gamma correction, camera module, and touch screen. an ecu/ f c can be located on the serializer side of the link (typi- cal for video display), on the deserializer side of the link (typical for image sensing), or on both sides. base-mode communication with peripherals uses either i 2 c or the gmsl uart format. a bypass mode enables full-duplex communication using a user-defined uart format. the gmsl serializer pre/deemphasis, along with the deserializer channel equalizer, extends the link length and enhances the link reliability. spread spectrum is available to reduce emi on the lvds and control outputs. the serial inputs comply with iso 10605 and iec 61000- 4-2 esd protection standards. register mapping the f c configures various operating conditions of the gmsl serializer and the deserializer through internal registers. table 1 lists the default register values. the device addresses are stored in registers 0x00 and 0x01 of both the gmsl serializer and the deserializer. write to registers 0x00 and 0x01 in both devices to change the device address of the gmsl serializer or the deserializer. table 1. power-up default register map (see tables 16 and 17 ) register address (hex) power-up default (hex) power-up default settings (msb first) 0x00 0x40, 0x44, 0x48, 0x80, 0x84, 0x88, 0xc0, 0xc4, 0xc8 serid = xx00xx0, serializer device address is determined by add1 and add0 (table 2)reserved = 0 0x01 0x50, 0x54, 0x58, 0x90, 0x94, 0x98, 0xd0, 0xd4, 0xd8 desid = xx01xx0, deserializer device address is determined by add1 and add0 (table 2)cfgblock = 0, registers 0x00 to 0x1f are read/write 0x02 0x1f or 0x5f ss = 00 (ssen = low), ss = 01 (ssen = high), spread-spectrum settings depend on ssen pin state at power-up reserved = 0 audioen = 1, i 2 s channel enabled prng = 11, automatically detect the pixel clock rangesrng = 11, automatically detect the serial-data rate 0x03 0x00 autofm = 00, calibrate spread-modulation rate only once after lockingreserved = 0 sdiv = 00000, autocalibrate sawtooth divider downloaded from: http:///
________________________________________________________________ maxim integrated products 16 max9266 hdcp gigabit multimedia serial link deserializer with lvds system interface table 1. power-up default register map (see tables 16 and 17 ) (continued) register address (hex) power-up default (hex) power-up default settings (msb first) 0x04 0x03, 0x13, 0x43, 0x53 locked = 0, lock output is low (read only)outenb = 0 ( enable = low), outenb = 1 ( enable = high), outenb default depends on enable pin state at power-upprbsen = 0, prbs test disabled sleep = 0 or 1, sleep setting default depends on cds and ms pin state at power-up (see the link startup procedure section) inttype = 00, base mode uses i 2 c revccen = 1, reverse control channel active (sending)fwdccen = 1, forward control channel active (receiving) 0x05 0x24 or 0x29 i2cmethod = 0, i 2 c master sends the register address hpftune = 01, 3.75mhz equalizer highpass cutoff frequencypdhf = 0, high-frequency boosting disabled eqtune = 0100 (eqs = high, 5.2db), eqtune = 1001 (eqs = low, 10.7db), eqtune default setting depends on eqs pin state at power-up 0x06 0x0f reserved = 0, outputs are staggeredautorst = 0, error registers/output autoreset disabled disint = 0, int transmission enabled int = 0, int output is low (read only) gpio1out = 1, gpio1 output set to high gpio1 = 1, gpio1 input = high (read only) gpio0out = 1, gpio0 output set to high gpio0 = 1, gpio0 input = high (read only) 0x07 0x54 reserved = 01010100 0x08 0x30 reserved = 001100disvsfilt = 0, vsync glitch filter active dishsfilt = 0, hsync glitch filter active 0x09 0xc8 reserved = 11001000 0x0a 0x12 reserved = 00010010 0x0b 0x20 reserved = 00100000 0x0c 0x00 errthr = 00000000, error threshold set to zero for decoding errors 0x0d 0x00 (read only) decerr = 00000000, zero decoding errors detected 0x0e 0x00 (read only) prbserr = 00000000, zero prbs errors detected 0x12 0x00 mclksrc = 0, mclk is derived from txclkout_ (see table 5)mclkdiv = 0000000, mclk output is disabled 0x13 0x10 reserved = 00010000 downloaded from: http:///
________________________________________________________________ maxim integrated products 17 max9266 hdcp gigabit multimedia serial link deserializer with lvds system interface table 1. power-up default register map (see tables 16 and 17 ) (continued) register address (hex) power-up default (hex) power-up default settings (msb first) 0x14 0x09 invvsync = 0, deserializer does not invert vsyncinvhsync = 0, deserializer does not invert hsync forcelvds = 0, normal lvds operation dcs = 0, normal cmos driver current discntl = 1, cntl1 forced low disres = 0, serial-data bit 27 is mapped to res ilvds = 01, 3.5ma lvds current 0x1e 0x08 (read only) id = 00001000, device id is 0x08 0x1f 0x1x (read only) reserved = 000caps = 1, hdcp capable revision = xxxx 0x80 to 0x84 0xxxxxxxxxxx (read only) bksv = 0xxxxxxxxxxx, hdcp receiver ksv is 0xxxxxxxxxxx 0x85, 0x86 0xxxxx (read only) ri? = 0xxxxx, ri? of the transmitter is 0xxxxx 0x87 0xxx (read only) pj? = 0xxxxx, pj? of the transmitter is 0xxx 0x88 to 0x8f 0x00000000 00000000 an = 0000000000000000, session random number is 0000000000000000 0x90 to 0x94 0x00000000 00000000 aksv = 0x0000000000, hdcp transmitter ksv is 0x0000000000000000 0x95 0x00 pd_hdcp = 0, hdcp circuits powered upreserved = 000 gpio1_function = 0, normal gpio1 function gpio0_function = 0, normal gpio0 function auth_started = 0, hdcp authentication not started encryption_enable = 0, hdcp encryption disabled 0x96 0x00 reserved = 000000new_dev_conn = 0, no new devices connected ksv_list_ready = 0, ksv list is not ready 0x97 0x00 reserved = 0000000repeater = 0, hdcp receiver is not a repeater 0x98 to 0x9f 0x00000000 00000000 (read only) reserved = 0x0000000000000000 0xa0 to 0xa3 0xxxxxxxxx (read only) h0 part of sha-1 hash value is 0xxxxxxxxx 0xa04 to 0xa7 0xxxxxxxxx (read only) h1 part of sha-1 hash value is 0xxxxxxxxx downloaded from: http:///
________________________________________________________________ maxim integrated products 18 max9266 hdcp gigabit multimedia serial link deserializer with lvds system interface table 1. power-up default register map (see tables 16 and 17 ) (continued) table 2. device address defaults (register 0x00, 0x01) x = indeterminate. * x = 0 for the serializer address, x = 1 for the deserializer address. register address (hex) power-up default (hex) power-up default settings (msb first) 0xa8 to 0xab 0xxxxxxxxx (read only) h2 part of sha-1 hash value is 0xxxxxxxxx 0xac to 0xaf 0xxxxxxxxx (read only) h3 part of sha-1 hash value is 0xxxxxxxxx 0xb0 to 0xb3 0xxxxxxxxx (read only) h4 part of sha-1 hash value is 0xxxxxxxxx 0xb4 0x00 reserved = 0000max_cascade_exceeded = 0, seven or fewer cascaded hdcp devices attached depth = 000, device cascade depth is zero 0xb5 0x00 max_devs_exceeded = 0, 14 or fewer hdcp devices attacheddevice_count = 0000000, zero attached devices 0xb6 0x00 gpmem = 00000000, 0x00 stored in general-purpose memory 0xb7 to 0xb9 0x000000 (read only) reserved = 0x000000 0xba to 0xff all zero ksv_list = all zero, no ksvs stored pin device address (bin) serializer device address (hex) deserializer device address (hex) add1 add0 d7 d6 d5 d4 d3 d2 d1 d0 low low 1 0 0 x* 0 0 0 r/ w 80 90 low high 1 0 0 x* 0 1 0 r/ w 84 94 low open 1 0 0 x* 1 0 0 r/ w 88 98 high low 1 1 0 x* 0 0 0 r/ w c0 d0 high high 1 1 0 x* 0 1 0 r/ w c4 d4 high open 1 1 0 x* 1 0 0 r/ w c8 d8 open low 0 1 0 x* 0 0 0 r/ w 40 50 open high 0 1 0 x* 0 1 0 r/ w 44 54 open open 0 1 0 x* 1 0 0 r/ w 48 58 downloaded from: http:///
________________________________________________________________ maxim integrated products 19 max9266 hdcp gigabit multimedia serial link deserializer with lvds system interface table 3. lvds, hdcp mapping and bus-width selection (see figures 12 and 13 ) hdcp bitmapping and bus-width selection the lvds output has two selectable widths: 3-channe l and 4-channel. serial data is mapped to outputs on the deseri- alizer according to figure 12 and figure 13 . in 3-channel mode, txout3_ and cntl1, cntl2/mclk are not avail- able. for both modes, the sd/cntl0, sck, and ws pin s are for i 2 s audio when audio is enabled. with audio disabled, sd/cntl0 becomes control signal cntl0. the deserial izer outputs 8.33mhz to 104mhz clock rates for 3-channel mode and 6.25mhz to 78mhz for 4-channel mode table 3 lists the hdcp bit mapping for the lvds interface output. dout18 and dout19 are reserved for hsync and vsync, respectively. the deserializer has hdcp decryption on dout[17:0] and the i 2 s output. 4-channel mode has additional hdcp decryption on dout[26:21]. dout[28:27] and dout[20:18] do not have hdcp decryption. sd, when used as an additional data output (audioen = 0), also does not have hdcp decryption. * see the reserved bit (res)/cntl1 section for details. ** hdcp decryption on sd when used as an i 2 s signal. output bits 3-channel mode (bws = low) 4-channel mode (bws = high) typical bit- mapping auxiliary signals mapping hdcp de- cryption capability typical bit- mapping auxiliary signals mapping hdcp de- cryption capability dout[0:5] r[0:5] ? yes r[0:5] ? yes dout[6:11] g[0:5] ? yes g[0:5] ? yes dout[12:17] b[0:5] ? yes b[0:5] ? yes dout[18:20] hs, vs, de ? no hs, vs, de ? no dout[21:22] not available ? ? r6, r7 ? yes dout[23:24] not available ? ? g6, g7 ? yes dout[25:26] not available ? ? b6, b7 ? yes dout27 not available not available ? res* cntl1* no dout28 ? not available ? ? cntl2 no sd ? sd/cntl0 i 2 s** ? sd/cntl0 i 2 s** downloaded from: http:///
________________________________________________________________ maxim integrated products 20 max9266 hdcp gigabit multimedia serial link deserializer with lvds system interface figure 12. lvds output timing figure 13. typical panel clock and bit assignment dout1 cycle n txout0+ /txout0- txclkout+ txclkout- txout1+/txout1-txout2+/txout2- dout0 dout6 dout5 dout4 dout3 dout2 dout1 dout0 dout8 dout7 dout13 dout12 dout11 dout10 dout9 dout8 dout7 dout15 dout14 dout20 dout19 dout18 dout17 dout16 dout15 dout14 txout3+/txout3- cntl1 dout22 dout21 dout27 cntl2/mclk dout28 sd/cntl0 *only when i 2 s is disabled. sd* dout27 dout26 dout25 dout24 dout23 dout22 dout21 cycle n-1 r1 cycle n-1 cycle n txout0+/txout0- txclkout+ txclkout- txout1+/txout1-txout2+/txout2- r0 g0 r5 r4 r3 r2 r1 r0 g2 g1 b1 b0 g5 g4 g3 g2 g1 b3 b2 de vs hs b5 b4 b3 b2 txout3+/txout3- r7 r6 res b7 b6 g7 g6 r7 r6 downloaded from: http:///
________________________________________________________________ maxim integrated products 21 max9266 hdcp gigabit multimedia serial link deserializer with lvds system interface serial link signaling and data format the gmsl serializer uses cml signaling with program- mable pre/deemphasis and ac-coupling. the deseri- alizer uses ac-coupling and programmable channel equalization. together, the gmsl link can operate at full speed over stp cable lengths to 15m or more. the gmsl serializer scrambles and encodes the input data and sends the 8b/10b coded signal through the serial link. the deserializer recovers the embedded serial clock and then samples, decodes, and descrambles before outputting the data. figure 14 and 15 show the serial-data packet format after unscrambling and 8b/10b decoding. in 3-channel or 4-channel mode, 21 or 29 bits map to the high-speed output. the audio channel bit (acb) contains an encoded audio signal derived from the three i 2 s signals (sd, sck, and ws). the forward control-channel (fcc) bit carries the forward control data. the last bit (pcb) is the parity bit of the previous 23 or 31 bits. figure 14. 3-channel mode serial link data format figure 15. 4-channel mode serial link data format note: vs/hs must be set at din[19:18] for hdcp functionality. only dout[17:0] and acb have hdcp decryption. dout 0 r0 r1 b5 hs vs de dout 1 dout 17 dout 18 dout 19 dout 20 acb fcc pcb 24 bits rgb data lvds data (3 channels) contol bits packet parity check bit audio channel or cntl0 bit forward control- channel bit rgb data control bits rgb data aux control bits note: vs/hs must be set at din[19:18] for hdcp functionality. only dout[17:0], dout[26:21], and acb have hdcp decryption. *dout27 outputs to lvds data (txout3_) and/or external pin (cntl1). dout 0 r0 r1 b5 hs vs de r6 r7 g6 g7 b6 b7 res/ cntl1* cntl2 dout 1 dout 17 dout 18 dout 19 dout 20 dout 21 dout 22 dout 23 dout 24 dout 25 dout 26 dout 27 dout 28 acb fcc pcb 32 bits packet parity check bit audio channel or cntl0 bit forward control- channel bit lvdsdata (txout[2:0]_) lvdsdata (txout3_) downloaded from: http:///
________________________________________________________________ maxim integrated products 22 max9266 hdcp gigabit multimedia serial link deserializer with lvds system interface reverse control channel the gmsl serializer uses the reverse control channel to receive i 2 c/uart and interrupt signals from the deseri- alizer in the opposite direction of the video stream. the reverse control channel and forward video data coexist on the same twisted pair forming a bidirectional link. the reverse control channel operates independently from the forward control channel. the reverse control channel is available 500 f s after power-up. the gmsl serializer tem- porarily disables the reverse control channel for 350 f s after starting/stopping the forward serial link. reserved bit (res)/cntl1 in 4-channel mode, the deserializer by default deserial- izes serial data bit 27 to res (disres = 0) while cntl is forced low (discntl = 1). setting disres (d2 of register 0x14) = 1 forces res low. setting discntl1 (d3 of reg- ister 0x14) = 0 maps data bit 27 to cntl1. data-rate selection the deserializer uses the drs input to set the txclkout_ frequency range. set drs high for a 6.25mhz to 12.5mhz txclkout_ frequency range (4-channel mode) or 8.33mhz to 16.66mhz (3-channel mode). set drs low for normal operation with a 12.5mhz to 78mhz txclkout_ frequency range (4-channel mode) or 16.66mhz to 104mhz (3-channel mode). audio channel the i 2 s audio channel supports 8khz to 192khz audio sampling rates and audio word lengths from 4 bits to 32 bits. the audio bit clock (sck) does not have to be synchronized with txclkout_. the gmsl serial- izer automatically encodes audio data into a single bit stream synchronous with txclkout_. the deserializer decodes the audio stream and stores audio words in a fifo. audio rate detection uses an internal oscillator to continuously determine the audio data rate and output the audio in i 2 s format. the audio channel is enabled by default. when the audio channel is disabled, the sd/cntl0 on the gmsl serializer and deserializer is treated as an additional control signal (cntl0). since the audio data sent through the serial link i s syn- chronized with txclkout_, low txclkout_ frequen- cies limit the maximum audio sampling rate. table 4 lists the maximum audio sampling rate for various txclkou t_ frequencies. spread-spectrum settings do not affect the i 2 s data rate or ws clock frequency. additional mclk output for audio applications some audio dacs, such as the max9850, do not require a synchronous main clock (mclk), while other dacs require mclk to be a specific multiple of ws. if an audio dac chip needs the mclk to be a multiple of ws, use an external pll to regenerate the required mclk from txclkout_ or sck. for audio applications that cannot use txclkout_ directly, the deserializer provides a divided mclk output on cntl2/mclk at the expense of one less control line in 4-channel mode. by default, cntl2/mclk operates as a control data output and mclk is turned off. set mclkdiv (deserializer register 0x12, d[6:0]) to a nonzero value to enable the mclk output. set mclkdiv to 0x00 to disable mclk and set cntl2/mclk as a control output. table 4. maximum audio ws frequency (khz) for various txclkout_ frequencies word length (bits) txclkout_ frequency (drs = low) (mhz) txclkout_ frequency (drs = high) (mhz) 12.5 15 16.6 > 20 6.25 7.5 8.33 > 10 8 > 192 > 192 > 192 > 192 > 192 > 192 > 192 > 192 16 > 192 > 192 > 192 > 192 > 192 > 192 > 192 > 192 18 185.5 > 192 > 192 > 192 185.5 > 192 > 192 > 192 20 174.6 > 192 > 192 > 192 174.6 > 192 > 192 > 192 24 152.2 182.7 > 192 > 192 152.2 182.7 > 192 > 192 32 123.7 148.4 164.3 > 192 123.7 148.4 164.3 > 192 downloaded from: http:///
________________________________________________________________ maxim integrated products 23 max9266 hdcp gigabit multimedia serial link deserializer with lvds system interface the output mclk frequency is: src mclk f f mclkdiv = where:f src is the mclk source frequency (see table 5 ) mclkdiv is the divider ratio from 1 to 127 choose mclkdiv values so that f mclk is not greater than 60mhz. mclk frequencies derived from txclkout_ (mclksrc = 0) are not affected by spread-spectrum settings in the deserializer. enabling spread spectrum in the gmsl serializer, however, introduces spread spectrum into mclk. spread-spectrum settings of either device do not affect mclk frequencies derived from the internal oscillator. the internal oscillator frequency ranges from 100mhz to 150mhz over all process corners and operating conditions. control channel and register programming the control channel is available for the f c to send and receive control data over the serial link simultane- ously with the high-speed data. configuring the cds pin allows the f c to control the link from either the gmsl serializer or the deserializer side to support video-display or image-sensing applications. the control channel between the f c and gmsl serializer or deserializer runs in base mode or bypass mode according to the mode- selection (ms) input of the device connected to the f c. base mode is a half-duplex control channel and bypass mode is a full-duplex control channel. base mode in base mode, the f c accesses the core and hdcp registers of the gmsl serializer and deserializer using the gmsl uart protocol. the f c can also program i 2 c peripherals on the remote side by sending uart packets that are converted to i 2 c on the remote side of the link. the f c communicates with a uart periph- eral in base mode (through inttype register settings), using the half-duplex default gmsl uart protocol. the device addresses of the gmsl serializer and deserializer in base mode are programmable. the default value is determined by the pin settings of add0 and add1 (see table 2 ). when the peripheral interface is i 2 c (default), the device converts packets to i 2 c that have device addresses dif- ferent from those of the gmsl serializer or deserializer. the converted i 2 c bit rate is the same as the original uart bit rate. the deserializer uses a proprietary differential li ne coding to send signals back towards the serializer. the speed of the control channel ranges from 9.6kbps to 1mbps in both directions. the gmsl serializer and dese- rializer automatically detect the control-channel bit rate in base mode. when changing the bit rate, the new packet bit rate can vary up to 3.5x from the previous bit rate (see the changing the clock frequency section). table 5. f src settings mclksrc setting (register 0x12, d7) data-rate setting bus-width setting mclk source frequency (f src ) 0 high speed (drs = high) 3-channel mode 3 x f txclkout_ 4-channel mode 4 x f txclkout_ low speed (drs = low) 3-channel mode 6 x f txclkout_ 4-channel mode 8 x f txclkout_ 1 ? ? internal oscillator (120mhz typ) downloaded from: http:///
________________________________________________________________ maxim integrated products 24 max9266 hdcp gigabit multimedia serial link deserializer with lvds system interface figure 16 shows the uart protocol for writing and read- ing in base mode between the f c and the gmsl serial- izer/deserializer. figure 17 shows the uart data format. figures 18 and 19 detail the formats of the sync byte (0x79) and the ack byte (0xc3). the f c and the connected slave chip generate the sync byte and ack byte, respectively. events such as device wake-up and interrupt generate transitions on the control channel that should be ignored by the f c. data written to the gmsl serializer/deserializ- er registers do not take effect until after the acknowledge byte is sent. this allows the f c to verify write commands received without error, even if the result of the write com- mand directly affects the serial link. the slave uses the sync byte to synchronize with the f c uart data rate automatically. if the int or ms inputs of the deserializer toggle while there is control-channel communication, the control-channel communication can be corrupted. in the event of a missed acknowledge, the f c assumes there was an error in the packet when the slave device receives it, or that an error occurred during the response from the slave device. in base mode, the f c must keep the uart tx/rx lines high for 16 bit times before sending a new packet. figure 16. gmsl uart protocol for base mode figure 17. gmsl uart data format for base mode figure 18. sync byte (0x79) figure 19. ack byte (0xc3) write data format sync dev addr + r/w reg addr number of bytes sync dev addr + r/w reg addr number of bytes byte 1 byte n ack byte n byte 1 ack master reads from slave read data frmat master writes to slave master writes to slave master reads from slave start d0 d1 d2 d3 d4 d5 d6 d7 parity stop 1 uart frame frame 1 frame 2 frame 3 stop start stop start start d0 1 0 0 1 1 1 1 0 d1 d2 d3 d4 d5 d6 d7 parity stop start d0 1 1 0 0 0 0 1 1 d1 d2 d3 d4 d5 d6 d7 parity stop downloaded from: http:///
________________________________________________________________ maxim integrated products 25 max9266 hdcp gigabit multimedia serial link deserializer with lvds system interface as shown in figure 20 , the remote-side device converts the packets going to or coming from the peripherals from the uart format to the i 2 c format and vice versa. the remote device removes the byte number count and adds or receives the ack between the data bytes of i 2 c. the i 2 c?s data rate is the same as the uart data rate. interfacing command-byte-only i 2 c devices the gmsl serializer and deserializer uart-to-i 2 c con- version interfaces with devices that do not require reg- ister addresses, such as the max7324 gpio expander. in this mode, the i 2 c master ignores the register address byte and directly reads/writes the subsequent data bytes ( figure 21 ). change the communication method of the i 2 c master using the i2cmethod bit. i2cmethod = 1 sets command-byte-only mode, while i2cmethod = 0 sets normal mode where the first byte in the data stream is the register address. figure 20. format conversion between gmsl uart and i 2 c with register address (i2cmethod = 0) figure 21. format conversion between gmsl uart and i 2 c with register address (i2cmethod = 1) : master to slave gmsl serializer/deserializer gmsl serializer/deserializer gmsl serializer/deserializer uart-to-i 2 c conversion of read packet (i2cmethod = 1) uart-to-i 2 c conversion of write packet (i2cmethod = 1) f c gmsl serializer/deserializer f c sync frame 11 11 11 11 11 11 11 11 11 11 11 11 11 11 device id + rd register address number of bytes sync frame device id + wr register address number of bytes data 0 data n ack frame ack frame data 0 data n data n a data 0 w a dev id s a p peripheralperipheral s 1 1 1 8 8 8 1 11 1 7 1 1 8 1 1 1 7 dev id r a a a p data 0 data n : slave to master s: start p: stop a: acknowledge 11 sync frame register address number of bytes device id + wr data 0 dev id a 11 11 11 11 data n 11 11 s 1 1 1 ack frame 7 : master to slave 8 gmsl serializer/deserializer peripheral w 1 reg addr 8 a 1 1 8 1 11 sync frame register address number of bytes device id + rd 11 11 11 11 ack frame data 0 11 data n 11 uart-to-i 2 c conversion of write packet (i2cmethod = 0) uart-to-i 2 c conversion of read packet (i2cmethod = 0) s: start p: stop a: acknowledge : slave to master data 0 a data n a p dev id a s 1 1 7 w 1 dev id a s 1 1 7 r 1 data n p 1 8 a 1 data 0 8 a 1 reg addr 8 a 1 f c gmsl serializer/deserializer f c gmsl serializer/deserializer gmsl serializer/deserializer peripheral downloaded from: http:///
________________________________________________________________ maxim integrated products 26 max9266 hdcp gigabit multimedia serial link deserializer with lvds system interface bypass mode in bypass mode, the gmsl serializer/deserializer ig nore uart commands from the f c and the f c communi- cates with the peripherals directly using its own d efined uart protocol. the f c cannot access the gmsl seri- alizer/deserializer?s registers in this mode. perip herals accessed through the forward control channel using the uart interface must tolerate up to one txclkout _ period q 10ns of jitter due to the asynchronous sampling of the uart signal by txclkout_. set ms = high to put the control channel into bypass mode. a 1ms wai t time is required between setting ms high on the deserial- izer and the bypass becoming active. there is no de lay when switching to bypass mode on the serializer (cd s = low). do not send a logic-low longer than 100 f s on the control channel in bypass mode if interrupt (int) i s used. bypass mode accepts bit rates down to 10kbps in eit her direction. interrupt control the int pin of the gmsl serializer is the interrupt output and the int pin of the deserializer is the interrupt input. following a transition, the logic state of the interrupt input is reproduced on the interrupt output. the interrupt supports remote-side functions such as touch-screen peripherals, remote power-up, or remote monitoring. an interrupt that occurs when the reverse control channel is disabled, such as during link startup/shutdown, is sent once the reverse control channel becomes available. bit d4 of register 0x06 in the deserializer stores the interrupt input state. the int output of the gmsl serializer is low after power-up. the f c can set the int output by writ- ing the setint register bit. do not low-state data on the control channel longer than 100 f s in either base mode or bypass mode to ensure proper interrupt functionality. line equalizer the deserializer includes an adjustable line equalizer to compensate cable attenuation at high frequencies. the cable equalizer has 11 levels of compensation from 2.1db to 13db (see table 6 ). the eqs input selects the default equalization level at power-up. the state of eqs is latched upon power-up or when resuming from power- down mode. to select other equalization levels, set the corresponding register bits in the deserializer (0x05 d[3:0]). use equalization in the deserializer, together with pre/deemphasis in the gmsl serializer to create the most reliable link for a given cable. spread spectrum to reduce the emi generated by transitions on the serial link and outputs of the deserializer, the gmsl serial- izer/deserializer are individually capable of generating spread spectrum. however, turning on spread spectrum in the gmsl serializer spreads the serial link and the deserializer outputs since the deserializer tracks the spread on the serial link. do not enable spread genera- tion on the gmsl serializer/deserializer at the same time. the amplitudes of the deserializer spread-spectrum gen- erator are q 2% and q 4% (see table 7 ). set the deserializer ssen input high to select a q 2% spread at power-up and ssen input low to select no spread at power-up. the state of ssen is latched upon power-up or when resuming from power-down mode. table 6. deserializer cable equalizer boost levels table 7. output spread boost setting (0x05 d[3:0]) typical boost gain (db) 0000 2.1 0001 2.8 0010 3.4 0011 4.2 0100 5.2 power-up default (eqs = high) 0101 6.2 0110 7 0111 8.2 1000 9.4 1001 10.7 power-up default (eqs = low) 1010 11.7 1011 13 ss spread (%) 00 no spread spectrum. power-up default when ssen = low. 01 q 2% spread spectrum. power-up default when ssen = high. 10 no spread spectrum 11 q 4% spread spectrum downloaded from: http:///
________________________________________________________________ maxim integrated products 27 max9266 hdcp gigabit multimedia serial link deserializer with lvds system interface turning on spread spectrum on the gmsl serializer or deserializer does not spread the audio data stream. the gmsl serializer spreads the deserializer mclk output if it is derived from txclkout_ (mclksrc = 0). the deserializer includes a sawtooth divider to control the spread-modulation rate. autodetection or manual programming of the txclkout_ operation range guar- antees a spread-spectrum modulation frequency within 20khz to 40khz. additionally, manual configuration of the sawtooth divider (sdiv, 0x03 d[4:0]) allows the user to set a modulation frequency according to the txclkout_ frequency. always keep the modulation frequency between 20khz and 40khz to ensure proper operation. manual programming of the spread-spectrum divider the modulation rate for the deserializer relates to the txclkout_ frequency as follows: ( ) txclkout_ m f f 1 drs mod sdiv = + where:f m = modulation frequency drs = drs pin input value (0 or 1) f txclkout_ = txclkout_ frequency mod = modulation coefficient given in table 8 sdiv = 5-bit sdiv setting, manually programmed by th e f c to program the sdiv setting, first look up the modula- tion coefficient according to the desired bus-width and spread-spectrum settings. solve the above equation for sdiv using the desired pixel clock and modulation fre- quencies. if the calculated sdiv value is larger than the maximum allowed sdiv value in table 8 , set sdiv to the maximum value. sleep mode the deserializer includes a low-power sleep mode to reduce power consumption on the device. set the sleep bit to 1 to initiate sleep mode. the deserializer sleeps after serial link inactivity or 8ms (whichever arrives first) after setting its sleep = 1. see the link startup procedure section for details on waking up the device for different f c and starting conditions. the f c can only put the remote-side device into sleep mode. use the pwdn input pin to bring the f c-side device into a low-power state. entering sleep mode resets the hdcp registers but not the configuration regist ers. power-down mode the deserializer includes a power-down mode that reduces power consumption more than sleep mode. set pwdn low to enter power-down mode. in power-down mode, the outputs are high impedance. power-down mode resets the internal registers of the device. upon exiting power-down mode, the deserializer relatches the state of the ssen, drs, and eqs pins. configuration link gmsl includes a low-speed configuration link to allow control-channel operation in the absence of a clock input. in either display or camera applications, the con- figuration link can program equalizer, preemphasis, or other registers before establishing the video link. an internal oscillator provides txclkout_ for establishing the serial configuration link. set clinken = 1 on the gmsl serializer to turn on the configuration link. the configuration link remains active as long as the video link is not enabled. the video link overrides the configuration link and attempts to lock when seren = 1. table 8. modulation coefficients and maximum sdiv settings spread-spectrum setting (%) modulation coefficient (dec) sdiv upper limit (dec) q 4 208 15 q 2 208 30 downloaded from: http:///
________________________________________________________________ maxim integrated products 28 max9266 hdcp gigabit multimedia serial link deserializer with lvds system interface link startup procedure table 9 lists four startup cases for display applications. table 10 lists two startup cases for image-sensing appli- cations. in either application, the control link is available after the video link or the configuration link is e stablished. then the gmsl registers or the peripherals are read y for programming. video-display applications for video-display applications, connect the f c to the gmsl serializer and set cds = low for both the gmsl serializer and deserializer. table 9 summarizes the four startup cases based on the settings of autos and ms. case 1: autostart mode after power-up or when pwdn transitions from low to high for both the gmsl serializer and deserializer, the serial link is established if a stable clock is present. the gmsl serializer locks to the clock and sends the serial data to the deserializer. the deserializer then detects activity on the serial link and locks to the input serial data. case 2: standby start mode after power-up or when pwdn transitions from low to high for both the gmsl serializer and deserializer, the deserializer starts up in sleep mode, and the gmsl serializer stays in standby mode (does not send serial data). use the f c and program the gmsl serializer to set seren = 1 to establish a video link, or clinken = 1 to establish the configuration link. after locking to a stable clock (for seren = 1) or the internal oscillator (for clinken = 1), the gmsl serializer sends a wake- up signal to the deserializer. the deserializer exits sleep mode after locking to the serial data and sets sleep = 0. if after 8ms the deserializer does not lock to the input serial data, the deserializer goes back to sleep, and the internal sleep bit remains set (sleep = 1). case 3: remote-side autostart mode after power-up or when pwdn transitions from low to high, the remote device (deserializer) starts up and trie s to lock to an incoming serial signal with sufficient power. the host side (gmsl serializer) is in standby mode and does not try to establish a link. use the f c and program the gmsl seri- alizer to set seren = 1 (and apply a stable clock s ignal) to establish a video link, or clinken = 1 to establ ish the configuration link. in this case, the deserializer ignores the short wake-up signal sent from the gmsl serializer. table 9. startup selection for display applications (both cds = low) case autos (gmsl serializer) gmsl serializer power-up state ms (gmsl deserializer) gmsl deserializer power-up state link startup mode 1 low serialization enabled low normal (sleep = 0) both devices power up with the serial link active (autostart). 2 high serialization disabled high sleep mode (sleep = 1) serial link is disabled and the deserializer powers up in sleep mode. set seren = 1 or clinken = 1 in the gmsl serializer to start the serial link and wake up the deserializer. 3 high serialization disabled low normal (sleep = 0) both devices power up in normal mode with the serial link disabled. set seren = 1 or clinken = 1 in the gmsl serializer to start the serial link. 4 low serialization enabled high in sleep mode (sleep = 1) the deserializer starts in sleep mode. link autostarts upon gmsl serializer power- up. use this case when the deserializer powers up before the gmsl serializer. downloaded from: http:///
________________________________________________________________ maxim integrated products 29 max9266 hdcp gigabit multimedia serial link deserializer with lvds system interface case 4: remote side in sleep mode after power-up or when pwdn transitions from low to high, the remote device (deserializer) starts up in sleep mode. the high-speed link establishes automatically after the gmsl serializer powers up with a stable clock signal and sends a wake-up signal to the deserializer. use this mode in applications where the deserializer powers up before the gmsl serializer. image-sensing applications for image-sensing applications, connect the f c to the deserializer and set cds = high for both the gmsl seri- alizer and deserializer. the deserializer powers up nor- mally (sleep = 0) and continuously tries to lock to a valid serial input. table 10 summarizes both startup cases, based on the state of the gmsl serializer autos pin. case 1: autostart mode after power-up, or when pwdn transitions from low to high, the gmsl serializer locks to a stable input clock and sends the video data to the deserializer. the deseri- alizer locks to the serial data and outputs the video data and clock. case 2: sleep mode after power-up or when pwdn transitions from low to high, the gmsl serializer starts up in sleep mode. to wake up the serializer, use the f c to send a gmsl pro- tocol uart frame containing at least three rising edges (e.g., 0x66) at a bit rate no greater than 1mbps. the low-power wake-up receiver of the serializer detects the wake-up frame over the reverse control channel and powers up. reset the sleep bit (sleep = 0) of the gmsl serializer using a control-channel write packet to power up the device. send the sleep bit reset write packet at least 500 f s after the wake-up frame. the gmsl serializer goes back to sleep mode if its sleep bit is not reset within 5ms (min) after detecting a wake-up frame. figure 22. state diagram, cds = low (display application) sleep ms pin setting low high 01 sleep bit power-up value config link operating program registers power-off high to low sleep = 1, video link or config link not locked after 8ms power-on idle wake-up signal serial port locking signal detected config link unlocked config link locked video link locked video link unlocked 0 sleep 0 sleep all states int changes from low to high or send int to pwdn = low or pwdn = high,power-on power-down or power-off serial link activity stops or 8ms elapses after f c sets sleep = 1 video link operating prbsen = 0prbsen = 1 video link prbs test gmsl serializer downloaded from: http:///
________________________________________________________________ maxim integrated products 30 max9266 hdcp gigabit multimedia serial link deserializer with lvds system interface high-bandwidth digital content protection (hdcp) note: the explanation of hdcp operation in this data sheet is provided as a guide for general understanding. implementation of hdcp in a product must meet the requirements given in the hdcp system v1.3 amendment for gmsl , which is available from dcp. hdcp has two main phases of operation: authentication and the link integrity check. the f c starts authentica- tion by writing to the start_authentication bit in the gmsl serializer. the gmsl serializer generates a 64-bit random number. the host f c first reads the 64-bit random number from the gmsl serializer and writes it to the deserializer. the f c then reads the gmsl seri- alizer public key selection vector (aksv) and writes it to the deserializer. the f c then reads the deserializer ksv (bksv) and writes it to the gmsl serializer. the f c begins checking bksv against the revocation list. using the cipher, the gmsl serializer and deserializer calculate a 16-bit response value, r0 and r0?, respectively. the gmsl amendment for hdcp reduces the 100ms mini- mum wait time allowed for the receiver to generate r0? (specified in hdcp rev 1.3) to 128 pixel clock cycles in the gmsl amendment. there are two response-value comparison modes: inter- nal comparison and f c comparison. set en_int_comp = 1 to select internal comparison mode. set en_int_ comp = 0 to select f c comparison mode. in inter- nal comparison mode, the f c reads the deserializer response r0? and writes it to the gmsl serializer. the gmsl serializer compares r0? to its internally generated response value r0, and sets r0_ri_matched. in f c comparison mode, the f c reads and compares the r0/ r0? values from the gmsl serializer/deserializer. figure 23. state diagram, cds = high (camera application) table 10. startup selection for image-sensing application (both cds = high) case autos (gmsl serializer) gmsl serializer power-up state gmsl deserializer power-up state link startup mode 1 low serialization enabled normal (sleep = 0) autostart. 2 high sleep mode (sleep = 1) normal (sleep = 0) gmsl serializer is in sleep mode. wake up the gmsl serializer through the control channel ( f c attached to deserializer). power-on idle serial port locking all states power-down or power-off no signal detected pwdn = high, power-on config link operating video link operating video link locked video link unlocked prbsen = 0prbsen = 1 video link prbs test config link unlocked config link locked signal detected program registers pwdn = low or power-off (reverse channel active) downloaded from: http:///
________________________________________________________________ maxim integrated products 31 max9266 hdcp gigabit multimedia serial link deserializer with lvds system interface during response-value generation and comparison, the host f c checks for a valid bksv (having 20 1s and 20 0s is also reported in bksv_invalid) and checks bksv against the revocation list. if bksv is not on the list and the response values match, the host authenticates the link. if the response values do not match, the f c resamples the response values (as described in hdcp rev 1.3, appendix c). if resampling fails, the f c restarts authentication by setting the reset_hdcp bit in the gmsl serializer. if bksv appears on the revocation list, the host cannot transmit data that requires protec- tion. the host knows when the link is authenticated and decides when to output data requiring protection. the f c performs a link integrity check every 128 frames or every 2s q 0.5s. the gmsl serializer/deserializer gener- ate response values every 128 frames. these values are compared internally (internal comparison mode) or can be compared in the host f c. in addition, the gmsl serializer/deserializer provi de response values for the enhanced link verification. enhanced link verification is an optional method of link verification for faster detection of loss-of-synchronization. for this option, the gmsl serializer and deserializer gen- erate 8-bit enhanced link-verification response values (pj and pj?) every 16 frames. the host must detect three consecutive pj/pj? mismatches before resampling. encryption enable the gmsl link transfers either encrypted or nonen- crypted data. to encrypt data, the host f c sets the encryption enable (encryption_enable) bit in both the gmsl serializer and deserializer. the f c must set encryption_enable in the same vsync cycle in both the gmsl serializer and deserializer (no internal vsync falling edges between the two writes). the same timing applies when clearing encryption_enable to disable encryption. note: encryption_enable enables/disables encryp- tion on the gmsl irrespective of the content. to comply with hdcp, the f c must not allow content requiring encryption to cross the gmsl unencrypted. the f c must complete the authentication process before enabling encryption. in addition, encryption must be dis- abled before starting a new authentication session. synchronization of encryption the video vertical sync (vsync) synchronizes the start of encryption. once encryption has started, the gmsl generates a new encryption key for each frame and each line, with the internal falling edge of vsync and hsync. rekeying is transparent to data and does not disrupt the encryption of video or audio data. repeater support the gmsl serializer/deserializer include features to build an hdcp repeater. an hdcp repeater receives and decrypts hdcp content and then encrypts and trans- mits on one or more downstream links. a repeater can also use decrypted hdcp content (e.g., to display on a screen). to support hdcp repeater-authentication pro- tocol, the deserializer has a repeater register bit. this register bit must be set to 1 by a f c (most likely on the repeater module). both the gmsl serializer and deserial- izer use sha-1 hash-value calculation over the assem- bled ksv lists. hdcp gmsl links support a maximum of 15 receivers (total number including the ones in repeater modules). if the total number of downstream receivers exceeds 14, the f c must set the max_devs_exceeded register bit when it assembles the ksv list. hdcp authentication procedures the gmsl serializer generates a 64-bit random number exceeding the hdcp requirement. the gmsl serial- izer/deserializer internal one-time programmable (otp) memories contain a unique hdcp keyset programmed at the factory. the host f c initiates and controls the hdcp authentication procedure. the gmsl serializer and dese- rializer generate hdcp authentication response values for the verification of authentication. use the following procedures to authenticate the hdcp gmsl encryption (refer to the hdcp 1.3 amendment for gmsl for details). the f c must perform link integrity checks while encryp- tion is enabled (see table 12 ). any event that indicates that the deserializer has lost link synchronization should retrigger authentication. the f c must first write 1 to the reset_hdcp bit in the gmsl serializer before starting a new authentication attempt. downloaded from: http:///
________________________________________________________________ maxim integrated products 32 max9266 hdcp gigabit multimedia serial link deserializer with lvds system interface hdcp protocol summary table 11 , 12 , and 13 list the summaries of the hdcp protocol. these tables serve as an implementation guide only. meet the requirements in the gmsl amendment for hdcp to be in full compliance. table 11. startup, hdcp authentication, and normal operation (deserializer is not a repeater)?first part of the hdcp authentication protocol no. c hdcp gmsl serializer hdcp gmsl deserializer 1 initial state after power-up. powers up waiting for hdcp authentication. powers up waiting for hdcp authentication. 2 makes sure that a/v data not requiring protection (low-value content) is available at the gmsl serializer inputs (such as blue or informative screen). alternatively, uses the force_video and force_audio bits of the gmsl serializer to mask a/v data at the input of the gmsl serializer. starts the link by writing seren = h or link starts automatically if autos is low. ? ? 3 ? starts serialization and transmits low-value content a/v data. locks to incoming data stream and outputs low-value content a/v data. 4 reads the locked bit of the deserializer and makes sure the link is established. ? ? 5 optionally writes a random-number seed to the gmsl serializer. combines seed with internally generated random number. if no seed provided, only internal random number is used. ? 6 if hdcp encryption is required, starts authentication by writing 1 to the start_authentication bit of the gmsl serializer. generates (stores) an, and resets the start_authentication bit to 0. ? 7 reads an and aksv from the gmsl serializer and writes to the deserializer. ? generates r0? triggered by the f c?s write of aksv. 8 reads the bksv and repeater bit from and writes to the gmsl serializer. generates r0, triggered by the f c?s write of bksv. ? 9 reads the invalid_bksv bit of the gmsl serializer and continues with authentication if it is 0. authentication can be restarted if it fails (set reset_hdcp = 1 before restarting authentication). ? ? downloaded from: http:///
________________________________________________________________ maxim integrated products 33 max9266 hdcp gigabit multimedia serial link deserializer with lvds system interface table 12. link integrity check (normal)?performed every 128 frames after encryption is enabled table 11. startup, hdcp authentication, and normal operation (deserializer is not a repeater)?first part of the hdcp authentication protocol (continued) no. c hdcp gmsl serializer hdcp gmsl deserializer 10 reads r0? from the deserializer and reads r0 from the gmsl serializer. if they match, continues with authentication; otherwise, retries up to two more times (optionally, gmsl serializer comparison can be used to detect if r0/r0? match). authentication can be restarted if it fails (set reset_hdcp = 1 before restarting authentication). ? ? 11 waits for the vsync falling edge (internal to the gmsl serializer) and then sets the encryption_enable bit to 1 in the deserializer and gmsl serializer (if the f c is not able to monitor vsync, it can utilize the vsync_det bit in the gmsl serializer). encryption enabled after the next vsync falling edge. decryption enabled after the next vsync falling edge. 12 checks that bksv is not in the key revocation list and continues if it is not. authentication can be restarted if it fails. note: revocation list check can start after bksv is read in step 8. ? ? 13 starts transmission of a/v content that needs protection. performs hdcp encryption on high-value content a/v data. performs hdcp decryption on high-value content a/v data. no. c hdcp gmsl serializer hdcp gmsl deserializer 1 ? generates ri and updates the ri register every 128 vsync cycles. generates ri? and updates the ri? register every 128 vsync cycles. 2 ? continues to encrypt and trans- mit a/v data. continues to receive, decrypt, and output a/v data. 3 every 128 video frames (vsync cycles) or every 2s. ? ? 4 reads ri from the gmsl serializer. ? ? 5 reads ri? from the deserializer. ? ? 6 reads ri again from the gmsl serializer and makes sure it is stable (matches the previous ri that it has read from the gmsl serializer). if ri is not stable, go back to step 5. ? ? downloaded from: http:///
________________________________________________________________ maxim integrated products 34 max9266 hdcp gigabit multimedia serial link deserializer with lvds system interface table 12. link integrity check (normal)?performed every 128 frames after encryption is enabled (continued) table 13. optional enhanced link integrity check?performed every 16 frames after encryption is enabled no. c hdcp gmsl serializer hdcp gmsl deserializer 7 if ri matches ri?, the link integrity check is successful; go back to step 3. ? ? 8 if ri does not match ri?, the link integrity check fails. after the detection of failure of link integrity check, the f c makes sure that a/v data not requiring protection (low-value con- tent) is available at the gmsl serializer inputs (such as blue or informative screen). alterna- tively, the force_video and force_audio bits of the gmsl serializer can be used to mask a/v data input of the gmsl serializer. ? ? 9 writes 0 to the encryption_enable bit of the gmsl serializer and deserializer. disables encryption and trans- mits low-value content a/v data. disables decryption and outputs low-value content a/v data. 10 restarts authentication by writing 1 to the reset_hdcp bit followed by writing 1 to the start_authentication bit in the gmsl serializer. ? ? no. c hdcp gmsl serializer hdcp gmsl deserializer 1 ? generates pj and updates the pj register every 16 vsync cycles. generates pj? and updates the pj? register every 16 vsync cycles. 2 ? continues to encrypt and trans- mit a/v data. continues to receive, decrypt, and output a/v data. 3 every 16 video frames, reads pj from the gmsl serializer and pj? from the deserializer. ? ? 4 if pj matches pj?, the enhanced link integrity check is successful; go back to step 3. ? ? downloaded from: http:///
________________________________________________________________ maxim integrated products 35 max9266 hdcp gigabit multimedia serial link deserializer with lvds system interface table 13. optional enhanced link integrity check?performed every 16 frames after encryption is enabled (continued) example repeater network?two cs the example shown in figure 24 has one repeater and two f cs. table 14 summarizes the authentication operation. figure 24. example network with one repeater and two cs (tx = gmsl serializer?s, rx = deserializer?s) no. c hdcp gmsl serializer hdcp gmsl deserializer 5 if there is a mismatch, retry up to two more times from step 3. enhanced link integrity check fails after 3 mismatches. after the detection of failure of enhanced link integrity check, the f c makes sure that a/v data not requiring protection (low-value content) is available at the gmsl serializer inputs (such as blue or informative screen). alternatively, the force_video and force_audio bits of the gmsl serializer can be used to mask a/v data input of the gmsl serializer. ? ? 6 writes 0 to the encryption_enable bit of the gmsl serializer and deserializer. disables encryption and trans- mits low-value content a/v data. disables decryption and outputs low-value content a/v data. 7 restarts authentication by writing 1 to the reset_hdcp bit followed by writing 1 to the start_authentication bit in the gmsl serializer. ? ? bd-drive rx_r1 c_b tx_b1 display 1 rx_d1 display 2 rx_d2 repeater tx_r1 tx_r2 rx_r2 c_r video routing memory with srm video connectioncontrol connection 1 (c_b in bd-drive is master) control connection 2 (c_r in repeater is master) downloaded from: http:///
________________________________________________________________ maxim integrated products 36 max9266 hdcp gigabit multimedia serial link deserializer with lvds system interface table 14. hdcp authenticaion and normal operation (one repeater, two cs)?first and second parts of the hdcp authentication protocol no. c_b c_r hdcp gmsl serializer (tx_b1, tx_r1, tx_r2) hdcp gmsl deserializer (rx_r1, rx_d1, rx_d2) tx_b1 cds = 0tx_r1 cds = 0 tx_r2 cds = 0 rx_r1 cds = 1rx_d1 cds = 0 rx_d2 cds = 0 1 initial state after power-up. initial state after power-up. all: power-up waiting for hdcp authentication. all: power-up waiting for hdcp authentication. 2 ? writes repeater = 1 in rx_r1. retries until proper acknowledge frame received. note: this step must be completed before the first part of authentication is started between tx_b1 and rx_r1 by the f c_b (step 7). for example, to satisfy this requirement, rx_r1 can be held at power- down until f c_r is ready to write the repeater bit, or f c_b can poll f c_r before starting authentication. ? ? 3 makes sure that a/v data not requiring protection (low- value content) is available at the tx_b1 inputs (such as blue or informative screen). alternatively, the force_ video and force_audio bits of tx_b1 can be used to mask a/v data input of tx_b1. starts the link between tx_b1 and rx_r1 by writing seren = h to tx_b1, or link starts automatically if autos is low. ? tx_b1: starts serialization and transmits low-value content a/v data. rx_r1: locks to incoming data stream and outputs low-value content a/v data. 4 ? starts all downstream links by writing seren = h to tx_r1, tx_r2, or links start automatically if autos of transmitters are low. tx_r1, tx_r2: starts serialization and transmits low-value content a/v data. rx_d1, rx_d2: locks to incoming data stream and outputs low-value content a/v data. downloaded from: http:///
________________________________________________________________ maxim integrated products 37 max9266 hdcp gigabit multimedia serial link deserializer with lvds system interface table 14. hdcp authenticaion and normal operation (one repeater, two cs)?first and second parts of the hdcp authentication protocol (continued) no. c_b c_r hdcp gmsl serializer (tx_b1, tx_r1, tx_r2) hdcp gmsl deserializer (rx_r1, rx_d1, rx_d2) tx_b1 cds = 0tx_r1 cds = 0 tx_r2 cds = 0 rx_r1 cds = 1rx_d1 cds = 0 rx_d2 cds = 0 5 reads the locked bit of rx_r1 and makes sure the link between tx_b1 and rx_r1 is established. reads the locked bit of rx_d1 and makes sure the link between tx_r1 and rx_d1 is established. reads the locked bit of rx_d2 and makes sure the link between tx_r2 and rx_d2 is established. ? ? 6 optionally, writes a random number seed to tx_b1. writes 1 to the gpio_0_function and gpio_1_ function bits in rx_r1 to change gpio functionality used for hdcp purpose. optionally, writes a random-number seed to tx_r1 and tx_r2. ? ? 7 starts and completes the first part of the authentication protocol between tx_b1, rx_r1 (see steps 6?10 in table 11). ? tx_b1: according to commands from f c_b, generates an, computes r0. rx_r1: according to commands from f c_b, computes r0?. 8 ? when gpio_1 = 1 is detected, starts and completes the first part of the authentication protocol between the (tx_r1, rx_d1) and (tx_r2, rx_d2) links (see steps 6?10 in table 11). tx_r1, tx_r2: according to commands from f c_r, generates an, computes r0. rx_d1, rx_d2: according to commands from f c_r, computes r0?. 9 waits for the vsync falling edge and then enables encryption on the (tx_b1, rx_r1) link. full authentication is not complete yet so it makes sure a/v content that needs protection is not transmitted. since repeater = 1 was read from rx_r1, the second part of authentication is required. ? tx_b1: encryption enabled after next vsync falling edge. rx_r1: decryption enabled after next vsync falling edge. downloaded from: http:///
________________________________________________________________ maxim integrated products 38 max9266 hdcp gigabit multimedia serial link deserializer with lvds system interface table 14. hdcp authenticaion and normal operation (one repeater, two cs)?first and second parts of the hdcp authentication protocol (continued) no. c_b c_r hdcp gmsl serializer (tx_b1, tx_r1, tx_r2) hdcp gmsl deserializer (rx_r1, rx_d1, rx_d2) tx_b1 cds = 0tx_r1 cds = 0 tx_r2 cds = 0 rx_r1 cds = 1rx_d1 cds = 0 rx_d2 cds = 0 10 ? when gpio_0 = 1 is detected, enables encryption on the (tx_r1, rx_d1) and (tx_r2, rx_d2) links. tx_r1, tx_r2: encryption enabled after next vsync falling edge. rx_d1, rx_d2: decryption enabled after next vsync falling edge. 11 waits for some time to allow f c_r to make the ksv list ready in rx_r1. then polls (reads) the ksv_list_ready bit of rx_r1 regularly until proper acknowledge frame is received and bit is read as 1. blocks control channel from f c_b side by setting revccen = fwdccen = 0 in rx_r1. retries until proper acknowledge frame received. ? rx_r1: control channel from serializer side (tx_b1) is blocked after fwdccen = revccen = 0 is written. 12 writes bksvs of rx_d1 and rx_d2 to the ksv list in rx_r1. then, calculates and writes the binfo register of rx_r1. ? rx_r1: triggered by f c_r?s write of binfo, calculates hash value (v?) on the ksv list, binfo and the secret- value m0?. 13 writes 1 to the ksv_list_ready bit of rx_r1 and then unblocks the control channel from the f c_b side by setting revccen = fwdccen = 1 in rx_r1. ? rx_r1: control channel from the serializer side (tx_b1) is unblocked after fwdccen = revccen = 1 is written. 14 reads the ksv list and binfo from rx_r1 and writes them to tx_b1. if any of the max_ devs_exceeded or max_ cascade_exceeded bits is 1, then authentication fails. note: binfo must be written after the ksv list. ? tx_b1: triggered by f c_b?s write of binfo, calculates hash value (v) on the ksv list, binfo and the secret- value m0. ? downloaded from: http:///
________________________________________________________________ maxim integrated products 39 max9266 hdcp gigabit multimedia serial link deserializer with lvds system interface detection and action upon new device connection when a new device is connected to the system, the device must be authenticated and the device?s ksv checked against the revocation list. the downstream f cs can set the new_dev_conn bit of the upstream receiver and invoke an interrupt to notify upstream f cs. notification of start of authentication and enable of encryption to downstream links hdcp repeaters do not immediately begin authentication upon startup or detection of a new device, but instead wait for an authentication request from the upstream transmitter/repeaters. use the following procedure to notify downstream links of the start of a new authentication request: 1) host f c begins authentication with the hdcp repeat- er?s input receiver. 2) when aksv is written to hdcp repeater?s input receiver, its auth_started bit is automatically set and its gpio1 goes high (if gpio1_function is set to high). 3) hdcp repeater?s f c waits for a low-to-high transition on hdcp repeater input receiver?s auth_started bit and/or gpio1 (if configured) and starts authenti- cation downstream. 4) hdcp repeater?s f c resets the auth_started bit. set gpio0_function to high to have gpio0 follow the encryption_enable bit of the receiver. the repeater f c can use this function for notification when encryption is enabled/disabled by an upstream f c. table 14. hdcp authenticaion and normal operation (one repeater, two cs)?first and second parts of the hdcp authentication protocol (continued) no. c_b c_r hdcp gmsl serializer (tx_b1, tx_r1, tx_r2) hdcp gmsl deserializer (rx_ r1, rx_d1, rx_d2) tx_b1 cds = 0tx_r1 cds = 0 tx_r2 cds = 0 rx_r1 cds = 1rx_d1 cds = 0 rx_d2 cds = 0 15 reads v from tx_b1 and v? from rx_r1. if they match, continues with authentication; otherwise, retries up to two more times. ? ? ? 16 searches for each ksv in the ksv list and bksv of rx_r1 in the key revocation list. ? ? ? 17 if keys are not revoked, the second part of the authentication protocol is completed. ? ? ? 18 starts transmission of a/v content that needs protection. ? all: perform hdcp encryption on high- value a/v data. all: perform hdcp decryption on high- value a/v data. downloaded from: http:///
________________________________________________________________ maxim integrated products 40 max9266 hdcp gigabit multimedia serial link deserializer with lvds system interface applications information error checking the deserializer checks the serial link for errors and stores the number of detected decoding errors in the 8-bit register, decerr (0x0d). if a large number of 8b/10b decoding or parity errors are detected within a short duration (error rate r 1/4), the deserializer loses lock and stops the error counter. the deserializer then attempts to relock to the serial data. decerr resets upon successful video link lock, successful readout of decerr (through uart), or whenever autoerror reset is enabled. the deserializer does not check for decoding or parity errors during the internal prbs test and decerr is reset to 0x00. err output the deserializer has an open-drain err output. this output asserts low whenever the number of decoding errors exceeds the error threshold errthr (0x0c) dur- ing normal operation, or when at least one prbs error is detected during prbs test. err reasserts high whenever decerr (0x0d) resets due to decerr readout, video link lock, or autoerror reset. autoerror reset the default method to reset errors is to read the respective error registers in the deserializer (0x0d, 0x0e). autoerror reset clears the decoding error counter decerr and the err output ~1 f s after err goes low. autoerror reset is disabled on power-up. enable autoerror reset through autorst (0x06, d6). autoerror reset does not run when the device is in prbs test mode. prbs self-test the gmsl serializer/deserializer link includes a prbs pattern generator and a bit-error verification function. first, disable the glitch filters (set disvsfilt, dishsfilt to 1) in the deserializer. next, disable vsync/hsync inversion in both the gmsl serializer and deserializer (set invvsync, invhsync to 0). then, set prbsen = 1 (0x04, d5) in the gmsl serializer and then the deserial- izer to start the prbs self-test. set prbsen = 0 (0x04, d5) first in the deserializer and then the gmsl serializer to exit the prbs self-test. the deserializer uses an 8-bit register (0x0e) to count the number of detected errors. the control link also controls the start and stop of the error counting. during prbs mode, the device does not count decoding errors and the deserializer err output reflects prbs errors only. microcontrollers on both sides of the gmsl link (dual c control) usually the microcontroller is either on the gmsl serial- izer side for video-display applications or on the deserial- izer side for image-sensing applications. for the former case, both the cds pins of the gmsl serializer and deserializer are set to low, and for the latter case, the cds pins are set to high. however, if the cds pin of the gmsl serializer is low and the same pin of the deserial- izer is high, then the gmsl serializer/deserializer connect to both f cs simultaneously. in such a case, the f cs on either side can communicate with the gmsl serializer and deserializer. contentions of the control link can happen if the f cs on both sides are using the link at the same time. the gmsl serializer/deserializer do not provide the solution for con- tention avoidance. the serializer/deserializer do not send an acknowledge frame when communication fails due to contention. users can always implement a higher layer protocol to avoid the contention. in addition, if uart communication across the serial link is not required, the f cs can disable the forward and reverse control channel through the fwdccen and revccen bits (0x04, d[1:0]) in the gmsl serializer/deserializer. uart communication across the serial link is stopped and contention between f cs no longer occurs. during dual f c operation, if one of the cds pins on either side changes state, the link resumes the corresponding state described in the link startup procedure section. as an example of dual f c use in an image-sensing appli- cation, the gmsl serializer can be in sleep mode an d waiting for wake-up by the deserializer. after wake -up, the serializer-side f c sets the gmsl serializer?s cds pin low and assumes master control of the serializer?s regi sters. hsync/vsync glitch filter the deserializer contains one-cycle glitch filters on hsync and vsync. this eliminates single-cycle glitches in hsync and vsync that can cause a loss of hdcp synchronization between the gmsl serializer and dese- rializer while encryption is enabled. the glitch filters are on by default. write to d[1:0] of register 0x08 in the dese- rializer to disable the glitch filters for hsync or vsync. the glitch filter, when active, suppresses all single-cycle- wide pulses sent. disable the glitch filter before running prbs ber tests. the internal ber checker assumes that the incoming bit stream is unaltered prbs data. downloaded from: http:///
________________________________________________________________ maxim integrated products 41 max9266 hdcp gigabit multimedia serial link deserializer with lvds system interface changing the clock frequency both the video clock rate (f txclkout_ ) and the control- channel clock rate (f uart ) can be changed on the fly to support applications with multiple clock speeds. it is rec- ommended to enable the serial link after the video clock stabilizes. stop the video clock for 5 f s and restart the serial link or toggle seren after each change in th e video clock frequency to recalibrate any automatic settin gs if a clean frequency change cannot be guaranteed. the reverse control channel remains unavailable for 350 f s after serial link start or stop. limit on-the-fly c hanges in f uart to factors of less than 3.5 at a time to ensure th at the device recognizes the uart sync pattern. for ex am- ple, when lowering the uart frequency from 1mbps to 100kbps, first send data at 333kbps and then at 100 kbps to have reduction ratios of 3 and 3.333, respective ly. do not interrupt txclkout_ or change its frequency while encryption is enabled; otherwise, hdcp synchronizat ion is lost and authentication must be repeated. to cha nge the txclkout_ frequency, stop the high-value conten t a/v data. then disable encryption in the gmsl seria lizer/ deserializer within the same vsync cycle?encryption stops at the next vsync falling edge. txclkout_ can now be changed/stopped. reenable encryption before sending any high-value content a/v data. fast detection of loss-of-synchronization a measure of link quality is the recovery time from loss- of-hdcp synchronization. with the gmsl, it is likely that hdcp synchronization will not be lost unless the gmsl synchronization is lost. the host can be quickly notified of loss-of-lock by connecting the deserializer lock output to the int input. if other sources use the interrupt input, such as a touch-screen controller, the f c can implement a routine to distinguish between interrupts from loss- of-sync and normal interrupts. reverse control-channel communication does not require an active forward link to operate and accurately tracks the lock status of the gmsl link. lock asserts for video link only and not for the configuration link. programming the device addresses both the gmsl serializer and the deserializer have programmable device addresses. this allows multiple gmsl devices along with i 2 c peripherals to coexist on the same control channel. the serializer device address is stored in register 0x00 of each device, while the dese- rializer device address is stored in register 0x01 of each device. to change the device address, first write to the device whose address changes (register 0x00 of the gmsl serializer for serializer device-address change, or register 0x01 of the deserializer for deserializer device- address change). then write the same address into the corresponding register on the other device (register 0x00 of the deserializer for serializer device-address change, or register 0x01 of the gmsl serializer for deserializer device-address change). 3-level inputs for default device address add0 and add1 are 3-level inputs that control the dese- rializer?s default-device slave addresses (see table 2 ). connect add0/add1 through a pullup resistor to iovdd, a pulldown resistor to gnd, or a high-impedance con- nection. for digital control, use three-state logic to drive the 3-level logic inputs. add0/add1 set the device addresses in the deserializer only and not the gmsl serializer. set the gmsl serial- izer?s add0/add1 inputs to the same settings as the deserializer; alternatively, write to register 0x00 and 0x01 of the gmsl serializer to reflect any changes made due to the 3-level inputs. configuration blocking the deserializer can block changes to the non-hdcp registers. set cfgblock to make all non-hdcp regis- ters read only. once set, the registers remain blocked until the supplies are removed or until pwdn is low. backward compatibility the deserializer is backward compatible with the no n- hdcp max9268 deserializer with the following except ions: ? uart packet delay at power-up: the f c must wait 2.7ms before sending the first uart packet to the deserializer. this delay is < 200 f s for the max9268. ? glitch filters: the deserializer includes one-cycle glitch filters on hs and vs. for backward compat- ibility, disable the glitch filters by setting d[1:0] of register 0x08 to 0. the pinouts and packages are the same for both devices. see table 3 and the pin description section for backward-compatible pin mapping. downloaded from: http:///
________________________________________________________________ maxim integrated products 42 max9266 hdcp gigabit multimedia serial link deserializer with lvds system interface key memory each device has a unique hdcp key set that is stored in secure nonvolatile memory (nvm). the hdcp key set consists of forty 56-bit private keys and one 40-bit public key. the nvm is qualified for automotive applications. gpios the deserializer has two open-drain gpios available . when not used for hdcp purposes (see the notification of start of authentication and enable of encryption to downs tream links section), gpio1out and gpio0out (0x06, d3 and d1) set the output state of the gpios. the gpio inp ut buffers are always enabled. the input states are st ored in gpio1 and gpio0 (0x06, d2 and d0). set gpio1out/ gpio0out to 1 when using gpio1/gpio0 as an input. internal input pulldowns the control and configuration inputs on the deserializer include an active pulldown to gnd. pulldowns are dis- abled when the device is shut down ( pwdn = low) or put into sleep mode. during power-up, keep all inputs driven or use external pullup/pulldown resistors to prevent addi- tional current consumption and undesired configuration due to undefined inputs. choosing i 2 c/uart pullup resistors both i 2 c/uart open-drain lines require pullup resistors to provide a logic-high level. there are trade-offs between power dissipation and speed, and a compromise made in choosing pullup resistor values. every device connect- ed to the bus introduces some capacitance even when the device is not in operation. i 2 c specifies 300ns rise times to go from low to high (30% to 70%) for fast mode, which is defined for data rates up to 400kbps (see the i 2 c specifications in the dc electrical characteristics and ac electrical characteristics tables for details). to meet the fast-mode rise-time requirement, choose the pullup resis- tors so rise time t r = 0.85 x r pullup x c bus < 300ns. the waveforms are not recognized if the transition time becomes too slow. the deserializer supports i 2 c/uart rates up to 1mbps. ac-coupling ac-coupling isolates the receiver from dc voltages up to the voltage rating of the capacitor. four capacitors (two at the serializer output and two at the deserializer input) are needed for proper link operation and to provide protection if either end of the cable is shorted to a high voltage. ac-coupling blocks low-frequency ground shifts and low-frequency common-mode noise. selection of ac-coupling capacitors voltage droop and the digital sum variation (dsv) of transmitted symbols cause signal transitions to start from different voltage levels. because the transition time is finite, starting the signal transition from different volt- age levels causes timing jitter. the time constant for an ac-coupled link needs to be chosen to reduce droop and jitter to an acceptable level. the rc network for an ac-coupled link consists of the cml receiver termination resistor (r tr ), the cml driver termination resistor (r td ), and the series ac-coupling capacitors (c). the rc time constant for four equal-value series capacitors is (c x (r td + r tr ))/4. r td and r tr are required to match the transmission line impedance (usually 100 i ). this leaves the capacitor selection to change the system time con- stant. use at least 0.2 f f high-frequency surface-mount ceramic capacitors, with sufficient voltage rating to with- stand a short to battery, to pass the lower speed reverse control-channel signal. use capacitors with a case size less than 3.2mm x 1.6mm to have lower parasitic effects to the high-speed signal. power-supply circuits and bypassing the deserializer uses an avdd and dvdd of 3.0v to 3.6v. all single-ended inputs and outputs on the dese- rializer derive power from a 1.7v to 3.6v v iovdd , which scales with iovdd. proper voltage-supply bypassing is essential for high-frequency circuit stability. cables and connectors interconnect for cml typically has a differential i mped- ance of 100 i . use cables and connectors that have matched differential impedance to minimize impedanc e discontinuities. twisted-pair and shielded twisted- pair cables tend to generate less emi due to magnetic-fi eld canceling effects. balanced cables pick up noise as com- table 15. suggested connectors and cables for gmsl vendor connector cable jae electronics, inc. mx38-ff a-bw-lxxxxx nissei electric co., ltd. gt11l-2s f-2wme awg28 rosenberger hochfrequenztechnik gmbh d4s10a-40ml5-z dacar 538 downloaded from: http:///
________________________________________________________________ maxim integrated products 43 max9266 hdcp gigabit multimedia serial link deserializer with lvds system interface mon mode rejected by the cml receiver. table 15 lists the suggested cables and connectors used in the gmsl li nk. board layout separate the digital signals and cml/lvds high-speed signals to prevent crosstalk. use a four-layer pcb with separate layers for power, ground, cml/lvds, and digi- tal signals. lay out pcb traces close to each other for a 100 i differential characteristic impedance. the trace dimensions depend on the type of trace used (microstrip or stripline). note that two 50 i pcb traces do not have 100 i differential impedance when brought close togeth- er because the impedance goes down when the traces are brought closer. route the pcb traces for a cml/lvds channel (there are two conductors per cml/lvds channel) in parallel to maintain the differential characteristic impedance. avoid vias. keep pcb traces that make up a differential pair equal length to avoid skew within the differential pair. esd protection the deserializer esd tolerance is rated for human body model, iec 61000-4-2, and iso 10605. the iso 10605 and iec 61000-4-2 standards specify esd tolerance for electronic systems. the serial link i/o are tested for iso 10605 esd protection and iec 61000-4-2 esd protec- tion. all pins are tested for the human body model. the human body model discharge components are c s = 100pf and r d = 1.5k i ( figure 25 ). the iec 61000-4-2 discharge components are c s = 150pf and r d = 330 i ( figure 26 ). the iso 10605 discharge components are c s = 330pf and r d = 2k i ( figure 27 ). figure 25. human body model esd test circuit figure 26. iec 61000-4-2 contact discharge esd test circuit figure 27. iso 10605 contact discharge esd test circuit storagecapacitor high- voltage dc source device under test charge-current- limit resistor discharge resistance 1m i r d 1.5k i c s 100pf c s 150pf storagecapacitor high- voltage dc source device under test charge-current- limit resistor discharge resistance r d 330 i storagecapacitor high- voltage dc source device under test charge-current- limit resistor discharge resistance r d 2k i c s 330pf downloaded from: http:///
________________________________________________________________ maxim integrated products 44 max9266 hdcp gigabit multimedia serial link deserializer with lvds system interface table 16. gmsl core register table (see table 1 ) register address bits name value function default value 0x00 d[7:1] serid xxxxxxx serializer device address. power-up default address determined by add0 and add1 (see table 2). 1000000 d0 ? 0 reserved 0 0x01 d[7:1] desid xxxxxxx deserializer device address. power-up default address determined by add0 and add1 (see table 2). 1001000 d0 cfgblock 0 normal operation 0 1 registers 0x00 to 0x1f are read only 0x02 d[7:6] ss 00 no spread spectrum. power-up default when ssen = low. 00, 01 01 q 2% spread spectrum. power-up default when ssen = high 10 no spread spectrum 11 q 4% spread spectrum d5 ? 0 reserved 0 d4 audioen 0 disable i 2 s channel 1 1 enable i 2 s channel d[3:2] prng 00 12.5mhz to 25mhz pixel clock 11 01 25mhz to 50mhz pixel clock 10 50mhz to 104mhz pixel clock 11 automatically detect the pixel clock range d[1:0] srng 00 0.5gbps to 1gbps serial-data rate 11 01 1gbps to 2gbps serial-data rate 10 2gbps to 3.125gbps serial-data rate 11 automatically detect serial-data rate 0x03 d[7:6] autofm 00 calibrate spread-modulation rate only once after locking 00 01 calibrate spread-modulation rate every 2ms after locking 10 calibrate spread-modulation rate every 16ms after locking 11 calibrate spread-modulation rate every 256ms after locking d5 ? 0 reserved 0 d[4:0] sdiv 00000 autocalibrate sawtooth divider 00000 xxxxx manual sdiv setting (see the manual programming of the spread-spectrum divider section) downloaded from: http:///
________________________________________________________________ maxim integrated products 45 max9266 hdcp gigabit multimedia serial link deserializer with lvds system interface table 16. gmsl core register table (see table 1 ) (continued) register address bits name value function default value 0x04 d7 locked 0 lock output is low 0 (read only) 1 lock output is high d6 outenb 0 enable outputs 0 1 disable outputs d5 prbsen 0 disable prbs test 0 1 enable prbs test d4 sleep 0 normal mode (default value depends on cds and ms pin values at power-up) 0, 1 1 activate sleep mode (default value depends on cds and ms pin values at power-up) d[3:2] inttype 00 base mode uses i 2 c peripheral interface 00 01 base mode uses uart peripheral interface 10, 11 base mode peripheral interface disabled d1 revccen 0 disable reverse control channel to serializer (sending) 1 1 enable reverse control channel to serializer (sending) d0 fwdccen 0 disable forward control channel from serializer (r eceiving) 1 1 enable forward control channel from serializer (re ceiving) 0x05 d7 i2cmethod 0 i 2 c conversion sends the register address 0 1 disable sending of i 2 c register address (command- byte-only mode) d[6:5] hpftune 00 7.5mhz equalizer highpass cutoff frequency 01 01 3.75mhz cutoff frequency 10 2.5mhz cutoff frequency 11 1.87mhz cutoff frequency d4 pdhf 0 high-frequency boosting enabled 0 1 high-frequency boosting disabled d[3:0] eqtune 0000 2.1db equalizer boost gain 0100, 1001 0001 2.8db equalizer boost gain 0010 3.4db equalizer boost gain 0011 4.2db equalizer boost gain 0100 5.2db equalizer boost gain. power-up default when eqs = high. 0101 6.2db equalizer boost gain 0110 7db equalizer boost gain 0111 8.2db equalizer boost gain 1000 9.4db equalizer boost gain 1001 10.7db equalizer boost gain. power-up default when eqs = low. 1010 11.7db equalizer boost gain 1011 13db equalizer boost gain 11xx do not use downloaded from: http:///
________________________________________________________________ maxim integrated products 46 max9266 hdcp gigabit multimedia serial link deserializer with lvds system interface table 16. gmsl core register table (see table 1 ) (continued) register address bits name value function default value 0x06 d7 ? 0 reserved 0 d6 autorst 0 do not automatically reset error registers and outputs 0 1 automatically reset error registers and outputs d5 disint 0 enable interrupt transmission to serializer 0 1 disable interrupt transmission to serializer d4 int 0 int input = low (read only) 0 (read only) 1 int input = high (read only) d3 gpio1out 0 output low to gpio1 1 1 output high to gpio1 d2 gpio1 0 gpio1 is low 1 (read only) 1 gpio1 is high d1 gpio0out 0 output low to gpio0 1 1 output high to gpio0 d0 gpio0 0 gpio0 is low 1 (read only) 1 gpio0 is high 0x07 d[7:0] ? 01010100 reserved 01010100 0x08 d[7:2] ? 00110000 reserved 001100 d1 disvsfilt 0 vsync glitch filter active 0 1 vsync glitch filter disabled d0 dishsfilt 0 hsync glitch filter active 0 1 hsync glitch filter disabled 0x09 d[7:0] ? 11001000 reserved 11001000 0x0a d[7:0] ? 00010010 reserved 00010010 0x0b d[7:0] ? 00100000 reserved 00100000 0x0c d[7:0] errthr xxxxxxxx error threshold for decoding errorserr = low when decerr > errthr 00000000 0x0d d[7:0] decerr xxxxxxxx decoding error counterthis counter remains zero while the device is in prbs test mode 00000000 (read only) 0x0e d[7:0] prbserr xxxxxxxx prbs error counter 00000000 (read only) 0x12 d7 mclksrc 0 mclk derived from txclkout_ (see table 5) 0 1 mclk derived from internal oscillator d[6:0] mclkdiv 0000000 mclk disabled 0000000 xxxxxxx mclk divider 0x13 d[7:5] ? xxx reserved (read only) d[4:0] ? 10000 reserved 10000 downloaded from: http:///
________________________________________________________________ maxim integrated products 47 max9266 hdcp gigabit multimedia serial link deserializer with lvds system interface table 16. gmsl core register table (see table 1 ) (continued) x = don?t care. register address bits name value function default value 0x14 d7 invvsync 0 deserializer does not invert vsync 0 1 deserializer inverts vsync d6 invhsync 0 deserializer does not invert hsync 0 1 deserializer inverts hsync d5 forcelvds 0 normal operation 0 1 force lvds outputs low d4 dcs 0 normal driver current for cmos outputs (ws, sck, sd/cntl0, cntl1, cntl2/mclk) 0 1 strong driver current for cmos outputs (ws, sck, sd/cntl0, cntl1, cntl2/mclk) d3 discntl1 0 serial-data bit 27 is mapped to cntl1 1 1 cntl1 forced low d2 disres 0 serial-data bit 27 is mapped to res 0 1 res bit forced low d[1:0] ilvds 00 1.75ma lvds current 01 01 3.5ma lvds current 10 do not use 11 7ma lvds current 0x1e d[7:0] id 00001000 device identifier(max9266 = 0x08) 00001000 (read only) 0x1f d[7:5] ? 000 reserved 000 (read only) d4 caps 0 not hdcp capable 1 (read only) 1 hdcp capable d[3:0] revision xxxx device revision (read only) downloaded from: http:///
________________________________________________________________ maxim integrated products 48 max9266 hdcp gigabit multimedia serial link deserializer with lvds system interface table 17. hdcp register table (see table 1 ) register address size (bytes) name read/ write function default value (hex) 0x80 to 0x84 5 bksv read only hdcp receiver ksv (read only) 0x85 to 0x86 2 ri? read only link verification response (read only) 0x87 1 pj? read only enhanced link verification response (read only) 0x88 to 0x8f 8 an read/write session random number 0x0000000000000000 0x90 to 0x94 5 aksv read/write hdcp transmitter ksv 0x0000000000 0x95 1 bctrl read/write d7 = pd_hdcp1 = power down hdcp circuits 0 = hdcp circuits normal 0x00 d[6:4] = reservedd3 = gpio1_function 1 = gpio1 mirrors auth_started 0 = normal gpio1 operation d2 = gpio0_function 1 = gpio0 mirrors encryption_enable 0 = normal gpio0 operation d1 = auth_started 1 = authentication started (triggered by write to aksv) 0 = authentication not started d0 = encryption_enable 1 = enable encryption 0 = disable encryption 0x96 1 bstatus read/write d[7:2] = reserved 0x00 d1 = new_dev_conn1 = set to 1 if a new connected device is detected 0 = set to 0 if no new device is connected d0 = ksv_list_ready 1 = set to 1 if ksv list and binfo is ready 0 = set to 0 if ksv list or binfo is not ready 0x97 1 bcaps read/write d[7:1] = reserved 0x00 d0 = repeater1 = set to 1 if device is a repeater 0 = set to 0 if device is not a repeater 0x98 to 0x9f 8 ? read only reserved 0x0000000000000000 (read only) downloaded from: http:///
________________________________________________________________ maxim integrated products 49 max9266 hdcp gigabit multimedia serial link deserializer with lvds system interface table 17. hdcp register table (see table 1 ) (continued) register address size (bytes) name read/ write function default value (hex) 0xa0 to 0xa3 4 v?.h0 read/write h0 part of sha-1 hash value 0x00000000 0xa4 to 0xa7 4 v?.h1 read/write h1 part of sha-1 hash value 0x00000000 0xa8 to 0xab 4 v?.h2 read/write h2 part of sha-1 hash value 0x00000000 0xac to 0xaf 4 v?.h3 read/write h3 part of sha-1 hash value 0x00000000 0xb0 to 0xb3 4 v?.h4 read/write h4 part of sha-1 hash value 0x00000000 0xb4 to 0xb5 2 binfo read/write d[15:12] = reserved 0x0000 d11 = max_cascade_exceeded1 = set to 1 if more than seven cascaded devices attached 0 = set to 0 if seven or fewer cascaded devices attached d[10:8] = depth depth of cascaded devices d7 = max_devs_exceeded 1 = set to 1 if more than 14 devices attached 0 = set to 0 if 14 or fewer devices attached d[6:0] = device_count number of devices attached 0xb6 1 gpmem read/write general-purpose memory byte 0x00 0xb7 to 0xb9 3 ? read only reserved 0x000000 0xba to 0xff 70 ksv_list read/write list of ksv?s downstream repeaters and receivers (maximum of 14 devices) all zero downloaded from: http:///
________________________________________________________________ maxim integrated products 50 max9266 hdcp gigabit multimedia serial link deserializer with lvds system interface typical application circuit ordering information /v denotes an automotive qualified part. + denotes a lead(pb)-free/rohs-compliant package. * ep = exposed pad. t = tape and reel. package information for the latest package outline information and land patterns (footprints), go to www.maxim-ic.com/packages . note that a ?+?, ?#?, or ?-? in the package code indicates rohs status only. package drawings may show a different suffix character, but the drawing pertains to the package regardless of rohs status. chip information process: cmos part temp range pin-package max9266gcm/v+ -40 n c to +105 n c 48 tqfp-ep* max9266gcm/v+t -40 n c to +105 n c 48 tqfp-ep* package type package code outline no. land pattern no. 48 tqfp-ep c48e+8 21-0065 90-0138 ws lflt intms sck sd tx rx tclkout+/- txout0+/- to txout2+/- cds int rx/sda tx/scl lock ws sck sd/cntl0 sd sck ws sda scl cdsautos rx/sda in+in- in to peripherals display display application note: not all pullup/pulldown resistors are shown. see pin description for details. rx0+/-to rx2+/- rxclk+/- out pll out+ 45k i 45k i 5k i 5k i 50k i 50k i lmn1lmn0 out- tx/scllflt int ms add0add1 wssck sd/cntl0 txclk+/- rxclkin+/- rxin0+/-to rxin2+/- tx0+/- to tx2+/- gpu ecu mclk uartaudio max9265 max9266 max9850 downloaded from: http:///
maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim product. no circuit patent licenses are implied. maxim reserves the right to change the circuitry and specifications without notice at any time. maxim integrated products, 120 san gabriel drive, sunnyvale, ca 94086 408-737-7600 51 ? 2011 maxim integrated products maxim is a registered trademark of maxim integrated products, inc. max9266 hdcp gigabit multimedia serial link deserializer with lvds system interface revision history revision number revision date description pages changed 0 3/11 initial release ? downloaded from: http:///

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