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? 2006 microchip technology inc. ds22004b-page 1 mcp6g01/1r/1u/2/3/4 features 3 gain selections: - +1, +10, +50 v/v one gain select input per amplifier rail-to-rail input and output low gain error: 1% (max.) high bandwidth: 250 khz to 900 khz (typ.) low supply current: 110 a (typ.) single supply: 1.8v to 5.5v extended temperature range: -40c to +125c typical applications a/d converter driver industrial instrumentation bar code readers metering digital cameras block diagram description the microchip technology inc. mcp6g01/1r/1u/2/3/4 are analog selectable gain amplifiers (sga). they can be configured for gains of +1 v/v, +10 v/v, and +50 v/v through the gain select input pin(s). the chip select pin on the mcp6g03 can put it into shutdown to conserve power. these sgas are optimized for single supply applications requiring reasonable quiescent current and speed. the single amplifiers mcp6g01, mcp6g01r, mcp6g01u, and mcp6g03, are available in 5-pin sot-23 package and the dual amplifier mcp6g02, are available in 8-pin soic and msop packages. the quad amplifier mcp6g04 is available in 14-pin soic and tssop packages. all parts are fully specified from -40c to +125c. package types v out v dd gsel v in v ss 3 r f r g gain select logic gain switches resistor ladder (r lad ) gain (v/v) gsel voltage (typ.) (v) 1v dd /2 (or open) 10 0 50 v dd note: v ss is assumed to be 0v cs (mcp6g03 only) 5m v in gsel v ss v out v dd 12 3 4 8 76 5 ncnc nc gsel a v outa v ina gsel c v inc 12 3 4 1413 12 11 v ss v outc gsel d 56 7 10 98 v dd gsel b v outd v outb v ind v inb mcp6g01 soic, msop v ina gsel a v ss gsel b v outb 12 3 4 8 76 5 v dd v inb v outa mcp6g02 soic, msop mcp6g04 soic, tssop v in gsel v ss v out v dd 12 3 4 8 76 5 cs nc nc mcp6g03 soic, msop v dd 12 3 54 v ss v out v in gsel mcp6g01r sot-23-5 v ss 12 3 54 v dd v in gsel v out mcp6g01u sot-23-5 v ss 12 3 54 v dd v out v in gsel mcp6g01 sot-23-5 110 a selectable gain amplifier downloaded from: http:///
mcp6g01/1r/1u/2/3/4 ds22004b-page 2 ? 2006 microchip technology inc. 1.0 electrical characteristics absolute maximum ratings ? v dd Cv ss ........................................................................7.0v current at analog input pin (v in ) ...................................... 2ma analog input (v in ) ?? ..................... v ss C1.0vtov dd +1.0v all other inputs and outputs........... v ss C0.3vtov dd +0.3v output short circuit current...................................continuous current at output and supply pins ................................ 30 ma storage temperature.....................................-65c to +150c junction temperature.................................................. +150c esd protection on all pins (hbm; mm) ................ 4 kv; 200v ? notice: stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rati ng only and functional operation of the device at those or any other conditions above those indicated in the operational listi ngs of this specification is not implied. exposure to maximu m rating conditions for extended periods may affect device reliability. ?? see section 4.1.4 input voltage and current limits . dc electrical characteristics electrical specifications: unless otherwise indicated, t a = +25c, v dd = +1.8v to +5.5v, v ss = gnd, g = +1 v/v, v in = (0.3v)/g, r l = 100 k to v dd /2, gsel = v dd /2, and cs is tied low. parameters sym min typ max units conditions amplifier inputs (v in ) input offset voltage v os C4.5 1.0 +4.5 mv g = +1 1.0 mv g = +10, +50 input offset voltage drift v os / t a 2 v/c g = +1, t a = -40c to +125c power supply rejection ratio psrr 65 80 db g = +1 (note 1) input bias current i b 1 p a input bias current at i b 3 0 p at a = +85c temperature i b 1000 5000 pa t a = +125c input impedance z in 1 0 13 ||6 ||pf amplifier gain nominal gains g 1 to 50 v/v +1, +10 or +50 dc gain error g = +1 g e C0.3 +0.3 % v out 0.3v to v dd ? 0.3v g +10 g e C1.0 +1.0 % v out 0.3v to v dd ? 0.3v dc gain drift g = +1 g/ t a 1p p m / ct a = -40c to +125c g +10 g/ t a 4p p m / ct a = -40c to +125c ladder resistance (note 1) ladder resistance r lad 200 350 500 k ladder resistance across temperature r lad / t a C1800 ppm/c t a = -40c to +125c amplifier output dc output non-linearity g = +1 v onl C0.2 +0.2 % of fsr v out = 0.3v to v dd C0.3v, v dd =1.8v v onl C0.1 +0.1 % of fsr v out = 0.3v to v dd C0.3v, v dd =5.5v dc output non-linearity, g = +10, +50 v onl C0.05 +0.05 % of fsr v out = 0.3v to v dd C0.3v maximum output voltage swing v oh , v ol v ss +10 v dd C10 mv g = +1; 0.3v output overdrive v oh , v ol v ss +10 v dd C10 mv g +10; 0.5v output overdrive short circuit current i sc 7 m av dd = 1.8v i sc 2 0 m av dd = 5.5v note 1: r lad (r f +r g in figure 4-1 ) connects v ss , v out , and the inverting input of the internal amplifier. thus, v ss is coupled to the internal amplifier and the psrr spec des cribes psrr+ only. it is recommended that the v ss pin be tied directly to ground to avoid noise problems. 2: i q includes current in r lad (typically 0.6 a at v out = 0.3v), and excludes digital switching currents. downloaded from: http:///
? 2006 microchip technology inc. ds22004b-page 3 mcp6g01/1r/1u/2/3/4 power supply supply voltage v dd 1.8 5.5 v quiescent current per amplifier i q 60 110 170 a i o = 0 (note 2) dc electrical characte ristics (continued) electrical specifications: unless otherwise indicated, t a = +25c, v dd = +1.8v to +5.5v, v ss = gnd, g = +1 v/v, v in = (0.3v)/g, r l = 100 k to v dd /2, gsel = v dd /2, and cs is tied low. parameters sym min typ max units conditions note 1: r lad (r f +r g in figure 4-1 ) connects v ss , v out , and the inverting input of the internal amplifier. thus, v ss is coupled to the internal amplifier and the psrr spec des cribes psrr+ only. it is recommended that the v ss pin be tied directly to ground to avoid noise problems. 2: i q includes current in r lad (typically 0.6 a at v out = 0.3v), and excludes digital switching currents. ac electrical characteristics electrical specifications: unless otherwise indicated, t a = +25c, v dd = +1.8v to +5.5v, v ss = gnd, g = +1 v/v, v in = (0.3v)/g, r l = 100 k to v dd /2, c l = 60 pf, gsel = v dd /2, and cs is tied low. parameters sym min typ max units conditions frequency response -3db bandwidth bw 900 khz g = +1, v out < 100 mv p-p (note 1) bw 350 khz g = +10, v out < 100 mv p-p (note 1) bw 250 khz g = +50, v out < 100 mv p-p (note 1) gain peaking gpk 0.3 db g = +1; v out < 100 mv p-p gpk 0 db g = +10, v out < 100 mv p-p gpk 0.7 db g = +50; v out < 100 mv p-p total harmonic distortion plus noise f = 1 khz, g = +1 v/v thd+n 0.0029 % v out = 1.75v 1.4v pk , v dd = 5.0v, bw = 80 khz f = 1 khz, g = +10 v/v thd+n 0.18 % v out = 2.5v 1.4v pk , v dd = 5.0v, bw = 80 khz f = 1 khz, g = +50 v/v thd+n 1.3 % v out = 2.5v 1.4v pk , v dd = 5.0v, bw = 80 khz step response slew rate sr 0.50 v/s g = 1 sr 2.3 v/s g = 10 sr 4.5 v/s g = 50 noise input noise voltage e ni 9 v p-p f = 0.1 hz to 10 hz (note 2) e ni 5 0 v p-p f = 0.1 hz to 30 khz (note 2) input noise voltage density e ni 3 8n v / hz g = +1 v/v, f = 10 khz (note 2) e ni 4 6n v / hz g = +10 v/v, f = 10 khz (note 2) e ni 4 1n v / hz g = +50 v/v, f = 10 khz (note 2) input noise current density i ni 4 f a / hz f = 10 khz note 1: see table 4-1 for a list of typical numbers and figure 2-31 for the frequency response versus gain. 2: e ni and e ni include ladder resistance thermal noise. downloaded from: http:///
mcp6g01/1r/1u/2/3/4 ds22004b-page 4 ? 2006 microchip technology inc. digital electrical characteristics electrical specifications: unless otherwise indicated, t a = 25c, v dd = +1.8v to +5.5v, v ss = gnd, g = +1 v/v, v in = (0.3v)/g, r l = 100 k to v dd /2, c l = 60 pf, gsel = v dd /2, and cs is tied low. parameters sym min typ max units conditions cs low specifications cs logic threshold, low v csl 0 0.2v dd vc s = 0v cs input current, low i csl 3 0p ac s = 0v cs high specifications cs logic threshold, high v csh 0.8v dd v dd vc s = v dd cs input current, high i csh 0 . 8 ac s = v dd = 5.5v quiescent current per amplifier, shutdown mode (i dd ) i dd_shdn 120 pa cs = v dd , mcp6g03 quiescent current per amplifier, shutdown mode (i ss ) (note 3) i ss_shdn C2.4 a cs = v dd = 1.8v, mcp6g03 i ss_shdn C7.2 a cs = v dd = 5.5v, mcp6g03 cs dynamic specifications input capacitance c cs 1 0p f input rise/fall times t csrf 2 s (note 2) cs low to amplifier output high turn-on time t cson 40 s g = +1 v/v, v dd = 1.8v, v in = 0.9v dd cs = 0.2v dd to v out = 0.8v dd t cson 7 s g = +1 v/v, v dd = 5.5v, v in = 0.9v dd cs = 0.2v dd to v out = 0.8v dd cs high to amplifier output high-z turn-off time t csoff 30 s g = +1 v/v, v in = v dd /2, cs = 0.8v dd to v out = 0.1v dd /2 hysteresis v cshy 0 . 4 0 vv dd = 1.8v v cshy 0 . 5 5 vv dd = 5.5v gsel specifications (note 1) gsel logic threshold, low v gsl 0.15v dd 0.35v dd v gain changes between 1 and 10, i gsel = 0 gsel logic threshold, high v gsh 0.65v dd 0.85v dd v gain changes between 1 and 50, i gsel = 0 gsel input current, low i gsl C10 C1.5 a gsel voltage = 0.3v dd gsel input current, high i gsh +1.5 +10 a gsel voltage = 0.7v dd gsel dynamic specifications (note 1) input capacitance c gsel 8p f input rise/fall times t gsrf 10 s (note 2) hysteresis v gshy 4 5m v v dd = 1.8v v gshy 9 5m v v dd = 5.5v gsel low to valid output time, g = +1 to +10 select t gsl1 10 s v in = 150 mv, gsel = 0.25v dd to v out = 1.37v gsel middle to valid output time, g = +10 to +1 select t gsm10 12 s v in = 150 mv, gsel = 0.25v dd to v out = 0.28v gsel high to valid output time, g = +1 to +50 select t gsh1 9 s v in = 30 mv, gsel = 0.75v dd to v out = 1.35v gsel middle to valid output time, g = +50 to +1 select t gsm50 8 s v in = 30 mv, gsel = 0.75v dd to v out = 0.18v note 1: gsel is a tri-level input pin. the gain is 10 when its voltage is low, 1 when it is at mid-suppy, and 50 when it is high. 2: not tested in production. set by design and characterization. 3: i ss_shdn includes the current through the cs pin, r l and r lad , and excludes digital switchi ng currents. the block dia- gram on the from page shows these current paths (through v ss ). downloaded from: http:///
? 2006 microchip technology inc. ds22004b-page 5 mcp6g01/1r/1u/2/3/4 figure 1-1: gain select timing diagram. gsel high to valid output time, g = +10 to +50 select t gsh10 12 s v in = 30 mv, gsel = 0.75v dd to v out = 1.38v gsel low to valid output time, g = +50 to +10 select t gsl50 9 s v in = 30 mv, gsel = 0.25v dd to v out = 0.42v digital electrical chara cteristics (continued) electrical specifications: unless otherwise indicated, t a = 25c, v dd = +1.8v to +5.5v, v ss = gnd, g = +1 v/v, v in = (0.3v)/g, r l = 100 k to v dd /2, c l = 60 pf, gsel = v dd /2, and cs is tied low. parameters sym min typ max units conditions note 1: gsel is a tri-level input pin. the gain is 10 when its voltage is low, 1 when it is at mid-suppy, and 50 when it is high. 2: not tested in production. set by design and characterization. 3: i ss_shdn includes the current through the cs pin, r l and r lad , and excludes digital switchi ng currents. the block dia- gram on the from page shows these current paths (through v ss ). temperature characteristics electrical specifications: unless otherwise indicated, v dd = +1.8v to +5.5v, and v ss = gnd. parameters sym min typ max units conditions temperature ranges specified temperature range t a C40 +125 c operating temperature range t a C40 +125 c (note 1) storage temperature range t a C65 +150 c thermal package resistances thermal resistance, 5l-sot-23 ja 256 c/w thermal resistance, 8l-soic ja 163 c/w thermal resistance, 8l-msop ja 206 c/w thermal resistance, 14l-soic ja 120 c/w thermal resistance, 14l-tssop ja 100 c/w note 1: the mcp6g01/1r/1u/2/3/4 family of sgas operates over this temperature range, but operation must not cause t j to exceed maximum junction temperature (+150c). gsel v out t gsl1 0.15v 1.50v v in 0.150v 0.030v 0.15v t gsm10 0.03v 1.50v t gsh1 0.03v t gsm50 0.30v 1.50v t gsh10 0.30v t gsl50 downloaded from: http:///
mcp6g01/1r/1u/2/3/4 ds22004b-page 6 ? 2006 microchip technology inc. figure 1-2: sga chip select timing diagram. cs t csoff v out t cson high-z high-z i dd 120 pa (typ.) 110 a (typ.) 0.9v dd i ss Cv dd / 7 m (typ.) C110 a (typ.) i cs 30 pa (typ.) v dd / 7 m (typ.) downloaded from: http:///
? 2006 microchip technology inc. ds22004b-page 7 mcp6g01/1r/1u/2/3/4 1.1 dc output voltage specs / model 1.1.1 ideal model the ideal sga output voltage (v out ) is (see figure 1-3 ): equation 1-1: this equation holds when there are no gain or offset errors. 1.1.2 linear model the sgas linear region of operation is modeled by the line v o_lin shown in figure 1-3 . v o_lin includes offset and gain errors, but does not include non-linear effects. equation 1-2: this lines endpoints are 0. 3v from the supply rails (v o_id = 0.3v and v dd C 0.3v). the gain error and input offset voltage specifications (in the electrical specifications) relate to figure 1-3 as follows: equation 1-3: the input offset spec ification describes v os at g=+1v/v. the dc gain drift ( g/ t a ) can be calculated from the change in g e across temperature. this is shown in the following equation: equation 1-4: figure 1-3: output voltage model. 1.1.3 output non-linearity figure 1-4 shows the integral non-linearity (inl) of the output voltage. inl is the output non-linearity error not explained by v o_lin : equation 1-5: the output non-linearity specification (in the electrical specifications, with units of % of fsr) is related to figure 1-4 by: equation 1-6: note that the full scale range (fsr) is v dd C0.6v (0.3v to v dd C0.3v). where: g is the nominal gain v o_id gv in = v ref v ss 0v == v o_lin g 1 g e + () v in 0.3v g ----------- - v os + C ?? ?? 0.3v + = v ref v ss 0v == where: g is the nominal gain g e is the gain error v os is the input offset voltage g e 100% v 2 v 1 C v dd 0.6v C ---------------------------- - ? = v os v 1 g 1 g e + () ------------------------ - , = g +1 = where: v 1 v out v o _ id , C = v o _ id 0.3v = v 2 v out v o _ id , C = v o _ id v dd 0.3v C = g t a ? g g e t a --------- - , ? = in units of v/v/c g t a ? 100% g e t a --------- - , ? = in units of %/c 0 0 0.3 v dd -0.3 v dd v o ut v out (v) v in (v) 0.3 v dd -0.3 v dd g gg v 1 v o _ i d v o _ l i n v 2 inl v out v o _ lin C = v onl 100% max v 3 v 4 , () v dd 0.6v C ------------------------------ - ? = v 3 max inl C () = where: v 4 max inl () = downloaded from: http:///
mcp6g01/1r/1u/2/3/4 ds22004b-page 8 ? 2006 microchip technology inc. figure 1-4: output voltage inl. 0 inl (v) v in (v) 0.3 v dd -0.3 v dd g gg 0 v 3 v 4 downloaded from: http:///
? 2006 microchip technology inc. ds22004b-page 9 mcp6g01/1r/1u/2/3/4 2.0 typical performance curves note: unless otherwise indicated, t a =+25c, v dd = +1.8v to +5.5v, v ss = gnd, g = +1 v/v, v in = (0.3v)/g, r l =100k to v dd /2, c l = 60 pf, gsel = v dd /2, and cs is tied low. figure 2-1: dc gain error, g = +1. figure 2-2: dc gain error, g +10. figure 2-3: input offset voltage. figure 2-4: dc gain drift, g = +1. figure 2-5: dc gain drift, g +10. figure 2-6: input offset voltage drift. note: the graphs and tables provided following this note are a statistical summary based on a limited number of samples and are provided for informational purpose s only. the performance characteristics listed herein are not tested or guaranteed. in so me graphs or tables, the data presented may be outside the specified operating range (e.g., outside specified power suppl y range) and therefore outs ide the warranted range. 0% 5% 10% 15% 20% 25% 30% -0.28 -0.24 -0.20 -0.16 -0.12 -0.08 -0.04 0.00 0.04 0.08 0.12 0.16 0.20 0.24 0.28 dc gain error (%) percentage of occurrences 2460 samples g = +1 0% 2% 4% 6% 8% 10% 12% 14% -0.7 -0.6 -0.5 -0.4 -0.3 -0.2 -0.1 0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 dc gain error (%) percentage of occurrences 4916 samples g +10 0% 2% 4% 6% 8% 10% 12% 14% 16% 18% 20% -4.5 -3.5 -2.5 -1.5 -0.5 0.5 1.5 2.5 3.5 4.5 input offset voltage (mv) percentage of occurrences 2460 samples g = +50 g = +10 g = +1 0% 2% 4% 6% 8% 10% 12% 14% 16% 18% -5-4 -3 -2 -1 01 2 3 4 5 dc gain drift (ppm/c) percentage of occurrences 2459 samples g = +1 t a = -40 to +125c 0% 2% 4% 6% 8% 10% 12% 14% -14 -12 -10 -8-6 -4 -2 02 4 6 8 1012 14 dc gain drift (ppm/c) percentage of occurrences 4912 samples g +10 t a = -40 to +125c 0% 2% 4% 6% 8% 10% 12% 14% 16% 18% 20% 22% -12 -10 -8-6 -4 -2 02 4 6 8 1012 input offset voltage drift (v/c) percentage of occurrences 1612 samples g = +1, +10, +50 t a = -40 to +125c downloaded from: http:///
mcp6g01/1r/1u/2/3/4 ds22004b-page 10 ? 2006 microchip technology inc. note: unless otherwise indicated, t a =+25c, v dd = +1.8v to +5.5v, v ss = gnd, g = +1 v/v, v in = (0.3v)/g, r l =100k to v dd /2, c l = 60 pf, gsel = v dd /2, and cs is tied low. figure 2-7: the mcp6g01/1r/1u/2/3/4 family shows no phase reversal under overdrive. figure 2-8: psrr vs. temperature. figure 2-9: input noise voltage density vs. frequency. figure 2-10: crosstalk vs. frequency, with g = 50 (circuit in figure 4-7 ). figure 2-11: psrr vs. frequency. figure 2-12: quiescent current vs. supply voltage. -1 0 1 2 3 4 5 6 0.0e+00 1.0e-03 2.0e-03 3.0e-03 4.0e-03 5.0e-03 6.0e-03 7.0e-03 8.0e-03 9.0e-03 1.0e -02 time (1 ms/div) input, output voltage (v) v dd = 5.0v g = +1 v/v v in v out 70 80 90 100 110 120 -50 -25 0 25 50 75 100 125 ambient temperature (c) psrr (db) 10 100 1000 10000 0.1 1 10 100 1000 10000 10000 0 frequency (hz) input noise voltage density (nv/ ? hz) 1k 10k 100k 1 10 100 0.1 g = +1 = +10= +50 -120 -110 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 0 1.e+03 1.e+04 1.e+05 frequency (hz) crosstalk, input referred (db) 1k 100k 10k v dd = 5.0v g = 50 v/v r s = 0 ? r s = 1 m ? r s = 100 k ? r s = 10 k ? 20 30 40 50 60 70 80 90 100 1000 10000 100000 frequency (hz) power supply rejection ratio (db) input referred g = 1 g = 10 g = 50 v dd = 1.8v v dd = 5.5v 100 1k 10k 100k 0 20 40 60 80 100 120 140 160 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 power supply voltage (v) quiescent current (ma) t a = +25c t a = C40c t a = +125c t a = +85c downloaded from: http:///
? 2006 microchip technology inc. ds22004b-page 11 mcp6g01/1r/1u/2/3/4 note: unless otherwise indicated, t a =+25c, v dd = +1.8v to +5.5v, v ss = gnd, g = +1 v/v, v in = (0.3v)/g, r l =100k to v dd /2, c l = 60 pf, gsel = v dd /2, and cs is tied low. figure 2-13: quiescent current (i ss ) in shutdown mode vs. supply voltage. figure 2-14: input bias current vs. temperature. figure 2-15: input bias curr ent vs. input voltage. figure 2-16: quiescent current (i ss ) in shutdown mode vs. temperature. figure 2-17: input bias current vs. input voltage. figure 2-18: output short circuit current vs. supply voltage. -8 -7 -6 -5 -4 -3 -2 -1 0 0.00.51.01.52.02.53.03.54.04.55.05.5 power supply voltage (v) quiescent current in shutdown (a) in shutdown mode v in = v dd /2 cs = v dd i ss_shdn 1 10 100 1,000 55 65 75 85 95 105 115 125 ambient temperature (c) input bias current (pa) v dd = 5.5v v in = v dd 1 10 100 1,000 10,000 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 input voltage (v) input bias current (pa) t a = +85c v dd = 5.5v t a = +125c -9 -8 -7 -6 -5 -4 -3 -2 -1 0 -50 -25 0 25 50 75 100 125 ambient temperature (c) quiescent current in shutdown (a) in shutdown mode v in = v dd /2 v dd = 5.5v v dd = 1.8v 1.e-12 1.e-11 1.e-10 1.e-09 1.e-08 1.e-07 1.e-06 1.e-05 1.e-04 1.e-03 1.e-02 -1.0 -0.9 -0.8 -0.7 -0.6 -0.5 -0.4 -0.3 -0.2 -0.1 0.0 input voltage (v) input current magnitude (a) +125c +85c +25c -40c 10m 1m 100 10 1 100n 10n 1n 100p 10p 1p 0 5 10 15 20 25 30 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 power supply voltage (v) output short circuit current magnitude (ma) t a = C40c t a = +25c t a = +85c t a = +125c downloaded from: http:///
mcp6g01/1r/1u/2/3/4 ds22004b-page 12 ? 2006 microchip technology inc. note: unless otherwise indicated, t a =+25c, v dd = +1.8v to +5.5v, v ss = gnd, g = +1 v/v, v in = (0.3v)/g, r l =100k to v dd /2, c l = 60 pf, gsel = v dd /2, and cs is tied low. figure 2-19: output voltage error vs. ideal output voltage, with v dd =1.8v. figure 2-20: output voltage headroom vs. output plus ladder current (circuit in figure 4-4 ). figure 2-21: output impedance vs. frequency. figure 2-22: output voltage error vs. ideal output voltage, with v dd =5.5v. figure 2-23: output voltage headroom vs. temperature. figure 2-24: ladder resistance drift. -3 -2 -1 0 1 2 3 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 ideal output voltage; gv in (v) output error, input referred; v out /g C v in (mv) v dd = +1.8v representative part g = +1 g = +10 g = +50 1 10 100 1000 0.01 0.1 1 10 output current magnitude (ma) output voltage headroom; v dd C v oh and v ol C v ss (mv) v dd = +5.5v v dd C v oh v dd = +1.8v v ol C v ss 1.e+02 1.e+03 1.e+04 1.e+05 1.e+04 1.e+05 1.e+06 1.e+07 frequency (hz) output impedance magnitude ( ) g = 50 = 10= 1 100 1k 100k 10k 1m 100k 10k 10m -3 -2 -1 0 1 2 3 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 ideal output voltage; gv in (v) output error, input referred; v out /g C v in (mv) v dd = +5.5v representative part g = +1 g = +10 g = +50 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 -50 -25 0 25 50 75 100 125 ambient temperature (c) output voltage headroom; v dd Cv oh and v ol Cv ss (mv) v dd = 5.5v: v dd Cv oh v ol Cv ss v dd = 1.8v: v ol Cv ss v dd Cv oh 0% 2% 4% 6% 8% 10% 12% 14% -2000 -1900 -1800 -1700 -1600 -1500 ladder resistance drift (ppm/c) percentage of occurrences 1228 samples t a = -40 to +125c downloaded from: http:///
? 2006 microchip technology inc. ds22004b-page 13 mcp6g01/1r/1u/2/3/4 note: unless otherwise indicated, t a =+25c, v dd = +1.8v to +5.5v, v ss = gnd, g = +1 v/v, v in = (0.3v)/g, r l =100k to v dd /2, c l = 60 pf, gsel = v dd /2, and cs is tied low. figure 2-25: slew rate vs. temperature, with g = +1. figure 2-26: slew rate vs. temperature, with g = +10. figure 2-27: bandwidth vs. resistive load. figure 2-28: output voltage swing vs. frequency. figure 2-29: slew rate vs. temperature, with g = +50. figure 2-30: bandwidth vs. capacitive load. 0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 -50 -25 0 25 50 75 100 125 ambient temperature (c) slew rate (v/s) g = +1 v/v falling edge rising edge v dd = 1.8v v dd = 5.5v 0.0 0.5 1.0 1.5 2.0 2.5 3.0 -50 -25 0 25 50 75 100 125 ambient temperature (c) slew rate (v/s) g = +10 v/v falling edge rising edge v dd = 5.5v 1.e+04 1.e+05 1.e+06 1.e+02 1.e+03 1.e+04 1.e+05 resistive load ( ) bandwidth (hz) g = +1 g = +10g = +50 10k 1m 100k 10k 100k 100 1k 0.1 1 10 1.e+03 1.e+04 1.e+05 1.e+06 frequency (hz) output voltage swing (v p-p ) v dd = 1.8v v dd = 5.5v g = +1 g = +10 g = +50 1k 100k 1m 10k 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 -50 -25 0 25 50 75 100 125 ambient temperature (c) slew rate (v/s) g = +50 v/v falling edge rising edge v dd = 5.5v 1.e+05 1.e+06 10 100 1000 capacitive load (pf) bandwidth (hz) 100k 1m g = +10 g = +50 g = +1 downloaded from: http:///
mcp6g01/1r/1u/2/3/4 ds22004b-page 14 ? 2006 microchip technology inc. note: unless otherwise indicated, t a =+25c, v dd = +1.8v to +5.5v, v ss = gnd, g = +1 v/v, v in = (0.3v)/g, r l =100k to v dd /2, c l = 60 pf, gsel = v dd /2, and cs is tied low. figure 2-31: gain vs. frequency. figure 2-32: small signal pulse response. figure 2-33: thd plus noise vs. frequency, v out = 2.8 v p-p . figure 2-34: gain peaking vs. capacitive load. figure 2-35: large signal pulse response. figure 2-36: thd plus noise vs. frequency, v out = 4.0 v p-p . -40 -30 -20 -10 0 10 20 30 40 1.e+04 1.e+05 1.e+06 1.e+07 frequency (hz) gain (db) g = +1 100k 1m 10m 10k g = +50 g = +10 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0.00 5.00 10.00 15.00 20.00 25.00 30.00 35.00 40.00 45.00 50.00 time (5 s/div) output voltage (20 mv/div) 0 0 0 1 1 1 1 1 normalized input voltage (100 mv/div) v dd = +5.0v v out g = +50g = +10 g = +1 gv in 0.001 0.01 0.1 1 10 1.e+02 1.e+03 1.e+04 1.e+05 frequency (hz) thd + noise (%) measurement bw = 80 khz 100 1k 100k 10k g = +10 g = +1 g = +50 v out = 2.8v p-p v dd = 5.0v 0 1 2 3 4 5 6 7 10 100 1000 capacitive load (pf) gain peaking (db) g = +1 g = +10 g = +50 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 0.00 5.00 10.00 15.00 20.00 25.00 30.00 35.00 40.00 45.00 50.00 time (5 s/div) normalized input voltage, output voltage (v) v dd = +5.0v gv i v out g = +1 g = +10 g = +50 0.001 0.01 0.1 1 10 1.e+02 1.e+03 1.e+04 1.e+05 frequency (hz) thd + noise (%) v out = 4 v p-p v dd = 5.0v 100 1k 100k 10k g = +10 g = +1 g = +50 measurement bw = 80 khz downloaded from: http:///
? 2006 microchip technology inc. ds22004b-page 15 mcp6g01/1r/1u/2/3/4 note: unless otherwise indicated, t a =+25c, v dd = +1.8v to +5.5v, v ss = gnd, g = +1 v/v, v in = (0.3v)/g, r l =100k to v dd /2, c l = 60 pf, gsel = v dd /2, and cs is tied low. figure 2-37: thd plus noise vs. supply voltage. figure 2-38: thd plus noise vs. output swing. figure 2-39: gain select timing, with gain = 1 and 10. figure 2-40: thd plus noise vs. load resistance. figure 2-41: gain select timing, with gain = 1 and 50. figure 2-42: gain select timing, with gain = 1 and 10. 0.001 0.01 0.1 1 10 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 power supply voltage (v) thd + noise (%) g = +1 g = +10 g = +50 v out = 0.8v dd f = 1 khz measurement bw = 80 khz 0.001 0.01 0.1 1 10 11 0 output swing (v p-p ) thd + noise (%) g = +1 g = +10 g = +50 measurement bw = 80 khz v dd = 5.0v f = 1 khz 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 0 102030405060708090100 time (10 s/div) output voltage (v) -40 -35 -30 -25 -20 -15 -10 -5 0 5 10 gain select voltage (v) 0 gsel (g = +1) (g = +10) (g = +10) 5 v dd = 5.0v v in = 0.15v v out 0.001 0.01 0.1 1 10 1.e+03 1.e+04 1.e+05 1.e+06 load resistance ( ? ) thd + noise (%) g = +1 g = +10 g = +50 f = 1 khz v dd = 5.0v 1k 10k 100k 1m measurement bw = 80 khz 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 0 102030405060708090100 time (10 s/div) output voltage (v) -40 -35 -30 -25 -20 -15 -10 -5 0 5 10 gain select voltage (v) 0 gsel (g = +1) (g = +50) (g = +1) 5 v dd = 5.0v v in = 0.030v v out 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 0 102030405060708090100 time (10 s/div) output voltage (v) -40 -35 -30 -25 -20 -15 -10 -5 0 5 10 gain select voltage (v) 0 gsel (g = +10) (g = +50) (g = +10) 5 v dd = 5.0v v in = 0.030v v out downloaded from: http:///
mcp6g01/1r/1u/2/3/4 ds22004b-page 16 ? 2006 microchip technology inc. note: unless otherwise indicated, t a =+25c, v dd = +1.8v to +5.5v, v ss = gnd, g = +1 v/v, v in = (0.3v)/g, r l =100k to v dd /2, c l = 60 pf, gsel = v dd /2, and cs is tied low. figure 2-43: output voltage vs. chip select, with v dd =1.8v. figure 2-44: gsel pin current vs. gsel voltage, with v dd =1.8v. figure 2-45: gsel current, with gsel voltage of 0.3v dd . figure 2-46: output voltage vs. chip select, with v dd =5.0v. figure 2-47: gsel pin current vs. gsel voltage, with v dd =5.5v. figure 2-48: gsel current, with gsel voltage of 0.7v dd . -0.2 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 time (20 s/div) output voltage (mv) chip select voltage (v) 1.8 0 v out is "on" cs v dd = 1.8v v in = 0.9v dd shutdown g = 1 g = 10 g = 50 -10 -8 -6 -4 -2 0 2 4 6 8 10 0.00.20.40.60.81.01.21.41.61.8 gsel voltage (v) gsel current (a) t a = +25c = +85c = +125c v dd = 1.8v t a = +125c = +85c = +25c 0% 2% 4% 6% 8% 10% 12% 14% 16% 18% 20% 22% -7.0 -6.6 -6.2 -5.8 -5.4 -5.0 -4.6 -4.2 -3.8 -3.4 -3.0 gsel current (a) percentage of occurrences 1228 samples gsel = 0.3v dd v dd = 1.8v v dd = 5.5v -0.5 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 time (20 s/div) output voltage (mv) chip select voltage (v) 5 0 v out is "on" cs v dd = 5.0v v in = 0.9v dd shutdown g = 1 g = 10 g = 50 -10 -8 -6 -4 -2 0 2 4 6 8 10 0.00.51.01.52.02.53.03.54.04.55.05.5 gsel voltage (v) gsel current (a) v dd = 5.5v t a = +25c = +85c = +125c t a = +125c = +85c = +25c 0% 2% 4% 6% 8% 10% 12% 14% 16% 18% 20% 3.0 3.4 3.8 4.2 4.6 5.0 5.4 5.8 6.2 6.6 7.0 gsel current (a) percentage of occurrences 1228 samples gsel = 0.7v dd v dd = 5.5v v dd = 1.8v downloaded from: http:///
? 2006 microchip technology inc. ds22004b-page 17 mcp6g01/1r/1u/2/3/4 note: unless otherwise indicated, t a =+25c, v dd = +1.8v to +5.5v, v ss = gnd, g = +1 v/v, v in = (0.3v)/g, r l =100k to v dd /2, c l = 60 pf, gsel = v dd /2, and cs is tied low. figure 2-49: gsel trip point between g = +1 and g = +10. figure 2-50: gsel trip point between g = +1 and g = +50. 0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100% 0.213 0.218 0.222 0.227 0.231 0.236 0.241 0.245 0.250 0.255 0.259 normalized gsel trip point; v gsel /v dd percentage of occurrences 1227 samples g = +1 to +10 v dd = 1.8v v dd = 5.5v 0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100% 0.736 0.741 0.745 0.750 0.755 0.759 0.764 0.768 0.773 normalized gsel trip point; v gsel /v dd percentage of occurrences 1228 samples g = +1 to +50 v dd = 1.8v v dd = 5.5v downloaded from: http:///
mcp6g01/1r/1u/2/3/4 ds22004b-page 18 ? 2006 microchip technology inc. 3.0 pin descriptions descriptions of the pins are listed in table 3-1 (single op amps) and table 3-2 (dual and quad op amps). table 3-1: pin function table for single op amps table 3-2: pin function table for dual and quad op amps 3.1 analog output the output pin (v out ) is a low impedance voltage source. the selected gain (g) and input voltage (v in ) determine its value. 3.2 analog input the analog inputs (v in ) are high impedance cmos inputs with low bias currents. only three fixed, non- inverting gains are available through these inputs. 3.3 power supply (v ss and v dd ) the positive power supply pin (v dd ) is 1.8v to 5.5v higher than the negative power supply pin (v ss ). for normal operation, the other pins are at voltages between v ss and v dd . typically, these parts are used in a single (positive) supply configuration. in this case, v ss is connected to ground, and v dd is connected to the supply. v dd will need a local bypass capacitor (typically 0.01 f to 0.1 f) within 2 mm of the v dd pin. these parts need to use a bulk capacitor (typically 1.0 f to 10 f) within 100 mm of the v dd pin; it can be shared with nearby analog parts. 3.4 digital inputs the chip select (cs ) input is a schmitt-triggered, cmos logic input. the gain select (gsel) inputs are tri-level digital inputs. they function similar to normal logic inputs at low (g = +10) and high voltages (g = +50). the pin can also be set to mid-supply (g = +1) by a low impedance source, or by leaving this pin open. mcp6g01 (soic, msop) mcp6g01 (sot-23-5) mcp6g01r (sot-23-5) mcp6g01u (sot-23-5) mcp6g03 symbol description 61 1 46 v out analog output 2 4 4 3 2 gsel gain select input 33 3 13 v in analog input 75 2 57 v dd positive power supply 42 5 24 v ss negative power supply 8 c s chip select 1,5,8 1,5 nc no internal connection mcp6g02 mcp6g04 symbol description 11v outa analog output a 2 2 gsel a gain select input (sga a) 33 v ina analog input a 84 v dd positive power supply 55 v inb analog input b 6 6 gsel b gain select input (sga b) 77v outb analog output b 8v outc analog output c 9 gsel c gain select input (sga c) 1 0 v inc analog input c 41 1 v ss negative power supply 1 2 v ind analog input d 13 gsel d gain select input (sga d) 1 4v outd analog output d downloaded from: http:///
? 2006 microchip technology inc. ds22004b-page 19 mcp6g01/1r/1u/2/3/4 4.0 applications information the mcp6g01/1r/1u/2/3/4 family of selectable gain amplifiers (sga) is based on simple analog building blocks (see figure 4-1 ). each of these blocks will be explained in more detail in the following subsections. figure 4-1: sga block diagram. 4.1 internal op amp the internal op amp gives the right combination of bandwidth, accuracy, and flexibility. 4.1.1 compensation capacitors the internal op amp has three compensation capacitors (comp. caps.) connected to a switching network. they are selected to give good small signal bandwidth at high gains, and good slew rate (full power bandwidth) at low gains. the change in bandwidth as gain changes is between 250 and 900 khz. refer to table 4-1 for more information. table 4-1: gain vs. internal compensation capacitor 4.1.2 rail-to-rail inputs the input stage of the internal op amp uses two differential input stages in parallel; one operates at low v in (input voltage), while the other operates at high v in . with this topology, the internal inputs can operate to 0.3v past either supply ra il, although the output will clip the signal before that happens. the inputs need to be kept within a smaller range to prevent output clipping. th e input offset voltage also reduces the range; most designs will need the following for normal operation: equation 4-1: the transition between the two input stage occurs when v in v dd C 1.1v (see figure 2-19 and figure 2- 22 ). for the best distortion and gain linearity, avoid this region of operation. 4.1.3 phase reversal the mcp6g01/1r/1u/2/3/4 amplifier family is designed with cmos input devices. it is designed to not exhibit phase inversion when the input pins exceed the supply voltages. figure 2-7 shows an input voltage exceeding both supplies with no resulting phase inversion. gain (v/v) gsel voltage (typ.) (v) 1v dd /2 (or open) 10 0 50 v dd note: v ss is assumed to be 0v v out v dd gsel v in v ss 3 r f r g gain select logic gain switches resistor ladder (r lad ) cs (mcp6g03 only) 5m gain (v/v) internal comp. cap. g x bw (mhz) typ. sr (v/s) typ. fpbw (khz) typ. bw (khz) typ. 1 large 0.90 0.50 29 900 10 medium 3.5 2.3 133 350 50 small 12.5 4.5 260 250 note 1: changing the compensation capacitor does not change the dc performance (e.g., v os ). 2: g x bw is approximately the gain bandwidth product of the internal op amp. 3: fpbw is the full power bandwidth at v dd = 5.5v, which is based on slew rate (sr). 4: bw is the closed-loop, small signal C3 db bandwidth. v ol g --------- - v os v in v oh g ---------- - v os C << + downloaded from: http:///
mcp6g01/1r/1u/2/3/4 ds22004b-page 20 ? 2006 microchip technology inc. 4.1.4 input voltage and current limits the esd protection on the inputs can be depicted as shown in figure 4-2 . this structure was chosen to protect the input transistors, and to minimize input bias current (i b ). the input esd diodes clamp the inputs when they try to go more than one diode drop below v ss . they also clamp any voltages that go too far above v dd ; their breakdown voltage is high enough to allow normal operation, and low enough to bypass esd events within the specified limits. figure 4-2: simplified analog input esd structures. in order to prevent damage and/or improper operation of these amplifiers, the circuits they are in must limit the currents (and voltages) at the v in pins (see section absolute maximum ratings ? at the beginning of section 1.0 electri cal characteristics ). figure 4-3 shows the recommended approach to protecting these inputs. the internal esd diodes prevent the input pins (v in ) from going too far below ground, and the resistor r 1 limits the possible current drawn out of the input pin. diode d 1 prevents the input pin (v in ) from going too far above v dd . when implemented as shown, resistor r 1 also limits the current through d 1 . figure 4-3: protecting the analog inputs. it is also possible to connect the diode to the left of the resistor r 1 . in this case, the current through the diode d 1 needs to be limited by some other mechanism. the resistor then serves as in-rush current limiter; the dc current into the input pin (v in ) should be very small. a significant amount of current can flow out of the inputs when the common mode voltage (v cm ) is below ground (v ss ); see figure 2-17 . applications that are high impedance may need to limit the useable voltage range. 4.1.5 rail-to-rail output the maximum output voltage swing is the maximum swing possible under a particular amplifier load current. the amplifier load current is the sum of the external load current (i out ) and the current through the ladder resistance (i lad ); see figure 4-4 . equation 4-2: figure 4-4: amplifier load current. see figure 2-20 for the typical output headroom (v dd C v oh or v ol C v ss ) as a function of amplifier load current.the specificat ion table states the output can reach within 10 mv of either supply rail when r l = 100 k . 4.2 resistor ladder the resistor ladder shown in figure 4-1 (r lad =r f +r g ) sets the gain. placing the gain switches in series with the inverting input reduces the parasitic capacitance, distortion, and gain mismatch. r lad is an additional load on the output of the sga and causes additional current draw from the supplies. when cs is high, the sga is shut down (low power). r lad is still attached to the v out and v ss pins. thus, these pins and the internal amplifiers inverting input are all connected through r lad and the output is not high-z (unlike the internal op amp). r lad contributes to the output noise; see figure 2-9 . bond pad bond pad bond pad v dd v in v ss to the rest of input stage the amplifier v 1 mcp6g0x r 1 v dd d 1 r 1 v ss C (minimum expected v 1 ) 2ma v out v in where: amplifier load current i out i lad + = i lad v out v ss C () r lad --------------------------------- = v out v ss r lad i out i lad mcp6g0x v in downloaded from: http:///
? 2006 microchip technology inc. ds22004b-page 21 mcp6g01/1r/1u/2/3/4 r lad is intended to be driven at the v ss pin by a low impedance voltage source. the power supply driving the v ss pin should have an output impedance less than 0.1 to maintain reasonable gain accuracy. 4.3 mcp6g03 chip select (cs ) the mcp6g03 is a single amplifier with chip select (cs ). when cs is high, the internal op amp is shut down and its output placed in a high-z state. the resistive ladder is always connected between v ss and v out ; even in shutdown. this means that the output resistance will be 350 k (typ.), with a path for output signals to appear at the input. the supply current at v ss includes the current through the load resistor and ladder resistors; it also includes current from the cs pin to v ss . when cs is low, the amplifier is enabled. if cs is left floating, the amplif ier may not operate properly. figure 1-2 and figure 2-43 show how the output voltage and supply current response to a cs pulse. 4.4 gain select (gsel) the amplifier can be set to the gains +1 v/v, +10 v/v, and +50 v/v using one input pin (gsel). at the same time, different compensation capacitors are selected to optimize the bandwidth vs. slew rate trade-off (see ta b l e 4 - 1 ). ta b l e 4 - 2 shows how to change the gain using a gpio pin on a microcontroller and ta b l e 4 - 3 shows how to hard wire the gain (i.e., using pcb wiring). table 4-2: mcu driven gain selection table 4-3: hard wired gain selection 4.5 capacitive load and stability large capacitive loads ca n cause stability problems and reduced bandwidth for the mcp6g01/1r/1u/2/3/4 family of sgas ( figure 2-30 and figure 2-34 ). as the load capacitance increases, there is a corresponding increase in frequency response peaking and step response overshoot and ringing. this happens because a large load capacitance decreases the internal amplifiers phase margin and bandwidth. when driving large capacitive loads with these sgas (i.e., > 60 pf), a small series resistor at the output (r iso in figure 4-5 ) improves the internal amplifiers stability by making the load resistive at higher frequencies. the bandwidth will be generally lower than the bandwidth with no capacitive load. figure 4-5: sga circuit for large capacitive loads. figure 4-6 gives recommended r iso values for different capacitive l oads. after selecting r iso for your circuit, double check the resulting frequency response peaking and step response overshoot on the bench. modify r iso s value until the response is reasonable at all gains. gain mcu pins state +1 v/v output pics v ref at v dd /2 digital output high-z (notes 1) output v dd /2 pwm signal (notes 2) +10 v/v digital output driven low +50 v/v digital output driven high note 1: see section 4.8.1 driving the gain select pin with a microcontroller gpio pin . 2: see section 4.8.2 driving the gain select pin with a pwm signal selected gain possible gsel drivers +1 v/v open circuit (note 1) low impedance source at v dd /2 +10 v/v tied to gnd (0v) +50 v/v tied to v dd note 1: the gsel pin floats to mid-supply (v dd /2); a bypass capacitor may be needed. v in v out mcp6g0x r iso c l downloaded from: http:///
mcp6g01/1r/1u/2/3/4 ds22004b-page 22 ? 2006 microchip technology inc. figure 4-6: recommended r iso . 4.6 layout considerations good pc board layout techniques will help achieve the performance shown in section 1.0 electrical characteristics and section 2.0 typical performance curves . it will also help minimize electromagnetic compatibility (emc) issues. because the mcp6g01/1r/1u/2/3/4 sgas frequency response reaches unity gain at 10 mhz when g = 50, it is important to use good pcb layout techniques. any parasitic coupling at high frequency might cause undesired peaking. filtering high frequency signals (i.e., fast edge rates) can help. 4.6.1 component placement separate different circuit functions: digital from analog, low speed from high speed, and low power from high power. this will reduce crosstalk. keep sensitive traces short and straight. separate them from interfering com ponents and traces. this is especially important for high frequency (low rise time) signals. 4.6.2 supply bypass use a local bypass capacitor (0.01 f to 0.1 f) within 2 mm of the v dd pin for good, high frequency performance. it must connect directly to ground. use a bulk bypass capacitor (i.e., 1.0 f to 10 f) within 100 mm of the v dd pin. it needs to connect to ground, and provides large, slow currents. this capacitor may be shared with other nearby analog parts. ground plane is important, and power plane(s) can also be of great help. high fr equency (e.g., multi-layer ceramic capacitors), surface mount components improve the supplys performance. 4.6.3 input source impedance the sources driving the inputs of the sgas need to have reasonably low source impedance at higher frequencies. figure 4-7 shows how the external source resistance (r s ), sga package pin capacitance (c p1 ), and sga package pin-to-pin capacitance (c p2 ) form a positive feedback voltage divider network. feedback may cause frequency response peaking and step response overshoot and ringing. figure 4-7: positive feedback path. figure 2-10 shows the crosstalk (referred to input) that results when a hostile signal is connected to the other inputs (e.g., v inb through v ind ), and the input of interest (e.g., v ina ) has r s connected to gnd. a gain of +50 was chosen for this plot because it demonstrates the worst-case behavior. increasing r s increases the crosstalk as expected. at a source impedance of 10 m , there is noticeable change in behavior. most designs should use a source resistance (r s ) no larger than 10 m . careful attention to layout parasitics and proper component selection will help minimize this effect. when a source impedance larger than 10 m must be used, place a capacitor in parallel to c p1 to reduce the positive feedback. this capacitor needs to be large enough to overcome gain (or crosstalk) peaking, yet small enough to allow a reasonable signal bandwidth. 4.6.4 signal coupling the input pins of the mcp6 g01/1r/1u/2/3/ 4 family of sgas are high impedance. this makes them especially susceptible to capacitively coupled noise. using a ground plane helps reduce this problem. when noise is capacitively coupled, the ground plane provides additional shunt capacitance to ground. when noise is magnetically coupled, the ground plane reduces the mutual inductance between traces. increasing the separation between traces makes a significant difference. changing the direction of one of the traces can also reduce magnetic coupling. it may help to locate guard traces next to the victim trace. they should be on both sides of, and as close as possible to, the victim trace. connect the guard traces to the ground plane at both ends. also connect long guard traces to the ground plane in the middle. 10 100 1,000 10 100 1,000 10,000 100,000 load capacitance (f) recommended r iso ( : ) 10p 100p 1n 100n for all gains 10n v s mcp6g0x v out r s c p1 c p2 downloaded from: http:///
? 2006 microchip technology inc. ds22004b-page 23 mcp6g01/1r/1u/2/3/4 4.7 unused amplifiers an unused amplifier in a quad package (mcp6g04) should be configured as shown in figure 4-8 . this circuit prevents the output from toggling and causing crosstalk. be cause the v in pin looks like an open circuit, the gsel voltage is automatically set at v dd /2, and the gain is 1 v/v. the output pin provides a buffered v dd /2 voltage and minimizes the supply current draw of the unused amplifier. figure 4-8: unused amplifiers. 4.8 typical applications 4.8.1 driving the gain select pin with a microcontroller gpio pin the circuit in figure 4-9 uses a microcontroller gpio pin to drive the gain select input (gsel). setting the gpio pin to logic low, high-z or logic high gives a gsel voltage of 0v, v dd /2 or v dd , respectively (g = 10, 1 or 50). figure 4-9: driving the gsel pin. the microcontrollers gpio pin cannot produce a leakage current of more than 1 a for this circuit to function properly. in noisy environments, a capacitor may need to be added to the gpio pin. 4.8.2 driving the gain select pin with a pwm signal the circuit in figure 4-10 uses a pwm output on a pic microcontroller (100 khz clock rate) to drive the gain select input (gsel). setting the pwm duty cycle to 0%, 50% or 100% gives a gsel voltage of 0v, v dd /2 or v dd , respectively (g = 10, 1 or 50). figure 4-10: driving the gsel pin. the pwm clock rate needs to be fast so it is easily filtered and does not interf ere with the desired signal, and it needs to be slow enough for good accuracy and low crosstalk. this filter r educes the ripple at the gsel pin to about 7 mv p-p at v dd = 5.0v. the 10% settling time is about 200 s; the filter limits how quickly the gain can be changed. scale the resistors and/or capacitors for other clock rates, or for different ripple. 4.8.3 gain ranging figure 4-11 shows a circuit that measures the current i x . the circuits performance benefits from changing the gain on the sga. just as a hand-held multimeter uses different measurement ranges to obtain the best results, this circuit makes it easy to set a high gain for small signals and a low gain for large signals. as a result, the required dynamic range at the sgas output is less than at its input (by up to 34 db). figure 4-11: wide dynamic range current measurement circuit. ? mcp6g04 v out mcp6g0x v in gsel v dd v out mcp6g0x v in gsel mcu gpio pin v dd v dd v out mcp6g0x v in gsel pic mcu pwm output 4.7 nf v dd v dd 10 k 4.7 nf 10 k i x v out mcp6g0x r s downloaded from: http:///
mcp6g01/1r/1u/2/3/4 ds22004b-page 24 ? 2006 microchip technology inc. 4.8.4 shifted gain range sga figure 4-12 shows a circuit using a mcp6271 at a gain of +10 in front of a mcp6g 01. this shifts the overall gain range to +10 v/v to +500 v/v (from +1 v/v to +50 v/v). figure 4-12: sga with higher gain range. it is also easy to shift the gain range to lower gains (see figure 4-13 ). the mcp6001 acts as a unity gain buffer, and the resistive voltage divider shifts the gain range down to +0.1 v/v to +5.0 v/ v (from +1 v/v to +50 v/v). figure 4-13: sga with lower gain range. 4.8.5 adc driver this family of sgas is well suited for driving analog-to- digital converters (adc). the gains (1, 10, and 50) effectively increase the adcs input resolution by a factor of as large as 50 (i.e., by 5.6 bits). this works well for applications needing relative accuracy more than absolute accuracy (e.g., power monitoring); see figure 4-14 . figure 4-14: sga as an adc driver. the low-pass filter in the block diagram reduces the integrated noise at the mc p6g01s output and serves as an anti-aliasing filter. this filter may be designed using microchips filterlab ? software, available at www.microchip.com. v in v out mcp6271 mcp6g01 1.11 k 10.0 k v in mcp6001 1.11 k 10.0 k v out mcp6g01 out mcp3001 10-bit adc 3 mcp6g01 v in low-pass filter downloaded from: http:///
? 2006 microchip technology inc. ds22004b-page 25 mcp6g01/1r/1u/2/3/4 5.0 packaging information 5.1 package marking information 8-lead soic (150 mil) ( mcp6g01 , mcp6g02, mcp6g03 ) example: xxxxxxxx xxxxyyww nnn 8-lead msop ( mcp6g01 , mcp6g02, mcp6g03 ) example: xxxxxxywwnnn 6g01 e 634256 mcp6g01 e sn^^0634 256 legend: xx...x customer-specific information y year code (last digit of calendar year) yy year code (last 2 digits of calendar year) ww week code (week of january 1 is week 01) nnn alphanumeric traceability code pb-free jedec designator for matte tin (sn) * this package is pb-free. the pb-free jedec designator ( ) can be found on the outer packaging for this package. note : in the event the full microchip part nu mber cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-specific information. 3 e 3 e 3 e 5-lead sot-23 ( mcp6g01, mcp6g01r, mcp6g01u ) xxnn ck25 device code mcp6g01 cknn mcp6g01r clnn mcp6g01u cmnn note: applies to 5-lead sot-23 downloaded from: http:///
mcp6g01/1r/1u/2/3/4 ds22004b-page 26 ? 2006 microchip technology inc. package marking information (continued) legend: xx...x customer-specific information y year code (last digit of calendar year) yy year code (last 2 digits of calendar year) ww week code (week of january 1 is week 01) nnn alphanumeric traceability code pb-free jedec designator for matte tin (sn) * this package is pb-free. the pb-free jedec designator ( ) can be found on the outer packaging for this package. note : in the event the full microchip part nu mber cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-specific information. 3 e 3 e 14-lead soic (150 mil) ( mcp6s24 ) example: xxxxxxxxxxx yywwnnn xxxxxxxxxxx xxxxxxxx nnn yyww 14-lead tssop (4.4mm) ( mcp6s24 ) example: 6g04 e/st 256 0609 mcp6g04 0609256 e/sl^^ 3 e downloaded from: http:///
? 2006 microchip technology inc. ds22004b-page 27 mcp6g01/1r/1u/2/3/4 5-lead plastic small outline transistor (ot) (sot-23) note: for the most current package drawings, please se e the microchip packaging specification located at http://www.microchip.com/packaging 1 p d b n e e1 l c a2 a a1 p1 10 5 0 10 5 0 b mold draft angle bottom 10 5 0 10 5 0 a mold draft angle top 0.50 0.43 0.35 .020 .017 .014 b lead width 0.20 0.15 0.09 .008 .006 .004 c lead thickness 10 5 0 10 5 0 f foot angle 0.55 0.45 0.35 .022 .018 .014 l foot length 3.10 2.95 2.80 .122 .116 .110 d overall length 1.75 1.63 1.50 .069 .064 .059 e1 molded package width 3.00 2.80 2.60 .118 .110 .102 e overall width 0.15 0.08 0.00 .006 .003 .000 a1 standoff 1.30 1.10 0.90 .051 .043 .035 a2 molded package thickness 1.45 1.18 0.90 .057 .046 .035 a overall height 1.90 .075 p1 outside lead pitch (basic) 0.95 .038 p pitch 5 5 n number of pins max nom min max nom min dimension limits millimeters inches * units dimensions d and e1 do not include mold flash or protrusions. mold flash or protrusions shall not exceed .005" ( 0.127mm) per s ide. notes: eiaj equivalent: sc-74a drawing no. c04-091 * controlling parameter revised 09-12-05 downloaded from: http:///
mcp6g01/1r/1u/2/3/4 ds22004b-page 28 ? 2006 microchip technology inc. 8-lead plastic micro small outline package (ms) (msop) note: for the most current package drawings, please se e the microchip packaging specification located at http://www.microchip.com/packaging l l1 ? c a2 a1 a b 2 1 note 1 e e e1 d n numb e r of pins pitchov e rall h e ight mold e d packag e thickn e ss standoff ov e rall width mold e d packag e width ov e rall l e ngth foot l e ngth footprintfoot angl e l e ad thickn e ss l e ad width units dim e nsion limits n e a a2a1 e e1 d l l1 ? c b ? 0.750.00 0.40 0 0.080.22 8 0.65 bsc ? 0.85 ? 4.90 bsc3 .00 bsc 3 .00 bsc 0.60 0.95 ref ?? ? 1.100.95 0.15 0.80 8 0.2 3 0.40 min nom max millimeters notes:1. pin 1 visual ind e x f e atur e may vary, but must b e locat e d within th e hatch e d ar e a. 2. dim e nsions d and e1 do not includ e mold flash or protrusions. mold flash or protrusions shall not e xc ee d 0.15 mm p e r sid e . 3 . dim e nsioning and tol e rancing p e r asme y14.5m bsc: basic dim e nsion. th e or e tically e xact valu e shown without tol e ranc e s. ref: r e f e r e nc e dim e nsion, usually without tol e ranc e , for information purpos e s only. microchip t e chnology drawing no. c04?111, s e pt. 8, 2006 downloaded from: http:///
? 2006 microchip technology inc. ds22004b-page 29 mcp6g01/1r/1u/2/3/4 8-lead plastic small outline (sn) C narrow, 150 mil (soic) note: for the most current package drawings, please se e the microchip packaging specification located at http://www.microchip.com/packaging foot angle 048048 15 12 0 15 12 0 mold draft angle bottom 15 12 0 15 12 0 mold draft angle top 0.51 0.42 0.33 .020 .017 .013 b lead width 0.25 0.23 0.20 .010 .009 .008 c lead thickness 0.76 0.62 0.48 .030 .025 .019 l foot length 0.51 0.38 0.25 .020 .015 .010 h chamfer distance 5.00 4.90 4.80 .197 .193 .189 d overall length 3.99 3.91 3.71 .157 .154 .146 e1 molded package width 6.20 6.02 5.79 .244 .237 .228 e overall width 0.25 0.18 0.10 .010 .007 .004 a1 standoff 1.55 1.42 1.32 .061 .056 .052 a2 molded package thickness 1.75 1.55 1.35 .069 .061 .053 a overall height 1.27 .050 p pitch 8 8 n number of pins max nom min max nom min dimension limits millimeters inches* units 2 1 d n p b e e1 h l c 45 a2 a a1 * controlling parameter notes: dimensions d and e1 do not include mold flash or protru sions. mold flash or protrusions shall not exceed .010 (0.254mm) per side. jedec equivalent: ms-012 drawing no. c04-057 significant characteristic downloaded from: http:///
mcp6g01/1r/1u/2/3/4 ds22004b-page 30 ? 2006 microchip technology inc. 14-lead plastic small outline (sl) C narrow, 150 mil (soic) note: for the most current package drawings, please se e the microchip packaging specification located at http://www.microchip.com/packaging foot angle 048048 15 12 0 15 12 0 mold draft angle bottom 15 12 0 15 12 0 mold draft angle top 0.51 0.42 0.36 .020 .017 .014 b lead width 0.25 0.23 0.20 .010 .009 .008 c lead thickness 1.27 0.84 0.41 .050 .033 .016 l foot length 0.51 0.38 0.25 .020 .015 .010 h chamfer distance 8.81 8.69 8.56 .347 .342 .337 d overall length 3.99 3.90 3.81 .157 .154 .150 e1 molded package width 6.20 5.99 5.79 .244 .236 .228 e overall width 0.25 0.18 0.10 .010 .007 .004 a1 standoff 1.55 1.42 1.32 .061 .056 .052 a2 molded package thickness 1.75 1.55 1.35 .069 .061 .053 a overall height 1.27 .050 p pitch 14 14 n number of pins max nom min max nom min dimension limits millimeters inches * units 2 1 d p n b e e1 h l c 45 a2 a a1 * controlling parameter notes: dimensions d and e1 do not include mold flash or protrusions. mold flash or protrusions shall not exceed .010 (0.254mm) per si de. jedec equivalent: ms-012 drawing no. c04-065 revised 7-20-06 significant characteristic downloaded from: http:///
? 2006 microchip technology inc. ds22004b-page 31 mcp6g01/1r/1u/2/3/4 14-lead plastic thin shrink small outline (st) C 4.4 mm (tssop) note: for the most current package drawings, please se e the microchip packaging specification located at http://www.microchip.com/packaging l c 2 1 d n b p e1 e a2 a1 a 8 4 0 8 4 0 foot angle mold draft angle bottom 12 ref mold draft angle top 0.30 0.25 0.19 .012 .010 .007 b lead width 0.20 0.15 0.09 .008 .006 .004 c lead thickness 0.70 0.60 0.50 .028 .024 .020 l foot length 5.10 5.00 4.90 .201 .197 .193 d molded package length 4.50 4.40 4.30 .177 .173 .169 e1 molded package width 6.50 6.38 6.25 .256 .251 .246 e overall width 0.15 0.10 0.05 .006 .004 .002 a1 standoff 0.95 0.90 0.85 .037 .035 .033 a2 molded package thickness 1.10 1.05 1.00 .043 .041 .039 a overall height 0.65 bsc .026 bsc p pitch 14 14 n number of pins max nom min max nom min dimension limits millimeters * inches units dimensions d and e1 do not include mold fla sh or protrusions. mold flash or protrusions shall no t exceed .005" (0.127mm) per s ide. notes: jedec equivalent: mo-153 ab-1 revised: 08-17-05 * controlling parameter bsc: basic dimension. theoretically exact value shown without tolerances. ref: reference dimension, usually without tole rance, for information purposes only. see asme y14.5m see asme y14.5m drawing no. c04-087 12 ref 12 ref 12 ref downloaded from: http:///
mcp6g01/1r/1u/2/3/4 ds22004b-page 32 ? 2006 microchip technology inc. notes: downloaded from: http:///
? 2006 microchip technology inc. ds22004b-page 33 mcp6g01/1r/1u/2/3/4 appendix a: revision history revision b (december 2006) the following is the list of modifications: added sot-23-5 package option for the single gain blocks mcp6g01, mcp6g01r, and mcp6g01u. added a discussion on v in range vs. g. revision a (september 2006) original release of this document. downloaded from: http:///
mcp6g01/1r/1u/2/3/4 ds22004b-page 34 ? 2006 microchip technology inc. notes: downloaded from: http:///
? 2006 microchip technology inc. ds22004b-page 35 mcp6g01/1r/1u/2/3/4 product identification system to order or obtain information, e.g., on pricing or de livery, refer to the factory or the listed sales office . device: mcp6g01: single sga mcp6g01t: single sga (tape and reel for msop and soic) mcp6g01rt: single sga (tape and reel for sot-23-5) mcp6g01ut: single sga (tape and reel for sot-23-5) mcp6g02: dual sga mcp6g02t: dual sga (tape and reel for msop and soic) mcp6g03: single sga mcp6g03t: single sga (tape and reel for msop and soic) mcp6g04: quad sga mcp6g04t: quad sga (tape and reel for soic and tssop) temperature range: e = -40c to +125c package: ms = plastic msop, 8-lead ot = plastic small outline transistor (sot-23-5), 5-lead sn = plastic soic (150 mil body), 8-lead sl = plastic soic (150 mil body), 14-lead (mcp6g04) st = plastic tssop (4.4mm body), 14-lead (mcp6g04) part no. Cx /xx package temperature range device examples: a) mcp6g01-e/ms: extended temperature, 8ld msop. b) mcp6g01t-e/sn: tape and reel, extended temperature, 8ld soic. c) mcp6g01t-e/ot: tape and reel, extended temperature, 5ld sot-23-5. d) mcp6g01rt-e/ot: tape and reel, extended temperature, 5ld sot-23-5. e) mcp6g01ut-e/ot: tape and reel, extended temperature, 5ld sot-23-5. a) mcp6g02-e/ms: extended temperature, 8ld msop. b) mcp6g02t-e/sn: tape and reel, extended temperature, 8ld soic. a) mcp6g03-e/ms: extended temperature, 8ld msop. b) mcp6g03t-e/sn: tape and reel, extended temperature, 8ld soic. c) mcp6g03-e/sn: extended temperature, 8ld soic. a) mcp6g04t-e/sl: tape and reel, extended temperature, 14ld soic. b) mcp6g04t-e/st: tape and reel, extended temperature, 14ld tssop. c) mcp6g04-e/st: extended temperature, 14ld tssop. downloaded from: http:///
mcp6g01/1r/1u/2/3/4 ds22004b-page 36 ? 2006 microchip technology inc. notes: downloaded from: http:///
? 2006 microchip technology inc. ds22004b-page 37 information contained in this publication regarding device applications and the like is prov ided only for your convenience and may be superseded by updates. it is your responsibility to ensure that your application me ets with your specifications. microchip makes no representations or warranties of any kind whether express or implied, written or oral, statutory or otherwise, related to the information, including but not limited to its condition, quality, performance, merchantability or fitness for purpose . microchip disclaims all liability arising from this information and its use. use of microchip devices in life support and/or safe ty applications is entirely at the buyers risk, and the buyer agrees to defend, indemnify and hold harmless microchip from any and all damages, claims, suits, or expenses resulting fr om such use. no licenses are conveyed, implicitly or ot herwise, under any microchip intellectual property rights. trademarks the microchip name and logo, the microchip logo, accuron, dspic, k ee l oq , micro id , mplab, pic, picmicro, picstart, pro mate, powersmart, rfpic, and smartshunt are registered trademarks of microc hip technology incorporated in the u.s.a. and other countries. amplab, filterlab, migratable memory, mxdev, mxlab, seeval, smartsensor and the embedded control solutions company are registered tradema rks of microchip technology incorporated in the u.s.a. analog-for-the-digital age, application maestro, codeguard, dspicdem, dspicdem.net, dspicworks, ecan, economonitor, fansense, flexrom, fuzzylab, in-circuit serial programming, icsp, icepic, linear active thermistor, mindi, miwi, mpasm , mplib, mplink, pickit, picdem, picdem.net, piclab, pictail, powercal, powerinfo, powermate, powertool, real ice, rflab, rfpicdem, select mode, smart serial, smarttel, total endurance, uni/o, wiperlock and zena are trademarks of microchip technology incorporated in the u.s.a. and other countries. sqtp is a service mark of mi crochip technology incorporated in the u.s.a. all other trademarks mentioned herein are property of their respective companies. ? 2006, microchip technology incorporated, printed in the u.s.a., all rights reserved. printed on recycled paper. note the following details of the code protection feature on microchip devices: microchip products meet the specification cont ained in their particular microchip data sheet. microchip believes that its family of products is one of the mo st secure families of its kind on the market today, when used i n the intended manner and under normal conditions. there are dishonest and possibly illegal meth ods used to breach the code protection fe ature. all of these methods, to our knowledge, require using the microchip products in a manner outside the operating specif ications contained in microchips data sheets. most likely, the person doing so is engaged in theft of intellectual property. microchip is willing to work with the customer who is concerned about the integrity of their code. neither microchip nor any other semiconduc tor manufacturer can guarantee the security of their code. code protection does not mean that we are guaranteeing the product as unbreakable. code protection is constantly evolving. we at microchip are committed to continuously improving the code protection features of our products. attempts to break microchips c ode protection feature may be a violation of the digital millennium copyright act. if such acts allow unauthorized access to your softwa re or other copyrighted work, you may have a right to sue for relief under that act. microchip received iso/ts-16949:2002 certification for its worldwide headquarters, design and wafer fabrication facilities in chandler and tempe, arizona, gresham, oregon and mountain view, california. the companys quality system processes and procedures are for its pic ? 8-bit mcus, k ee l oq ? code hopping devices, serial eeproms, microperipherals, nonvolatile memory and analog products. in addition, microchips quality system for the design and manufacture of development systems is iso 9001:2000 certified. downloaded from: http:///
ds22004b-page 38 ? 2006 microchip technology inc. americas corporate office 2355 west chandler blvd. chandler, az 85224-6199 tel: 480-792-7200 fax: 480-792-7277 technical support: http://support.microchip.com web address: www.microchip.com atlanta alpharetta, ga tel: 770-640-0034 fax: 770-640-0307 boston westborough, ma tel: 774-760-0087 fax: 774-760-0088 chicago itasca, il tel: 630-285-0071 fax: 630-285-0075 dallas addison, tx tel: 972-818-7423 fax: 972-818-2924 detroit farmington hills, mi tel: 248-538-2250 fax: 248-538-2260 kokomo kokomo, in tel: 765-864-8360 fax: 765-864-8387 los angeles mission viejo, ca tel: 949-462-9523 fax: 949-462-9608 santa clara santa clara, ca tel: 408-961-6444 fax: 408-961-6445 toronto mississauga, ontario, canada tel: 905-673-0699 fax: 905-673-6509 asia/pacific asia pacific office suites 3707-14, 37th floor tower 6, the gateway habour city, kowloon hong kong tel: 852-2401-1200 fax: 852-2401-3431 australia - sydney tel: 61-2-9868-6733 fax: 61-2-9868-6755 china - beijing tel: 86-10-8528-2100 fax: 86-10-8528-2104 china - chengdu tel: 86-28-8665-5511 fax: 86-28-8665-7889 china - fuzhou tel: 86-591-8750-3506 fax: 86-591-8750-3521 china - hong kong sar tel: 852-2401-1200 fax: 852-2401-3431 china - qingdao tel: 86-532-8502-7355 fax: 86-532-8502-7205 china - shanghai tel: 86-21-5407-5533 fax: 86-21-5407-5066 china - shenyang tel: 86-24-2334-2829 fax: 86-24-2334-2393 china - shenzhen tel: 86-755-8203-2660 fax: 86-755-8203-1760 china - shunde tel: 86-757-2839-5507 fax: 86-757-2839-5571 china - wuhan tel: 86-27-5980-5300 fax: 86-27-5980-5118 china - xian tel: 86-29-8833-7250 fax: 86-29-8833-7256 asia/pacific india - bangalore tel: 91-80-4182-8400 fax: 91-80-4182-8422 india - new delhi tel: 91-11-4160-8631 fax: 91-11-4160-8632 india - pune tel: 91-20-2566-1512 fax: 91-20-2566-1513 japan - yokohama tel: 81-45-471- 6166 fax: 81-45-471-6122 korea - gumi tel: 82-54-473-4301 fax: 82-54-473-4302 korea - seoul tel: 82-2-554-7200 fax: 82-2-558-5932 or 82-2-558-5934 malaysia - penang tel: 60-4-646-8870 fax: 60-4-646-5086 philippines - manila tel: 63-2-634-9065 fax: 63-2-634-9069 singapore tel: 65-6334-8870 fax: 65-6334-8850 taiwan - hsin chu tel: 886-3-572-9526 fax: 886-3-572-6459 taiwan - kaohsiung tel: 886-7-536-4818 fax: 886-7-536-4803 taiwan - taipei tel: 886-2-2500-6610 fax: 886-2-2508-0102 thailand - bangkok tel: 66-2-694-1351 fax: 66-2-694-1350 europe austria - wels tel: 43-7242-2244-39 fax: 43-7242-2244-393 denmark - copenhagen tel: 45-4450-2828 fax: 45-4485-2829 france - paris tel: 33-1-69-53-63-20 fax: 33-1-69-30-90-79 germany - munich tel: 49-89-627-144-0 fax: 49-89-627-144-44 italy - milan tel: 39-0331-742611 fax: 39-0331-466781 netherlands - drunen tel: 31-416-690399 fax: 31-416-690340 spain - madrid tel: 34-91-708-08-90 fax: 34-91-708-08-91 uk - wokingham tel: 44-118-921-5869 fax: 44-118-921-5820 w orldwide s ales and s ervice 10/19/06 downloaded from: http:///

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