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this is information on a product in full production. march 2015 docid027588 rev 1 1/17 RHFLVDS2281 rad-hard, dual 4x4 crosspoint switch lvds datasheet - production data features ? lvds input/output ? multiple configuration: mux, repeater and splitter ? ansi tia/eia-644 compliant ? 400 mbps lvds (200 mhz) ? 200 mhz clock channel ? cold spare on all pins ? fail-safe function ? 3.3 v operating power supply ? 4.8 v absolute rating ? hermetic package ? power consumption: 220 mw at 3.3 v ? large input common mode: -4 v to +5 v ? guaranteed up to 300 krad tid ? sel immune up to 135 mev.cm2/mg ? set/seu immune up to 22 mev.cm2/mg description the RHFLVDS2281 is an 8-channel, 4x4 crosspoint switch base, on low voltage differential signaling (lvds) for low-power and high-speed communications. the two 4x4 multiplexers allow connection from any of the four inputs to any of the four outputs. packaged and qualified for use in aerospace environments in a low-power, fast-transmission standard, the RHFLVDS2281 operates at 3.3 v power supply (3.6 v max. operating and 4.8 v amr) and a common mode of -4 v to +5 v. the lvds outputs operate over a controlled impedance of 100-ohm transmission media that may be printed circuit board traces, back planes, or cables. the circuit features an intern al fail-safe function to ensure a known state in case of an input short circuit or a floating input. all pins have cold spare buffers to ensure they are in high impedance when v cc is tied to gnd. the RHFLVDS2281 can operate over a wide temperature range of -55 c to +125 c and it is housed in an hermetic ceramic flat-64 package. ceramic flat-64 the upper metallic lid is electrically connected to ground. table 1. device summary reference smd pin quality level package lead finish mass eppl (1) 1. eppl = esa preferred part list temp. range RHFLVDS2281k1 - engineering model ceramic flat-64 gold 1.94 g - -55 c to 125 c RHFLVDS2281k01v 5962f1423401 qml-v flight target www.st.com
contents RHFLVDS2281 2/17 docid027588 rev 1 contents 1 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 2 functional diagram and pin c onfiguration . . . . . . . . . . . . . . . . . . . . . . . 4 3 maximum ratings and operati ng conditions . . . . . . . . . . . . . . . . . . . . . . 6 4 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 5 test circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 6 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 6.1 ceramic flat-64 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 7 ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 8 shipping information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 9 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
docid027588 rev 1 3/17 RHFLVDS2281 functional description 17 1 functional description note: 1 a floating sl pin is equi valent to a low logic level 2 channels 5, 6, 7, and 8 behave like chann els 1, 2, 3 and 4 respectively (see also figure 2 ) note: vid = (vin+)-(vin-), l = low level, h = high level, x = don?t care, z = high impedance table 2. mux truth table sl1 sl2 sl3 sl4 out1 out2 out3 out4 mode 0000in1in1in3in3 splitter 0001in1in1in3in4splitter/r epeater 0010in1in1in1in1 splitter 0011in1in1in4in4 0100in1in2in3in3splitter/r epeater 0101in1in2in3in4re peater 0110in1in2in4in3repeater/switch 0111in1in2in4in4splitter/r epeater 1000in2in2in2in2 splitter 1001in2in1in3in4switch/r epeater 1010in2in1in4in3 switch 1011in3in3in3in3 splitter 1100in2in2in3in3 1101in2in2in3in4splitter/r epeater 1110in4in4in4in4 splitter 1111in2in2in4in4 table 3. enable (en) truth table en inputs outputs (in+) - (in-) out+ out- lxzz h or floating (internal pull-up) vid ? 0.1 v h l vid ? -0.1 v l h -0.1v < vid < +0.1 v unknown full fail-safe open/short or terminated hl
internal schematic and pin configuration RHFLVDS2281 4/17 docid027588 rev 1 2 internal schematic and pin configuration figure 1. internal schematic 6/ ,1 ,1 6/ ,1 ,1 6/ ,1 ,1 6/ ,1 ,1 &/.,1 &/.,1 vnhz pdwfk (1 287 287 (1 287 287 (1 287 287 (1 287 287 (1. &/.287 &/.287 08; [ 6/ ,1 ,1 6/ ,1 ,1 6/ ,1 ,1 6/ ,1 ,1 (1 287 287 (1 287 287 (1 287 287 (1 287 287 08; [
docid027588 rev 1 5/17 RHFLVDS2281 internal schematic and pin configuration 17 figure 2. pinout 1. power supplies are not internally separated. all vcc pins must be connected to the same potential. (1 ,1 ,1 (1 ,1 ,1 9&& *1' ,1 ,1 (1 ,1 ,1 (1 (1&. &/.,1 &/.,1 *1' (1 ,1 ,1 (1 ,1 ,1 9&& *1' ,1 ,1 (1 ,1 ,1 (1 6/ 287 287 6/ 287 287 9&& *1' 6/ 287 287 6/ 287 287 9&& &/.287 &/.287 *1' 6/ 287 287 6/ 287 287 9&& *1' 6/ 287 287 6/ 287 287
maximum ratings and operating conditions RHFLVDS2281 6/17 docid027588 rev 1 3 maximum ratings and operating conditions absolute maximum ratings are those values be yond which damage to the device may occur. functional operation under these conditions is not implied. table 4. absolute maximum ratings symbol parameter value unit v cc supply voltage (1) 1. all voltages, except the differential i/o bus voltage, are with respect to the network ground terminal. 4.8 v v i ttl inputs (operating or cold-spare) -0.3 to +4.8 v out lvds outputs (operating or coldspare) -0.3 to +4.8 v cm lvds common mode (operating or cold-spare) -5 to +6 t stg storage temperature range -65 to +150 c t j maximum junction temperature +150 r thjc thermal resistance junction to case (2) 2. short-circuits can cause excessive heating. destructive dissipation can result from short-circuits on the amplifiers. 20 c/w esd hbm: human body model ? all pins excepted lvds inputs and outputs ? lvds inputs and outputs vs. gnd 2 8 kv cdm: charge device model 500 v table 5. operating conditions symbol parameter min. typ. max. unit v cc supply voltage 3 3.3 3.6 v v cm static common mode - 4 + 5 t a ambient temperature range -55 +125 c
docid027588 rev 1 7/17 RHFLVDS2281 electrical characteristics 17 4 electrical characteristics total dose (mil-std-883 tm 1019) the products guaranteed in radiation within the rha qml-v system fully comply with the mil-std-883 tm 1019 specification. the RHFLVDS2281 is rha qml-v, tested and characterized in full compliance with the ? mil-std-883 specification, between 50 and 300 rad/s only (full cmos technology). all parameters provided in table 7: electrical characteristics table apply to both pre- and post-irradiation, as follows: ? all test are performed in accordance with mil-prf-38535 and test method 1019 of mil-std-883 for total ionizing dose (tid). ? the initial characterization is performed in qualification only on both biased and unbiased parts. ? each wafer lot is tested at high dose rate only, in the worst bias case condition, based on the results obtained duri ng the initial qualification. heavy ions the behavior of the product when submitted to heavy ions is not tested in production. heavy-ion trials are performe d on qualification lots only. table 6. radiations type characteristics value unit tid high-dose rate (50 - 300 rad/sec) 300 krad heavy ions sel immunity up to: ? (with a particle angle of 60 , at 125 c) 135 mev.cm 2 /mg sel immunity up to: ? (with a particle angle of 0 , at 125 c) 67 set/seu immunity up to: ? (at 25 c) 22
electrical characteristics RHFLVDS2281 8/17 docid027588 rev 1 in table 7 below, v cc = 3 v to 3.6 v, capa-load (cl) = 10 pf, typical values are at ? t amb = +25 c, min. and max values are at t amb = - 55 c and + 125 c unless otherwise specified. table 7. electrical characteristics table symbol parameter test conditions min. typ. max. unit whole circuit i ccl total enabled supply current, drivers and receivers enabled, not switching v id = 400 mv and ? load = 100 w on all channels 67 80 ma i ccz total disabled supply current, loaded or not loaded, drivers and receivers disabled v id = 400 mv ? en and enck = gnd 20 digital inputs en, enck, and sl v ih input voltage high 2 v cc v v il input voltage low gnd 0.8 i ih high level input current v cc = 3.6 v, v in = v cc -10 10 a i il low level input current v cc = 3.6 v, v in = 0 -10 10 i off ttl inputs power off leakage current v cc = 0 v, ? en and sl = 3.6 v -10 10 lvds inputs v tl differential input low threshold v cm = 1.2 v -100 mv -4 v < v cm < +5 v -130 v th differential input high threshold v cm = 1.2 v +100 -4 v < v cm < +5 v +130 v cl ttl input clamp voltage i cl = 18 ma 1.5 v v cmr common mode voltage range v id = 200 mvp-p - 4 +5 v cmrej common mode rejection (1) f = 10 mhz 300 mvp-p i id differential input current v id = 400 mvp-p -10 10 a i icm common mode input current v ic = - 4 v to + 5 v -70 70 i offin lvds input power-off leakage current (2) v cc = 0 v, v in = -4 v to 5 v -60 60 c in input capacitance 3 pf lvds outputs v oh output voltage high 1.65 v v ol output voltage low 0.925 v od differential output voltage 250 400 mv dv od change of magnitude of v od for complementary output states 10 v os offset voltage 1.125 1.45 v
docid027588 rev 1 9/17 RHFLVDS2281 electrical characteristics 17 dv os change of magnitude of v os for complementary output states 25 mv i os output short-circuit current v id = -400 mv and v out- = 0 v ? v id = +400 mv and v out+ = 0 v -9 ma i oz high impedance output current disabled, v out = 3.6 v or 0v -10 10 a i offout lvds outputs power-off leakage current v cc = 0 v, v out = 3.6 v -50 +50 t s input to sl setup time (3) refer to figure 5 1.6 ns t h input to sl hold time (3) 1.5 t sw sl to switched output (3) 5 t phld propagation delay time, high to low v id = 200 mvp-p, input pulse from 1.1 v to 1.3 v, v cm =1.2 v ? load: refer to figure 3 1.5 4 t plhd propagation delay time, low to high 1.5 4 t sk1 channel to channel skew (3)(4) v id = 200 mvp-p ? load: refer to figure 6 0.6 t sk2 chip to chip skew (3)(5) 0.7 t skd differential skew (6) ? (t phld -t plhd ) 0.6 t r output signal rise time refer to figure 4 0.9 t f output signal fall time 0.9 t plz propagation delay time, low level to high impedance output refer to figure 6 2.8 t phz propagation delay time, high level to high impedance output 2.8 t pzh propagation delay time, high impedance to high level output 2.5 t pzl propagation delay time, high impedance to low level output 2.5 fail-safe and cold-spare t d1 fail-safe to active time 1 s t d2 active to fail-safe time 1 1. guaranteed by characterization on bench. 2. all pins are floating except pin under test and v cc . 3. guaranteed by design. 4. t sk1 is the maximum delay time differ ence between drivers on the same device (with all inputs connected together). 5. t sk2 is the maximum delay time difference between outputs of a ll devices when they operate with the same supply voltage, at the same temperature. 6. t skd is the maximum delay ti me difference between t phld and t plhd ( see figure 4 ). table 7. electrical charact eristics table (continued) symbol parameter test conditions min. typ. max. unit
electrical characteristics RHFLVDS2281 10/17 docid027588 rev 1 cold sparing the RHFLVDS2281 features a cold spare inpu t and output buffer. in high reliability applications, cold sparing enables a redundant device to be tied to the data bus with its power supply at 0 v (v cc = gnd) without affecting the bus signals or injecting current from the i/os to the power supplies. cold sparing also allows redundant devices to be kept powered off so that they can be switched on only when required. this has no impact on the application. cold sparing is achieved by im plementing a high impedance between the i/os and v cc . esd protection is ensured through a non-conventional dedicated structure. fail-safe in many applications, inputs need a fail-safe function to avoid an uncertain output state when the inputs are not connected properly. in case of an lvds input short circuit or floating inputs, the lvds outputs remain in stable logic-high state.
docid027588 rev 1 11/17 RHFLVDS2281 test circuit 17 5 test circuit figure 3. voltage and current definition figure 4. timing and voltage definiti ons for differential output signal 1. all input pulses are supplied by a generator with the following characteristics: t r or t f 1 ns, ? f = 1 mhz, z o = 50 ? , and duty cycle = 50%. 2. the product is guaranteed with c l = 10 pf. v od lvds driver lvds receiver out+ out- v os =(v out+ + v out- )/2 v cm =(v in+ + v in- )/2 v id v in+ v in- in+ in- i i 100-ohm cl=10pf cl=10pf v in+ v in- t phld t plhd 50% 50% tf v od tr 80% 20% 80% 20%
test circuit RHFLVDS2281 12/17 docid027588 rev 1 figure 5. mux switch timings figure 6. enable and disable waveforms 1. all input pulses are supplied by a generator with the following characteristics on en: ? t r or t f 1 ns, f = 500 khz, pulse width = 500 ns. in0 in1 sl out ts t h t sw in0 in1 ts t h t sw in1 in0 en t pzh 50% 50% t pzl 50% 50% t phz t plz 50% 50% v out+ or v out- v out+ or v out- v od cl=10pf 50ohm lvds output cl=10pf out+ out- 50ohm 1.2v v os
docid027588 rev 1 13/17 RHFLVDS2281 package information 17 6 package information in order to meet environmental requirements, st offers these devices in different grades of ecopack ? packages, depending on their level of environmental compliance. ecopack ? specifications, grade definitions a nd product status are available at: www.st.com . ecopack ? is an st trademark.
package information RHFLVDS2281 14/17 docid027588 rev 1 6.1 ceramic flat-64 p ackage information figure 7. ceramic flat 64 package mechanical drawing 1. the upper metallic lid is elec trically connected to ground. table 8. ceramic flat 64 package mechanical data ref. dimensions millimeters inches min. typ. max. min. typ. max. a 2.41 2.66 2.92 0.095 0.105 0.115 a1 0.33 - - 0.013 - - b 0.18 0.2 0.23 0.007 0.008 0.009 c 0.15 0.2 0.25 0.006 0.008 0.010 d 20.91 21.11 21.31 0.823 0.831 0.839 e 8.64 8.76 8.89 0.340 0.345 0.350 e2 6.57 6.72 6.87 0.259 0.265 0.270 e3 - 1.02 - - 0.040 - e - 0.635 - - 0.025 - l 12.45 12.7 12.95 0.49 0.5 0.51 s1 - 0.61 - - 0.024 -
docid027588 rev 1 15/17 RHFLVDS2281 ordering information 17 7 ordering information note: contact your st sales office for information regarding the specific conditions for products in die form and qml-q versions. 8 shipping information date code the date code is structured as follows: ? engineering model: em xyywwz ? qml flight model: fm yywwz where: x = 3 (em only), assembly location rennes (france) yy = last two digits of the year ww = week digits z = lot index of the week table 9. order codes order code description temp. range package marking (1) 1. specific marking only. complete marking includes the following: ? - smd pin (on qml-v flight only) ? - st logo ? - date code (date the package was sealed) in yywwa (year, week, and lot index of week) ? - qml logo (q or v) ? - country of origin (fr = france). packing RHFLVDS2281k1 engineering model -55 c to 125 c ceramic flat-64 RHFLVDS2281k1 strip pack RHFLVDS2281k01v qml-v flight 5962f1423401vxc
revision history RHFLVDS2281 16/17 docid027588 rev 1 9 revision history table 10. document revision history date revision changes 04-mar-2015 1 initial release.
docid027588 rev 1 17/17 RHFLVDS2281 17 important notice ? please read carefully stmicroelectronics nv and its subsidiaries (?st?) reserve the right to make changes, corrections, enhancements, modifications, and improvements to st products and/or to this document at any time without notice. purchasers should obtain the latest relevant in formation on st products before placing orders. st products are sold pursuant to st?s terms and conditions of sale in place at the time of o rder acknowledgement. purchasers are solely responsible for the choice, selection, and use of st products and st assumes no liability for application assistance or the design of purchasers? products. no license, express or implied, to any intellectual property right is granted by st herein. resale of st products with provisions different from the information set forth herein shall void any warranty granted by st for such product. st and the st logo are trademarks of st. all other product or service names are the property of their respective owners. information in this document supersedes and replaces information previously supplied in any prior versions of this document. ? 2015 stmicroelectronics ? all rights reserved

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