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1 ?2017 integrated device technology, inc. september 22, 2017 description the 8s89832i is a high speed 1-to-4 differential-to-lvds fanout buffer. the 8s89832i is optimized for high speed and very low output skew, making it suitable for use in demanding applications such as sonet, 1 gigabit and 10 gigabit ethernet, and fibre channel. the internally terminated differential input and v ref _ ac pin allow other differential signal families such as lvpecl, lvds, and sstl to be easily interfaced to the input with minimal use of external components. the device also has an output enable pin that may be useful for system test and debug purposes. the 8s89832i is packaged in a small 3mm x 3mm 16-pin vfqfn package which makes it ideal for use in space-constrained applications. features four differential lvds output pairs in, nin input pairs can accept the following differential input levels: lvpecl, lvds, sstl 50 ? internal input termination to v t maximum output frequency: 2ghz output skew: 25ps (maximum) part-to-part skew: 200ps (maximum) propagation delay: 550ps (maximum) additive phase jitter, rms: 0.09ps (typical) full 2.5v supply mode -40c to 85c ambient operating temperature available in lead-free (rohs 6) package 8s89832i 16-lead vfqfn 3mm x 3mm x 0.925mm package body k package top view block diagram pin assignment 50 50 d clk q q0nq0 q1 nq1 q2 nq2 q3 nq3 in v t nin v ref_ac en 5 6 7 8 16 15 14 13 12 3 4 1211 10 9 q1 nq1 q2 nq2 in v t v ref_ac nin q3 nq3 v dd en q0 v dd gnd nq0 8 s8 9 8 3 2 i da t a she e t low sk e w , 1 -t o-4 di ffe re nt ia l-t o-lv ds fa nout buffe r
2 ?2017 integrated device technology, inc. september 22, 2017 8s89832i data sheet table 1. pin descriptionsnote: pullup refers to internal input resistors. see table 2, pin characteristics, for typical values. table 2. pin characteristics number name type description 1, 2 q1, nq1 output differe ntial output pair. lvds interface levels. 3, 4 q2, nq2 output differe ntial output pair. lvds interface levels. 5, 6 q3, nq3 output differe ntial output pair. lvds interface levels. 7, 14 v dd power positive supply pins. 8 en input pullup synchronizing clock enable. when low, qx outputs will go low and nqx outputs will go high on the next low transition at in inputs. input threshold is v dd /2v. includes a 37k ? pullup resistor. default state is high wh en left floating. the internal latch is clocked on the falling edge of the input signal in. see table 3a lvttl / lvcmos interface levels. 9 nin input inverting differential clock input. 50 ? internal input termination to v t . 10 v ref_ac output reference voltage for ac-coupled applications. 11 v t input termination input. 12 in input non-inverting differential clock input. 50 ? internal input termination to v t . 13 gnd power power supply ground. 15, 16 q0, nq0 output differe ntial output pair. lvds interface levels. symbol parameter test conditio ns minimum typical maximum units c in input capacitance 2p f r pullup input pullup resistor 37 k ?
3 ?2017 integrated device technology, inc. september 22, 2017 8s89832i data sheet function tables table 3a. control input function table note: en switches, the clock outputs are disabled or enabled following a falling input clock edge as shown in figure 1. figure 1. en timing diagram table 3b. truth table note 1: on next negative transit ion of the input signal (in). input outputs en q[0:3] nq[0:3] 0 disabled; low disabled; high 1 enabled enabled inputs outputs in nin en q[0:3] nq[0:3] 01101 10110 xx00 (note 1) 1 (note 1) en nin in nqx qx t pd t s t h v od v dd /2 v dd /2 v in
4 ?2017 integrated device technology, inc. september 22, 2017 8s89832i data sheet absolute maximum ratings stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. these ratings are stress specifications only. functional operat ion of product at these condit ions or any conditions beyond those listed in the dc characteristics or ac characteristics is not implied. exposure to absolute maximum rating conditions for extended periods may affect product reliability. dc electrical characteristics table 4a. power supply dc characteristics, v dd = 2.5v 5%, t a = -40c to 85c table 4b. lvcmos/lvttl dc characteristics, v dd = 2.5v 5%, t a = -40c to 85c item rating supply voltage, v dd 4.6v inputs, v i -0.5v to v dd + 0.5v outputs, i o continuous current surge current 10ma15ma input current, in, nin 50ma v t current, i vt 100ma input sink/source, i ref_ac 0.5ma operating temperature range, t a -40c to +85c package thermal impedance, ? ja , (junction-to-ambient) 74.7 ? c/w (0 mps) storage temperature, t stg -65 ? c to 150 ? c symbol parameter test conditio ns minimum typical maximum units v dd positive supply voltage 2.375 2.5 2.625 v i dd power supply current 95 ma symbol parameter test conditio ns minimum typical maximum units v ih input high voltage 1.7 v dd + 0.3 v v il input low voltage -0.3 0.7 v i ih input high current v dd = v in = 2.625v 10 a i il input low current v dd = 2.625v, v in = 0v -150 a
5 ?2017 integrated device technology, inc. september 22, 2017 8s89832i data sheet table 4c. differential dc characteristics, v dd = 2.5v 5%, t a = -40c to 85c note 1: v il should not be less than -0.3v. note 2: guaranteed by design. table 4d. lvds dc characteristics, v dd = 2.5v 5%, t a = -40c to 85c ac electrical characteristics table 5. ac characteristics, v dd = 2.5v 5%, t a = -40c to 85c note: electrical parameters are guaranteed over the specif ied ambient operating temperature r ange, which is established when t he device is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. th e device will meet specifications after thermal equilibrium has been reached under these conditions. all parameters are measured at ? 1.5ghz unless otherwise noted. note 1: measured from the differential input crossi ng point to the differential output crossing point. note 2: defined as skew between outputs at the same supply voltage and with equal load conditions. measured at the output differential cross points. note 3: this parameter is defined in accordance with jedec standard 65. note 4: defined as skew between outputs on di fferent devices operating at the same supp ly voltage, same temperature, same frequ ency and with equal load conditions. using the same type of inputs on each device, the outputs are me asured at the differential cros s points. symbol parameter test conditio ns minimum typical maximum units r in differential input resistance in, nin in to vt, nin to vt 40 50 60 ? v ih input high voltage in, nin 1.2 v dd v v il input low voltage in, nin 0 v ih C 0.15 v v in input voltage swing; note 1 0.15 1.2 v v diff_in differential input voltage swing 0.3 v i in input current; note 2 in, nin 35 ma v ref_ac reference voltage v dd C 1.40 v dd C 1.35 v dd C 1.30 v symbol parameter test conditio ns minimum typi cal maximum units v od differential output voltage 247 454 mv ? v od v od magnitude change 50 mv v os offset voltage 1.125 1.375 v ? v os v os magnitude change 50 mv symbol parameter test conditio ns minimum typical maximum units f out operating frequency 2g h z t pd propagation delay; (differential) note 1 300 550 ps t sk(o) output skew; note 2, 3 25 ps t sk(pp) part-to-part skew; note 3, 4 200 ps t jit buffer additive phase jitter, rms; refer to additive phase jitter section 200mhz, integration range: 12khz - 20mhz 0.09 ps t s /t h clock enable setup time en to in, nin 300 ps t r / t f output rise/fall time 20% to 80% 50 235 ps
6 ?2017 integrated device technology, inc. september 22, 2017 8s89832i data sheet additive phase jitter the spectral purity in a band at a specific offset from the fundamental compared to the power of the fundamental is called the dbc phase noise. this value is normally expressed using a phase noise plot and is most often the specified plot in many applications. phase noise is defined as the ratio of the noise power present in a 1hz band at a specified offset from the fundamental frequency to the power value of the fundamental. this ratio is expressed in decibels (dbm) or a ratio of the power in the 1hz band to the power in the fundamental. when the required offset is specified, the phase noise is called a dbc value, which simply means dbm at a specified offset from the fundamental. by investigating jitter in the frequency domain, we get a better understanding of its effects on the desired application over the entire time record of the signal. it is mathematically possible to calculate an expected bit error rate given a phase noise plot. as with most timing specifications, phase noise measurements has issues relating to the limitations of the equipment. often the noise floor of the equipment is higher than the noise floor of the device. this is illustrated above. the device meets the noise floor of what is shown, but can actually be lower. the phase noise is dependent on the input source and measurement equipment. the source generator ?ifr2042 10khz ? 56.4ghz low noise signal generator as external input to an agilent 8133a 3ghz pulse generator?. additive phase jitter @ 200mhz 12khz to 20mhz = 0.09ps (typical) ssb phase noise dbc/hz offset from carr ier frequency (hz)
7 ?2017 integrated device technology, inc. september 22, 2017 8s89832i data sheet parameter measureme nt information lvds output load ac test circuit part-to-part skew single-ended & differential input, output voltage swing differential input level output skew v dd nqx qx nqy qy t sk(pp) p art 1 p art 2 v in , v out 350mv (typical) v diff_in , v diff_out 700mv (typical) v ih cross points v in v il v in , v out v diff_in , v diff_ out single-ended voltage swing differential voltage swing = 2 x v in in nin v dd gnd in nin in nin qx nqx qy nqy
8 ?2017 integrated device technology, inc. september 22, 2017 8s89832i data sheet parameter measure ment information, continued output rise/fall time offset voltage setup differential output voltage setup propagation delay 20% 80% 80% 20% t r t f v od nq0, nq1 q0, q1 t pd nq0,nq1 q0,q1 nin in
9 ?2017 integrated device technology, inc. september 22, 2017 8s89832i data sheet application informationrecommendations for unused output pins outputs lvds outputs all unused lvds output pairs can be either left floating or terminated with 100 ? across. if they are left floating, we recommend that there is no trace attached. 2.5v lvpecl input with built-in 50 ? termination interface the in /nin with built-in 50 ? terminations accept lvds, lvpecl, sstl and other differential signals. both differential signals must meet the v pp and v cmr input requirements. figures 2a to 2d show interface examples for the in /nin with built-in 50 ? termination input driven by the most common driv er types. the input interfaces suggested here are examples only. if the driver is from another vendor, use their termination reco mmendation. please consult with the vendor of the driver component to confirm the driv er termination requirements. figure 2a. in/nin input with built-in 50 ? driven by an lvds driver figure 2c. in/nin input with built-in 50 ? driven by a cml driver figure 2b. in/nin input with built-in 50 ? driven by an sstl driver figure 2d. in/nin input with built-in 50 ? driven by an lvpecl driver sstl r1 25 r2 25 innin vt receiverwith built-in 50 2.5v 2.5v zo = 50 zo = 50
10 ?2017 integrated device technology, inc. september 22, 2017 8s89832i data sheet vfqfn epad thermal release path in order to maximize both the removal of heat from the package and the electrical performance, a land pattern must be incorporated on the printed circuit board (pcb) within the footprint of the package corresponding to the exposed metal pad or exposed heat slug on the package, as shown in figure 3. the solderable area on the pcb, as defined by the solder mask, should be at least the same size/shape as the exposed pad/slug area on the package to maximize the thermal/electrical performance. sufficient clearance should be designed on the pcb between the outer edges of the land pattern and the inner edges of pad pattern for the leads to avoid any shorts. while the land pattern on the pcb provides a means of heat transfer and electrical grounding from the package to the board through a solder joint, thermal vias are necessary to effectively conduct from the surface of the pcb to the ground plane(s). the land pattern must be connected to ground through these vias. the vias act as ?heat pipes?. the number of vias (i.e. ?heat pipes?) are application specific and dependent upon the package power dissipation as well as electrical conductivity requirements. thus, thermal and electrical analysis and/or testing are recommended to determine the minimum number needed. maximum thermal and electrical performance is achieved when an array of vias is incorporated in the land pattern. it is recommended to use as many vias connected to ground as possible. it is also recommended that the via diameter should be 12 to 13mils (0.30 to 0.33mm) with 1oz copper via barrel plating. this is desirable to avoid any solder wicking inside the via during the soldering process which may result in voids in solder between the exposed pad/slug and the thermal land. precautions should be taken to eliminate any solder voids between the exposed heat slug and the land pattern. note: these recommendations are to be used as a guideline only. for further information, please refer to the application note on the surface mount assembly of amkor?s thermally/ electrically enhance leadframe base package, amkor technology. figure 3. p.c. assembly for exposed pad thermal release path C side view (drawing not to scale) 2.5v lvds driver termination figure 4 shows a typical termination for lvds driver in characteristic impedance of 100 ? differential (50 ? single) transmission line environment. for buffer with multiple lvds driver, it is recommended to te rminate the unused outputs. figure 4. typical lvds driver termination solder solder pin pin exposed heat slug pin pad pin pad ground plane land pattern (ground pad) thermal via
11 ?2017 integrated device technology, inc. september 22, 2017 8s89832i data sheet power considerations this section provides information on power dissipation and junction temperature for the 8s89832i. equations and example calculations are also provided. 1. power dissipation. the total power dissipation for the 8s89832i is the sum of the co re power plus the analog power plus the power dissipated in th e load(s). the following is the power dissipation for v dd = 2.5v + 5% = 2.625v, which gives worst case results. note: please refer to section 3 for details on calculating power dissipated in the load. power (core) max = v dd_max * i dd_max = 2.625v * 95ma = 249.375mw 2. junction temperature. junction temperature, tj, is the temperature at the junction of the bond wire and bond pad dire ctly affects the reliability of the device. the maximum recommended junction temperature is 125c. limiting the in ternal transistor junction temperature, tj, to 125c ensures that the bond wire and bond pad temperature remains below 125c. the equation for tj is as follows: tj = ? ja * pd_total + t a tj = junction temperature ? ja = junction-to-ambient thermal resistance pd_total = total device power dissipation (e xample calculation is in section 1 above) t a = ambient temperature in order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance ? ja must be used. assuming no air flow and a multi-layer board, the appropriate value is 74.7c/w per table 6 below. therefore, tj for an ambient temperature of 85c with all outputs switching is: 85c + 0.249w * 74.7c/w = 103.6c. this is well below the limit of 125c. this calculation is only an example. tj will obviously vary dep ending on the number of loaded outputs, supply voltage, air flow and the type of board (multi-layer). table 6. thermal resistance ? ja for 16 lead vfqfn forced convection reliability information table 7. ? ja vs. air flow table for a 16 lead vfqfn transistor count the transistor count for 8s89832i is: 339 pin compatible with sy89832u. this device is pin and function compatib le and a suggested replacement for 889832. ? ja by velocity meters per second 012 . 5 multi-layer pcb, jedec standard test boards 74.7c/w 65.3c/w 58.5c/w ? ja by velocity meters per second 012 . 5 multi-layer pcb, jedec standard test boards 74.7c/w 65.3c/w 58.5c/w
disclaimer integrated device technology, inc. (idt) and its affiliated companies (herein referred to as ?idt?) reserve the righ t to modify the products and/or specifications described herein at any time, without notice, at idt?s sole discreti on. performance specifications and operating param eters of the described products are determined in an independent state and are not guaranteed to perform the same way when installed in customer products. the information contained herein is provi ded without representation or wa rranty of any kind, whether expr ess or implied, including, but not limited to, the suitabil ity of idt's products for any particular purpose, an implied warranty of merchantability, or non-infringement of t he intellectual property rights of others. this document is presented only as a guide and does not convey any license under intellectual property rights of idt or any third parties. idt's products are not intended for use in applications involvi ng extreme environmental conditions or in life support systems o r similar devices where the failure or malf unction of an idt product can be reasonably expected to significantly affect the health or safety of users. anyone using an idt product in such a manner does so at their own risk, absent an express, written agreement by idt. integrated device technology, idt and the idt logo are trademarks or registered trademarks of idt and its subsidiaries in the u nited states and other count ries. other trademarks used herein are the property of idt or their respective third party owners. for datasheet type definitions and a glossa ry of common terms, visit www.idt.com/go/glossary . integrated device technology, inc. all rights reserved. t e c h support www.idt.com/go/support sa le s 1-800-345-7015 or 408-284-8200 fax: 408-284-2775 www.idt.com/go/sales corpora t e h e a dqua rt e rs 6024 silver creek valley road san jose, ca 95138 usa www.idt.com 12 ?2017 integrated device technology, inc. september 22, 2017 8s89832i data sheet package outline drawings the package outline drawings are located in the last section of this document. the package information is the most current data available and is subject to change without notice or revision of this document. ordering information table 9. ordering information revision history part/order number marking package shipping packaging temperature 8s89832akilf 832a lead-free 16 lead vfqfn tube -40 ? c to 85 ? c 8S89832AKILFT 832a lead-free 16 lead vfqfn tape & reel -40 ? c to 85 ? c revision date description of change september 22, 2017 updated the package outline drawings ; however, no mechanical changes completed other minor improvements january 27, 2016 removed ics from part numbers where needed. general description - deleted ics chip. ordering information - deleted quantity from tape and reel. deleted lf note below table. updated header and footer. january 11, 2010 parameter measurement information - updated differential input level diagram.

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