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GS73024Ab 128k x 24 3mb asynchronous sram 8, 10, 12 ns 3.3 v v dd center v dd and v ss bga commercial temp industrial temp rev: 1.02 11/2004 1/11 ? 2003, gsi technology specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. features ? fast access time: 8, 10, 12 ns ? cmos low power operation: 250/200/170 ma at minimum cycle time ? single 3.3 v 0.3v power supply ? all inputs and outputs are ttl-compatible ? fully static operation ? industrial temperatur e option: ?40 to 85c ? package b: 14 mm x 22 mm, 119-bump, 1.27mm pitch bga description the GS73024A is a high speed cmos static ram organized as 131,072 words by 24 bits. stat ic design eliminates the need for external clocks or timing strobes. operating on a single 3.3 v power supply, and all inputs and outputs are ttl-compatible. the GS73024A is available in a 119-bump bga package. 119-bump ball gr id array package pin descriptions symbol description symbol description a 0 to a 16 address input dq 1 to dq 24 data input/output we write enable input oe output enable input ce chip enable input v ss ground v dd +3.3 v power supply we oe memory array row decoder column decoder address input control i/o buffer a 0 dq 1 dq 24 a 16 ce block diagram
GS73024Ab specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. rev: 1.02 11/2004 2/11 ? 2003, gsi technology 119-bump, 1.27 mm pitch bga pa d out?top view (package b) 1234567 anca 3 a 2 a 16 a 1 a 0 nc bnca 7 a 6 ce a 5 a 4 nc cdq 13 nc nc nc nc nc dq 12 ddq 14 v dd v ss v ss v ss v dd dq 11 edq 15 nc v dd v ss v dd nc dq 10 fdq 16 v dd v ss v ss v ss v dd dq 9 gdq 17 nc v dd v ss v dd nc dq 8 hdq 18 v dd v ss v ss v ss v dd dq 7 j v dd v ss v dd v ss v dd v ss v dd kdq 19 v dd v ss v ss v ss v dd dq 6 ldq 20 nc v dd v ss v dd nc dq 5 mdq 21 v dd v ss v ss v ss v dd dq 4 ndq 22 nc v dd v ss v dd nc dq 3 pdq 23 v dd v ss v ss v ss v dd dq 2 rdq 24 nc nc nc nc nc dq 1 tnca 11 a 10 we a 9 a 8 nc unca 15 a 14 oe a 13 a 12 nc
GS73024Ab specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. rev: 1.02 11/2004 3/11 ? 2003, gsi technology x: ?h? or ?l? note: permanent device damage may occur if absolute maximum ratings ar e exceeded. functional operation shall be restricted to recomme nded operating conditions. exposure to higher than recommended voltages for extended peri ods of time could affect device reliability . truth table ce oe we mode dq0 to dq23 v dd current h x x not selected high z isb1, isb2 l l h read data out i dd l x l write data in l h h output disable high z absolute maximum ratings parameter symbol rating unit supply voltage v dd ?0.5 to +4.6 v input voltage v in ?0.5 to v dd +0.5 ( 4.6 v max.) v output voltage v out ?0.5 to v dd +0.5 ( 4.6 v max.) v allowable bga power dissipation pd 1.5 w storage temperature t stg ?55 to 150 o c
GS73024Ab specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. rev: 1.02 11/2004 4/11 ? 2003, gsi technology notes: 1. input overshoot voltage should be less than v dd +2 v and not exceed 20 ns. 2. input undershoot voltage should be greater than ?2 v and not exceed 20 ns. notes: 1. tested at t a = 25c, f = 1 mhz 2. these parameters are sampled and are not 100% tested. recommended oper ating conditions parameter symbol min typ max unit supply voltage for -10/12 v dd 3.0 3.3 3.6 v supply voltage for -8 v dd 3.135 3.3 3.6 v input high voltage v ih 2.0 ? v dd +0.3 v input low voltage v il ?0.3 ? 0.8 v ambient temperature, commercial range t ac 0?70 o c ambient temperature, industrial range t ai ?40 ? 85 o c capacitance parameter symbol test condition max unit input capacitance c in v in = 0 v 5pf i/o capacitance c out v out = 0 v 7pf dc i/o pin characteristics parameter symbol test conditions min max input leakage current i il v in = 0 to v dd ?1 ua 1 ua output leakage current i ol output high z, v out = 0 to v dd ?1 ua 1 ua output high voltage v oh i oh = ?4 ma 2.4 ? output low voltage v ol i ol = +4 ma ?0.4 v
GS73024Ab specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. rev: 1.02 11/2004 5/11 ? 2003, gsi technology ac test conditions power supply currents parameter symbol test conditions 0 to 70c ?40 to 85c 8 ns 10 ns 12 ns 8 ns 10 ns 12 ns operating supply current i dd ce v il all other inputs v ih or v il min. cycle time i out = 0 ma 250 ma 200 ma 170 ma 260 ma 210 ma 180 ma standby current i sb1 ce v ih all other inputs v ih or v il min. cycle time 40 ma 40 ma 30 ma 50 ma 50 ma 40 ma standby current i sb2 ce v dd - 0.2v all other inputs v dd - 0.2v or 0.2v 10 ma 20 ma dq vt = 1.4 v 50 ? 30pf 1 dq 3.3 v output load 1 output load 2 589 ? 434 ? 5pf 1 notes: 1. includes scope and jig capacitance 2. test conditions as specified with output loading as shown in fig. 1 unless otherwise noted 3. output load 2 for t lz , t hz , t olz and t ohz parameter conditions input high level v ih = 2.4 v input low level v il = 0.4 v input rise time t = 1 v/ns input fall time tf = 1 v/ns input reference level 1.4 v output reference level 1.4 v output load fig. 1& 2
GS73024Ab specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. rev: 1.02 11/2004 6/11 ? 2003, gsi technology ac characteristics * these parameters are sampled and are not 100% tested read cycle 1: ce = oe = v il , we = v ih read cycle parameter symbol -8 -10 -12 unit min max min max min max read cycle time t rc 8 ? 10 ? 12 ? ns address access time t aa ? 8 ? 10 ? 12 ns chip enable access time (ce ) t ac ? 8 ? 10 ? 12 ns mux control to output valid (v/s ) t av ? 8 ? 10 ? 12 ns output enable to output valid (oe ) t oe ?4?5?6ns output hold from address change t oh 3?3?3?ns output hold from mux controls change t oh1 3?3?3?ns chip enable to output in low z (ce ) t lz * 3?3?3?ns output enable to output in low z (oe ) t olz * 0?0?0?ns chip disable to output in high z (ce ) t hz * ?4?5?6ns output disable to output in high z (oe ) t ohz * ?4?5?6ns t aa t oh t rc address data out previous data data valid
GS73024Ab specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. rev: 1.02 11/2004 7/11 ? 2003, gsi technology read cycle 2: we = v ih * these parameters are sampled and are not 100% tested write cycle parameter symbol -8 -10 -12 unit min max min max min max write cycle time t wc 8 ? 10 ? 12 ? ns address valid to end of write t aw 5.5?7?8?ns chip enable to end of write (ce ) t cw 5.5?7?8?ns data set up time t dw 4?5?6?ns data hold time t dh 0?0?0?ns write pulse width t wp 5.5?7?8?ns address set up time t as 0?0?0?ns write recovery time (we ) t wr 0?0?0?ns write recovery time ( ce ) t wr1 0?0?0?ns output low z from end of write t wlz * 2?3?3?ns write to output in high z t whz * ?4?5?6ns t aa t rc address t ac t lz t oe t olz ce oe data out t hz t ohz data valid high impedance
GS73024Ab specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. rev: 1.02 11/2004 8/11 ? 2003, gsi technology write cycle 1: we control write cycle 2: ce control t wc address ce we data in oe data out t aw t cw t as t wp t wr t dw t dh t wlz t whz data valid high impedance t wc address ce we data in oe data out t aw t wp t as t cw t wr1 t dw t dh data valid high impedance
GS73024Ab specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. rev: 1.02 11/2004 9/11 ? 2003, gsi technology package dimensions?119-bump pbga (package b, variation 1) bpr 1999.05.18 n p a b pin 1 corner k e f ct a b c d e f g h j k l m n p r t u g s d 1 2 3 4 5 6 7 package admissions - 119 pin pbga unit: mm symbol description min. nom. max a width 13.8 14.0 14.2 b length 21.8 22.0 22.2 c package height (including ball) 1.96 2.06 2.19 d ball size 0.60 0.75 0.90 e ball height 0.50 0.60 0.70 f package height (excluding balls) 1.46 1.70 g width between balls 1.27 k package height above board 0.80 0.90 1.00 n cut-out package width 12.00 p foot length 19.50 r width of package between balls 7.62 s length of package between balls 20.32 t variance of ball height 0.15 bottom view r top view side view
GS73024Ab specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. rev: 1.02 11/2004 10/11 ? 2003, gsi technology ordering information part number package access time temp. range status GS73024Ab-8 119-bump bga (var. 1) 8 ns commercial GS73024Ab-10 119-bump bga (var. 1) 10 ns commercial GS73024Ab-12 119-bump bga (var. 1) 12 ns commercial GS73024Ab-8i 119-bump bga (var. 1) 8 ns industrial GS73024Ab-10i 119-bump bga (var. 1) 10 ns industrial GS73024Ab-12i 119-bump bga (var. 1) 12 ns industrial * customers requiring tape and r eel should add the character ?t? to the end of the part number. for example: GS73024Ab-12t
GS73024Ab specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. rev: 1.02 11/2004 11/11 ? 2003, gsi technology revision history rev. code: old; new types of changes format or content page/revisions/reason GS73024A_r1 ? creation of new datasheet GS73024A_r1; GS73024A_r1_01 content ? corrected pinout (balls c3, c5 , r2, r3, r5, r6 changed to nc) ? corrected pin description tabl e to reflect pinout corrections ? corrected truth table to reflect pinout corrections GS73024A_r1_01; GS73024A_r1_02 content/format ? updated format ? added variation informti on to package mechanical

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