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Xilinx, Inc.
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| Part No. |
XC2S50E-6PQG208C XC2S300E-6PQG208I
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| OCR Text |
... features include block ram (to 288k bits), distributed ram (to 221,184 bits), 19 select- able i/o standards, and four dlls (delay-locked lo...bit true dual-port block ram fast interfaces to external ram - fully 3.3v pci compliant to 64 bits ... |
| Description |
50,000 SYSTEM GATE 1.8V FPGA - NOT RECOMMENDED for NEW DESIGN FPGA, 384 CLBS, 23000 GATES, 357 MHz, PQFP208
300,000 SYSTEM GATE 1.8V FPGA - NOT RECOMMENDED for NEW DESIGN FPGA, 1536 CLBS, 93000 GATES, 357 MHz, PQFP208
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| File Size |
810.82K /
103 Page |
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it Online |
Download Datasheet
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XILINX INC
Xilinx, Inc.
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| Part No. |
XC2S200E-6FG676C XC2S200E-6FG676I XC2S200E-6FGG456C XC2S200E-6FGG456I XC2S200E-6FGG676C XC2S200E-6FGG676I XC2S200E-6FTG256C XC2S200E-6FTG256I XC2S200E-6PQG208C XC2S200E-6PQG208I XC2S200E-6TQG144C XC2S200E-6TQG144I XC2S400E XC2S400E-6FG456C XC2S400E-6FG456I XC2S400E-6FG676C XC2S400E-6FG676I XC2S400E-6FGG456C XC2S400E-6FGG456I XC2S400E-6FGG676C XC2S400E-6FGG676I XC2S400E-6FT256C XC2S400E-6FT256I XC2S400E-6FTG256C XC2S400E-6FTG256I XC2S400E-6PQ208C XC2S400E-6PQ208I XC2S400E-6PQG208C XC2S400E-6PQG208I XC2S400E-6TQ144C XC2S400E-6TQ144I XC2S400E-6TQG144C XC2S400E-6TQG144I XC2S400E-7FG456C XC2S400E-7FG456I XC2S400E-7FG676C XC2S400E-7FG676I XC2S400E-7FGG456C XC2S400E-7FGG456I XC2S400E-7FGG676C XC2S50E-6FTG256C XC2S50E-7FTG256C XC2S100E-6FTG256C XC2S100E-7FTG256C XC2S150E-6FTG256C XC2S150E-7FTG256C XC2S200E-7FTG256C XC2S300E-6FTG256C XC2S300E-7FTG256C XC2S400E-7FTG256C XC2S600E-6FTG256C XC2S600E-7FTG256C XC2S600E XC2S600E-6FG456C XC2S600E-6FG456I XC2S600E-6FG676C XC2S600E-6FG676I XC2S600E-6FGG456C XC2S600E-6FGG456I XC2S600E-6FGG676C XC2S600E-6FGG676I XC2S600E-6FT256C XC2S600E-6FT256I XC2S600E-6FTG256I XC2S600E-6PQ208C XC2S600E-6PQ208I XC2S600E-6PQG208C XC2S600E-6PQG208I XC2S600E-6TQ144C XC2
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| OCR Text |
... Features include block RAM (to 288K bits), distributed RAM (to 221,184 bits), 19 selectable I/O standards, and four DLLs (Delay-Locked Loop...bit true dual-port block RAM
Typical System Gate Range (Logic and RAM) 23,000 - 50,000 37,000 - 100... |
| Description |
Second generation ASIC replacement technology
FPGA, 864 CLBS, 52000 GATES, 357 MHz, PBGA676
100,000 SYSTEM GATE 1.8V FPGA - NOT RECOMMENDED for NEW DESIGN FPGA, 864 CLBS, 52000 GATES, 357 MHz, PBGA256
400000 SYSTEM GATE 1.8 VOLT FPGA - NOT RECOMMENDED for NEW DESIGN FPGA, 864 CLBS, 52000 GATES, 357 MHz, PBGA456
300,000 SYSTEM GATE 1.8V FPGA - NOT RECOMMENDED for NEW DESIGN FPGA, 1536 CLBS, 93000 GATES, 400 MHz, PBGA456
Spartan-IIE FPGA
Product Availability
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| File Size |
957.68K /
108 Page |
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it Online |
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