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  address-parity Datasheet PDF File

For address-parity Found Datasheets File :: 4578    Search Time::4.547ms    
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    SC28L92 SC28L92A1A SC28L92A1B

Philips Semiconductors
NXP Semiconductors
Part No. SC28L92 SC28L92A1A SC28L92A1B
OCR Text ...A3 RESET 4 OPERATION CONTROL ADDRESS DECODE R/W CONTROL 16 BYTE RECEIVE FIFO WATCH DOG TIMER RECEIVE SHIFT REGISTER MRA0, 1, 2 CRA SRA RxDA INTERRUPT CONTROL INTRN IMR ISR GP INTERNAL DATABUS CHANNEL B (AS ABOVE) TxDB RxDB INPUT...
Description 3.3V- 5.0V Dual universal asynchronous receiver/transmitter (DUART3.3V- 5.0V双通用异步接收传送器)
3.3V-5.0V Dual Universal Asynchronous Receiver/Transmitter DUART

File Size 294.07K  /  44 Page

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    GS88118 GS88136 GS88118GT-11IT GS88118GT-11.5IT GS88118GT-11.5T GS88118GT-11T GS88118T-11.5I GS88118T GS88136T-11.5I GS8

GSI Technology, Inc.
Part No. GS88118 GS88136 GS88118GT-11IT GS88118GT-11.5IT GS88118GT-11.5T GS88118GT-11T GS88118T-11.5I GS88118T GS88136T-11.5I GS88136T-100 GS88136T-11I GS88136T-80 GS88136T-100I GS88136T-66I GS88136T-80I GS88118T-80 GS88118T-80I GS88118T-66I GS88118T-100I GS88118T-11I
OCR Text ...ts * Clock Control, registered, address, data, and control * Internal self-timed write cycle * Automatic power-down for portable application...Parity Functions The GS88118/36T features ByteSafe data security functions. See detailed discussion...
Description 512K x 18, 256K x 36 ByteSafe?/a> 8Mb Sync Burst SRAMs
512K x 18, 256K x 36 ByteSafe 8Mb Sync Burst SRAMs
512K x 18, 256K x 36 ByteSafe8Mb Sync Burst SRAMs
8Mb锛?12K x 18Bit) ByteSafe Synchronous Burst SRAM(8M浣??512K x 18浣??ByteSafe??????RAM锛?甫2浣???插?????板?锛?
512K X 18 CACHE SRAM, 11.5 ns, PQFP100 TQFP-100
512K X 18 CACHE SRAM, 11 ns, PQFP100 TQFP-100
8Mb56K x 36Bit)ByteSafe Synchronous Burst SRAM(8M位(256K x 36位)ByteSafe同步静态RAM(带2位脉冲地址计数器))
8Mb12K x 18Bit) ByteSafe Synchronous Burst SRAM(8M位(512K x 18位)ByteSafe同步静态RAM(带2位脉冲地址计数器))

File Size 468.59K  /  33 Page

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    GS88418

GSI Technology
Part No. GS88418
OCR Text ...ts * Clock Control, registered, address, data, and control * Internal self-timed write cycle * Automatic power-down for portable application...Parity I/O Pins This SRAM allows the user to configure the device to operate in Parity I/O active (...
Description 8Mb12K x 18Bit) S/DCD Synchronous Burst SRAM(8M位(512K x 18位)可选单/双循环取消同步静态RAM(位脉冲地址计数)

File Size 801.27K  /  25 Page

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    UPD98405 UPD98405GL-PMU

NEC[NEC]
Part No. UPD98405 UPD98405GL-PMU
OCR Text ...: Acknowledge 64-bit Transfer : Address/Data : Ground for Analog Part : Slave Address Select : Attention : +3.3 V Power Supply for Analog Pa...parity : Control Memory Write Enable : Device Select : DMA Read/Write : PHY Empty/Rx Cell Available ...
Description 155M ATM INTEGRATED SAR CONTROLLER

File Size 323.42K  /  64 Page

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    TI store
Part No. SN74SSQE32882 SN74SSQE32882ZALR SN74SSQE32882-17 SN74SSQE32882ZCJR
OCR Text ...o 56-bit registered buffer with address parity test one pair to four pair differential clock pll driver the sn74ssqe32882 has two basic modes of operation associated with the quad chip select 2 jedec sste32882 compliant enable ( qcsen) inp...
Description <font color=red>[Old version datasheet]</font> 28-BIT TO 56-BIT REGISTERED BUFFER WITH ADDRESS PARITY TEST ONE PAIR TO FOUR PAIR DIFFERENTIAL CLOCK PLL DRIVER

File Size 738.66K  /  10 Page

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