|
|
|
Pulse A Technitrol Comp...
|
Part No. |
W3906B0100
|
OCR Text |
... or to manufacture, use or sell anything it may desc ribe. reproduction, disclosure or use without specific written authorization of pulse is strictly forbi dden. for more information: pulse worldwide headquarters pulse/larsen antennas eu... |
Description |
LTE Primary GNSS FPC Antenna
|
File Size |
1,077.06K /
20 Page |
View
it Online |
Download Datasheet |
|
|
|
Maxim
|
Part No. |
MAX9378 MAX9377-MAX9378
|
OCR Text |
anything-to-LVPECL/LVDS Translators with Pin-Selectable Divide-by-Four
General Description
The MAX9377/MAX9378 are fully differential, highspeed, low-jitter anything-to-LVPECL and anything-toLVDS translators, respectively, with a selectab... |
Description |
anything-to-LVPECL/LVDS Translators with Pin-Selectable Divide-by-Four From old datasheet system
|
File Size |
154.74K /
9 Page |
View
it Online |
Download Datasheet |
|
|
|
Integrated Device Techn...
|
Part No. |
9DBV0241
|
OCR Text |
...y on this pin. do not connect anything to this pin. 2 vddr1.8 pwr 1.8v power for differential input clock (receiver). this vdd should be treated as an analog power rail and filtered appropriately. 3 clk_in in true input for differential... |
Description |
SMBus-selectable features
|
File Size |
307.15K /
17 Page |
View
it Online |
Download Datasheet |
|
|
|
Integrated Circuit Syst...
|
Part No. |
9DBV0241
|
OCR Text |
...y on this pin. do not connect anything to this pin. 2 vddr1.8 pwr 1.8v power for differential input clock (receiver). this vdd should be treated as an analog power rail and filtered appropriately. 3 clk_in in true input for differential... |
Description |
slew rate for each output
|
File Size |
307.06K /
17 Page |
View
it Online |
Download Datasheet |
|
|
|
Integrated Circuit Syst... Integrated Device Techn...
|
Part No. |
9DBV0231
|
OCR Text |
...y on this pin. do not connect anything to this pin. 2 vddr1.8 pwr 1.8v power for differential input clock (receiver). this vdd should be treated as an analog power rail and filtered appropriately. 3 clk_in in true input for differential... |
Description |
slew rate for each output SMBus-selectable features
|
File Size |
302.62K /
17 Page |
View
it Online |
Download Datasheet |
|
|
|
Integrated Device Techn...
|
Part No. |
9DBV0231AKILF 9DBV0231AKILFT 9DBV0231AKLFT 9DBV0231-16
|
OCR Text |
...y on this pin. do not connect anything to this pin. 2 vddr1.8 pwr 1.8v power for differential input clock (receiver). this vdd should be treated as an analog power rail and filtered appropriately. 3 clk_in in true input for differential... |
Description |
2-output 1.8V PCIe Gen1/2/3 Zero Delay /Fanout Buffer
|
File Size |
264.87K /
17 Page |
View
it Online |
Download Datasheet |
|
Price and Availability
|