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XILINX
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| Part No. |
XC2C32A
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| OCR Text |
...is I/O compatible with standard lvttl and lvcmos18, lvcmos25, and lvcmos33 (see Table 1). This device is also 1.5V I/O compatible with the u...lvcmos standard is used in 3.3V, 2.5V, 1.8V applications. CoolRunner-II CPLDs are also 1.5V I/O comp... |
| Description |
The CoolRunner-II 32-macrocell device
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| File Size |
101.46K /
13 Page |
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it Online |
Download Datasheet
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XILINX
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| Part No. |
XC2C32
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| OCR Text |
...is I/O compatible with standard lvttl and lvcmos18, lvcmos25, and lvcmos33 (see Table 1). This device is also 1.5V I/O compatible with the u...lvcmos standard is used in 3.3V, 2.5V, 1.8V applications. CoolRunner-II CPLDs are also 1.5V I/O comp... |
| Description |
The CoolRunner-II 32-macrocell device
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| File Size |
97.22K /
13 Page |
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it Online |
Download Datasheet |
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ICS
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| Part No. |
M2026
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| OCR Text |
...as well as single-ended lvcmos, lvttl Loss of Lock (LOL) output pin; Narrow Bandwidth control input (NBW pin) AutoSwitch (AUTO pin) - automatic (non-revertive) reference clock reselection upon clock failure Acknowledge pin (REF_ACK pin) ... |
| Description |
SAW PLL for Frequency Translation with automatic reference clock reselection, Loss of Lock indicator, and Hitless Switching options
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| File Size |
333.73K /
12 Page |
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it Online |
Download Datasheet |
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ON Semiconductor
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| Part No. |
NB4N316M
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| OCR Text |
...t signals: lvpecl, cml, lvcmos, lvttl, or lvds. these signals will be translated to cml, operating up to 2.0 ghz or 2.5 gb/s, respectively. as such, the nb4n316m is ideal for sonet, gige, fiber channel, backplane and other clock or data dis... |
| Description |
3.3 V AnyLevel Receiver to CML Driver/Translator with Input Hysteresis - 2.0 GHz Clock / 2.5 Gb/s Data
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| File Size |
185.03K /
12 Page |
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it Online |
Download Datasheet |
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Integrated Device Techn...
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| Part No. |
IDT8T49N222I
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| OCR Text |
...ullup i 2 c clock input. lvcmos/lvttl interface levels. 19 reserved unused must be left unconnected. 20 s_a1 input pulldown i 2 c address bit 1. lvcmos/lvttl interface levels. 21 s_a0 input pulldown i 2 c address bit 0. lvcmos/lvttl interf... |
| Description |
Fourth generation FemtoClock
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| File Size |
697.58K /
40 Page |
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it Online |
Download Datasheet |
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Xilinx Inc
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| Part No. |
XC2C512-6PQ208C
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| OCR Text |
... 512 macrocell features lvcmos, lvttl, SSTL, and HSTL I/O implementations. See Table 1 for I/O standard voltages. The lvttl I/O standard is a general purpose EIA/JEDEC standard for 3.3V applications that use an lvttl input buffer and Push-P... |
| Description |
Complex PLD - Datasheet Reference
From old datasheet system
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| File Size |
113.77K /
20 Page |
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it Online |
Download Datasheet |
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NS
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| Part No. |
DS90C385AM
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| OCR Text |
...ter converts 28 bits of lvcmos/ lvttl data into four LVDS (Low Voltage Differential Signaling) data streams. A phase-locked transmit clock is transmitted in parallel with the data streams over the fifth LVDS link. Every cycle of the transmi... |
| Description |
3.3V Programmable LVDS Transmitter 24-Bit Flat Panel Display Link-87.5 MHz
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| File Size |
628.65K /
14 Page |
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it Online |
Download Datasheet |
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Integrated Device Techn...
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| Part No. |
IDT8T49N205I
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| OCR Text |
...fferential clock input. lvcmos/lvttl interface levels. 0 = clk0, nclk0 (default) 1 = clk1, nclk1 5 clk0 input pulldown non-inverting differential clock input. 6nclk0input pullup/ pulldown inverting differential clock input. v cc /2 defaul... |
| Description |
Fourth Generation FemtoClock
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| File Size |
732.27K /
41 Page |
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it Online |
Download Datasheet |
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Price and Availability
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