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quicklogic
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| Part No. |
QL5432 QL5432_DS
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| OCR Text |
...able byte enables as a master * Zero-wait-state write and one-wait-state read Target interface * Target interface supports retry, disconnect...phase of the master transaction. When high, Mst_BE[3:0] pushed into internal FIFO using Mst_WrData_V... |
| Description |
33 MHz/32-Bit PCI Master/Target with Embedded
Programmable Logic and Dual Port SRAM
From old datasheet system
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| File Size |
716.33K /
27 Page |
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it Online |
Download Datasheet
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Electronic Theatre Controls, Inc.
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| Part No. |
HEDS-9711
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| OCR Text |
...alog peak-to-peak signal to the zero current point. state width state width the number of electrical degrees between a transition state 1 in channel a and the neighboring transition in channel b. state 2 there are four states per cycle, eac... |
| Description |
200 lpi Analog Output Small Optical Encoder Modules 200低截获概率模拟输出小型光学编码器模块
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| File Size |
244.90K /
8 Page |
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it Online |
Download Datasheet |
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Motorola Inc
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| Part No. |
MPC9608
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| OCR Text |
zero delay clock buffer the mpc9608 is a 3.3 v compatible, 1:10 pll based zero-delay buffer. with a very wide frequency range and low outpu...phase to the reference clock phase, providing virtually zero propagation delay. this enables nested ... |
| Description |
1:10 LVCMOS Zero Delay Clock Buffer
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| File Size |
462.32K /
12 Page |
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it Online |
Download Datasheet |
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Price and Availability
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