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Datasheet File OCR Text: |
ASAHI KASEI [AK8430] AK8430 6CH CCD 1CH : 25M sample/sec 3CH : 10Mx3 sample/sec () 2CH(): 15Mx2 sample/sec 6CH(): 5Mx6 sample/sec : 1.05Vp-p(typ.)/ 2.10Vp-p(typ.) 6CH CDS (Correlated Double Sampling:) 2 (9bit, 90mV) (8bit, 90mV, 6 ) PGA x1~x4 (8bit, 6 ) (CDS ~ ADC) 10bit, DNL :0.5 LSB (typ.) INL :1.0 LSB (typ.) : 0.5 LSBrms (typ.)(PGA gain=1) 4 I/F 5V/3.3V : 600mW (typ.) : 64pin LQFP, 0.5mm, 10mmx10mm PVDD PVSS AVDD AVSS DVDD DVSS VREF2 VREF1 CN0_O DM0_O CN0_E DM0_E CN1_O DM1_O CN1_E DM1_E CN2_O DM2_O CN2_E DM2_E CDS/ Clamp CDS/ Clamp CDS/ Clamp CDS/ Clamp CDS/ Clamp CDS/ Clamp Timing Generator PGA Black Correction DAC MUX 8 Offset CN0O Offset CN0E Offset CN1O Offset CN1E Offset CN2O Offset CN2E registerR2~R7 Reference Voltage VRNGP VRNGN 10bit ADC 10 M U X VD0-9 8 Gain CN0O Gain CN0E Gain CN1O Gain CN1E Gain CN2O Gain CN2E registerR8~RD 9 PDB RESETB TEST Control Serial I/F CKCL CKSH ADCLK BD0-8 SDCLK SDENB SDIN SDOUT 2000/11 ASAHI KASEI [AK8430] CDS/Clamp CCD // CDS 1Vpp(typ.)/2Vpp(typ.)2Vpp 1/2 MUX(CDS/Clamp ) / PGA 10bit ADC 1236 Black Correction DAC DAC / DAC DAC 90mV 9 PGA(Programmable Gain Amplifier) 4 8bit GainCNnO, GainCNnE(n=0~2) PGA 10bit ADC 10bit,30MSPS ADC Reference Voltage AK8430 VREF1 VREF2 VREF1,VREF2 Timing Generator Control Serial I/F ADCLK,CKCL CHSH AK8430 4 2000/11 ASAHI KASEI [AK8430] VREF1 VREF2 VRNGP VRNGN AVDD AVSS TDI BD8 BD7 BD6 BD5 BD4 BD3 BD2 BD1 BD0 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 DM0_O CN0_O AVSS DM0_E CN0_E AVSS DM1_O CN1_O AVDD AVSS DM1_E CN1_E AVSS DM2_O CN2_O AVSS 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 TOP VIEW 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 DVSS DVDD VD9 VD8 VD7 VD6 VD5 PVSS PVDD VD4 VD3 VD2 VD1 VD0 SDOUT SDIN 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 SDENB SDCLK RESETB ADCLK CKSH CKCL PDB TEST AVDD AVSS ATOUT_N ATOUT_P ATIN_N ATIN_P CN2_E DM2_E BD0-8 SDCLK SDENB SDIN SDOUT VD0-9 33-41 15 16 17 18 19-23, 26-30 13 12 I/O I I I I O O I/F (MSB=BD8) 100k I/F I/F ADC ADC (MSB=VD9) &h000&h3FF ADC CKSH ADCLK P14 Fig.6 ON High : OFF Low : ADCLK CKSH I I CKCL 11 I 2000/11 ASAHI KASEI [AK8430] RESETB PDB TEST TDI 14 10 9 42 I/O I I I I Low Low DVSS DVSS AVSS CDS AVSS ADC ( ADC ) +5V(typ.) . +3.3V +5V(typ.) . +5V(typ.) CN0_O,CN1_O ,CN2_O CN0_E,CN1_E ,CN2_E DM0_O,DM0_E DM1_O,DM1_E DM2_O,DM2_E 50,56,63 I 53,60,2 I 49,52 55,59 62,1 I VREF1 VREF2 VRNGP VRNGN DVDD DVSS PVDD PVSS AVDD AVSS 48 47 46 45 31 32 24 25 8,44,57 7,43,51 54,58,61 64 3,4 5,6 O O O ATIN_P,ATIN_N ATOUT_P ATOUT_N I O AVSS AVSS 2000/11 ASAHI KASEI [AK8430] (16 ) 0 (16 ) 00 D7 D6 D5 D4 D3 D2 D1 D0 I/F PGA X ) F 01XXXXXXb 1 2 3 4 5 6 7 8 9 A B C D E F 07 80 80 80 80 80 80 00 00 00 00 00 00 XX CN0_O CN0_E CN1_O CN1_E CN2_O CN2_E PGA CN0_O PGA CN0_E PGA CN1_O PGA CN1_E PGA CN2_O PGA CN2_E ( 8bit) X X X ( 2bit) 2000/11 ASAHI KASEI [AK8430] R0 D0 0: 1: AK8430 10bit ADC RERF 0 RE D1 0: 1: R2~R7 BD0~BD8 BD0~BD8 BD0~BD8 AC CDS D2 PGA 0: 1: D5-D3 6CH D5 D4 0 0 0 0 0 1 1 0 1 0 1 1 D3 0 1 X 0 1 X CN0OCN1OCN2OCN0ECN1ECN2E CN2OCN0OCN1OCN2ECN0ECN1E CN1OCN2OCN0OCN1ECN2ECN0E CN0OCN2OCN1OCN0ECN2ECN1E CN1OCN0OCN2OCN1ECN0ECN2E CN2OCN1OCN0OCN2ECN1ECN0E ( 1 ) X Don't Care 3CH D5 D4 0 0 0 0 0 1 1 0 1 0 1 1 D3 0 1 X 0 1 X CN0OCN1OCN2O CN2OCN0OCN1O CN1OCN2OCN0O CN0OCN2OCN1O CN1OCN0OCN2O CN2OCN1OCN0O 2000/11 ASAHI KASEI [AK8430] D6 0: 1: CDS CDS CKCL CCD (CKSH) CCD CKCL=H CCD AK8430 VREF1 VREF1 (CKSH) CKCL VREF1 S/H CCD CCD CKCL S/H S/H: - S/H (CKSH) CDS (CKSH) Fig.1I/F (CKSH)CKSH ADCLK P15 AC 89 D7 0: 1: R1 D1,D0 D1 0 0 1 1 D0 0 1 0 1 1 CH: 3 CH: CN0O,CN1O,CN2O 2 CH: CN0O,CN0E 6 CH: CN0O,CN0E,CN1O,CN1E,CN2O,CN2E 2000/11 7 2Vpp (2.10Vpp typ.) 1Vpp (1.05Vpp typ.) ASAHI KASEI [AK8430] D7-D2 D7 0 0 0 0 0 1 D6 0 0 0 0 1 0 D5 0 0 0 1 0 0 D4 0 0 1 0 0 0 D3 0 1 0 0 0 0 D2 1 0 0 0 0 0 CN0O (default) CN0E CN1O CN1E CN2O CN2E (R0:D0=1) 1CH (R1:D1,D0=0,0) R2-R7 D7-D0 () 11111111 11111110 : 10000000 (default) : 00000000 R8-RD PGA = 335 / (335-) (default =0=1) -90mV : : 0mV : 90mV 5 4 Gain 3 2 1 0 0 100 200 Register Data Fig.2 PGA 2000/11 ASAHI KASEI [AK8430] RE,RF/D1-D0 ADC ADC 1LSB LSB R0/D0 1 RE,RF/D1~D0 PGA 1 ADCLKCKCL,CKSH R0/D0 1 SDEN ADCLK R0/D0 50 0 10 RE 8 RF 2 (REx4+RF) Black Correction FF PGA Level Shift 10bit ADC RE,RF &hFF ADC ADC 00 CODEADC(Of(FF)) CODEADC(Of(00)) &h00 ADC Fig.3 2000/11 ASAHI KASEI [AK8430] RF D6 0: 1: (default) 0 DM0~2_O/E DM0~2_O/E DM0~2_O/E AVSS CDS , D7 CDS 0: 1: (default) 0 1 AK8430 SDCLK SDIN SDOUT SDENB Fig.4 AK8430 SDCLK SDIN SDOUT SDENB Fig.5 RX X X A3 A2 A1 A0 High Z D7 D6 D5 D4 D3 D2 D1 D0 WX X X A3 A2 A1 A0 High Z D7 D6 D5 D4 D3 D2 D1 D0 2000/11 ASAHI KASEI [AK8430] DVSS=PVSS=AVSS=0V Min. Max. VD -0.3 6.5 V VP -0.3 6.5 V VA -0.3 6.5 V VTD -0.3 VD+0.3 V VTA -0.3 VA+0.3 V Tstg -55 125 C Tsol 260C, 10sec VAVD,VP DVSS=PVSS =AVSS=0V Min. Typ. Max. VD 4.75 5.0 5.25 V VP 3.15 - 5.25 V VAVD,VP VA 4.75 5.0 5.25 V () Ta 0 70 C () VA High 1 Low 1 2.4 VIL 0.8 V VIA ADCLK 2.4 Vpp High Low CKSH CKCL 1) V IOH=-0.5mA PVDD High VOH -0.5 Low VOL 0.5 V IOL=2mA IL -10 10 A VI=DVDD VI=DVSS ILPU BD0-8 -100 10 A 1) AC VIH ASAHI KASEI [AK8430] ( VD,VP,VA=5V5%,Ta=0-70C) Min. Typ. Max. 2V 1.89 2.10 2.31 Vp-p 1V 0.945 1.05 1.155 MSPS 1CH 25 2CH 15 3CH 10 6CH 5 MSPS 1CH 5.0 2CH 1.7 3CH 2.5 6CH 0.8 32 pF CN0O,CN1O,CN2O CN0E,CN1E,CN2E M CN0O,CN1O,CN2O 1 CN0E,CN1E,CN2E VREF1 2.88 3.2 3.52 V VREF2 1.95 2.2 2.45 V ON 50 CDS 1.0 k 4 8 mV C=0.22uF, =2Vpp, 8000 7 14 mV C=0.22uF, =2Vpp, 8000 =10sec ( 1) ( 2) 9 bit 72 90 mV 2 4 LSB ADC PGA(Programmable Gain Amp.) ( 3) 8 bit 0.95 1.0 1.05 4.0 4.2 4.4 2000/11 ASAHI KASEI [AK8430] ( 4) ( VD,VA,VP=5V5%,Ta=0-70C) Min. Typ. Max. ADC 10 bit 3FFH 0.9 1.0 1.1 Vp-p 000H -50 0 50 mVp-p 1 3 LSB 0.5 +1.5 LSB -1.0 0.5 LSBrms PGA min. 0.75 LSBrms PGA max. 1 LSB ADCLK=25MHz 5 LSB ADCLK=30MHz ( 1) ( 2) ( 3) ( 4) 1.8Vpp 1.8Vpp 0.2Vpp ADC PGA 1 0.2Vpp VREF1+90[mV] VREF1 9bit (8bit) VREF1-90[mV] 1FFH 100H 000H 10bit 000H Black VREF1-1.05[V] @1V Range (ATT=0dB) VREF1-1.1[V] 3FFH White Black Correction Range Video ADC Range VREF1-2.10[V] @2V Range (ATT=-6dB) Input Stage Fig.6 2000/11 ASAHI KASEI [AK8430] AC ADCLK CKCL CKSH Min. ( VD,VP,VA=5V5%,Ta=0-70C) Typ. Max. 6 nsec Low 2V 6 nsec High -2V ( VD,VP,VA=5V5%,Ta=0-70C) Min. Typ. Max. 33.3 nsec 6CH 33.3 nsec 2CH 33.3 nsec 3CH 40 nsec 1CH 15 nsec 15 nsec 10 nsec ( 1) 200 nsec 6CH 66.7 nsec 2CH 100 nsec 3CH 40 nsec 1CH 12 1.5T- nsec ( 1)( 3) 17 0 nsec nsec nsec nsec nsec nsec nsec nsec nsec 12 T-13 T-13 nsec nsec nsec C=20pF ( 2) ( 2) ( 3) ( 3) No. 1 ADCLK (T) ADCLK 2 3 4 5 ADCLK Low ADCLK High CKCL CKCL, CKSH ADCLK ADCLK CKCL CKCL CKSH 6 7 CKSH CKSH CKSH CKSH ( CKCL ) 8 CKSH CKSH 0 ( ADCLK ) 9 CKSH CKSH 15 ( ADCLK ) 10 CKSH CKSH 12 ( ADCLK ) 11 CN0~2 CNnO 10 ( CKCL ) CNnE 12 CN0~2 CNnO 2 ( CKCL ) CNnE 13 CN0~2 CNnO 15 ( CKSH ) CNnE 14 CN0~2 CNnO 3 ( CKSH ) CNnE 15 CKCL CKCL 0 ( CKSH ) 16 VD0~9 VD0~9 ( ADCLK ) 17 BD0~8 BD0~8 13 ( ADCLK ) 18 BD0~8 BD0~8 13 ( ADCLK ) ( 1) ( 2) AC 2000/11 ASAHI KASEI [AK8430] ( 3) AC 8 9 CKSH 8 9 ADCLK CKSH .AND. ADCLK (CKSH) I/F S/H S/H H S H S S H S H S H S H S H S H S H S H Fig.7 (6CH ) CKCL S/H MUX D/A S/H I/F CDS 1CH (CKSH) - S/H - Fig.8 Fig.7 ,Fig.8 (CKSH) I/F ( S/H) (CKSH){CKSH .AND. INV(ADCLK)} (CKSH) CKSH ADCLK (8) {CKSH .AND. INV(ADCLK)} ADCLK (9) MUX 2000/11 ASAHI KASEI [AK8430] No. 19 20 21 22 23 24 25 26 27 28 29 30 SDCLK SDCLK Low SDCLK High SDIN ( SDCLK ) SDIN ( SDCLK ) SDENB ( SDCLK ) SDENB ( SDCLK ) SDENB High SDOUT ( SDCLK ) SDOUT ( SDENB ) RESETB SDCLK SDCLK SDCLK SDCLK SDIN SDIN SDENB SDENB SDENB SDOUT SDOUT RESETB I/F ( VD,VP,VA=5V5%,Ta=0-70C) Min. Typ. Max. 80 nsec 40 nsec 40 nsec 1360 nsec 20 nsec 20 40 40 40 30 0 20 nsec nsec nsec nsec nsec nsec nsec C=20pF C=20pF 19 20 21 SDCLK 1 2 15 16 19 20 21 1 2 8 9 10 16 23 24 SDIN 22 23 24 22 SDOUT 25 SDENB Hi-Z 26 27 25 Hi-Z 28 26 29 27 Fig.9 AK8430 Fig.10 AK8430 30 RESETB Fig.11 2000/11 ASAHI KASEI [AK8430] CDS CN0(n+1) CN1(n+1) CN2(n+1) 14 15 6 n9 10 17 18 11 12 Analog Input CKCL CN0(n) CN1(n) CN2(n) 4 7 13 CKSH 23 1 8 n+1 5 ADCLK BD0~8 CN0O(n) CN2O(n) CN1E(n) CN2E(n) (CKSH) 16 CN1O(n) CN0E(n) VD0~9 CN0O(n-2) CN2O(n-2) CN1E(n-2) CN0O(n-1) CN1O(n-2) CN0E(n-2) CN2E(n-2) 7 CKSH ADCLK Fig.12 6CH Analog Input CKCL 11 4 12 7 CN0(n) 13 14 15 6 8 n 10 5 9 CN0(n+1) CKSH 3 1 2 n+1 ADCLK BD0~8 (CKSH) 17 18 CN0O(n) CN0E(n) 16 VD0~9 CN0O(n-5) CN0E(n-5) CN0O (n-4) 7 CKSH ADCLK Fig.13 2CH 2000/11 ASAHI KASEI CN0O(n) CN1O(n) CN2O(n) CN0O(n+1) CN1O(n+1) CN2O(n+1) CN0O(n+2) CN1O(n+2) CN2O(n+2) [AK8430] Analog Input CKCL 5 n-1 4 7 15 6 n 10 11 12 13 14 CKSH 8 9 n+1 n+2 ADCLK BD0~8 23 1 17 18 CN0O(n) CN2O(n) CN1O(n+1) CN2O(n+1) (CKSH) 16 CN1O(n) CN0O(n+1) VD0~9 CN0O(n-4) CN2O(n-4) CN1O(n-3) CN2O(n-3) CN1O(n-4) CN0O(n-3) 7 CKSH ADCLK Fig.14 3CH Analog Input CKCL CN0O(n) CN0O(n+1) CN0O(n+2) 47 15 5 6 n 11 12 13 14 CKSH 2 n-1 3 1 8 10 9 n+1 n+2 ADCLK 17 18 CN0O(n) CN0O(n+1) CN0O(n+2) BD0~8 (CKSH) CN0O(n-1) 16 VD0~9 CN0O(n-9) CN0O(n-8) CN0O(n-7) 7 CKSH ADCLK Fig.15 1CH 2000/11 ASAHI KASEI [AK8430] Analog Input CKCL CN0(Dummy) CN1(Dummy) CN2(Dummy) 4 7 6 13 14 15 Dummy 9 10 17 18 11 12 CN0(Dummy) CN1(Dummy) CN2(Dummy) CKSH 23 1 8 Dummy 5 ADCLK BD0~8 (CKSH) Dummy Dummy Dummy Dummy Dummy Dummy Dummy Dummy Dummy Dummy Dummy Dummy 16 VD0~9 Dummy Dummy Dummy Dummy Dummy Dummy Dummy Dummy Dummy Dummy Dummy Dummy CN0(Dummy) CN1(Dummy) Analog CN2(Dummy) Input 13 CN0(n) CN1(n) CN2(n) 14 CN0(n+1) CN1(n+1) CN2(n+1) CKCL 6 n9 10 17 18 n+1 5 CKSH 8 ADCLK BD0~8 23 1 CN0O(n) CN2O(n) CN1E(n) CN2E(n) (CKSH) 16 CN1O(n) CN0E(n) VD0~9 CN0O(n-2) CN2O(n-2) CN1E(n-2) CN2E(n-2) CN1O(n-2) CN0E(n-2) 7 CKSH ADCLK Fig.16 6CH () 2000/11 ASAHI KASEI [AK8430] Analog Input CKCL 11 4 12 7 CN0(Dummy) 13 14 15 6 8 Dummy 10 9 5 CN0(Dummy) CKSH 3 1 2 Dummy ADCLK BD0~8 (CKSH) 17 Dummy Dummy 18 Dummy Dummy 16 VD0~9 Dummy Dummy Dummy Dummy Analog Input CKCL CN0(n) 13 14 CN0(n+1) 6 CKSH 3 1 2 8 n 10 9 5 n+1 ADCLK BD0~8 (CKSH) 17 18 CN0O(n) CN0E(n) 16 VD0~9 CN0O(n-5) CN0E(n-5) CN0O(n-4) 7 CKSH ADCLK Fig.17 2CH () 2000/11 ASAHI KASEI [AK8430] Analog Input CKCL CN0O(Dummy) CN1O(Dummy) CN2O(Dummy) 11 12 4 7 5 CN0O(Dummy) CN1O(Dummy) CN2O(Dummy) 15 6 9 8 10 Dummy CN0O(n) CN1O(n) CN2O(n) 13 14 CN0O(n+1) CN1O(n+1) CN2O(n+1) CKSH Dummy n n+1 ADCLK BD0~8 Dummy 2 3 1 17 18 Dummy Dummy Dummy Dummy CN2O(n-1) CN0O(n) CN1O(n) CN2O(n) CN0O(n+1) (CKSH) 16 VD0~9 Dummy Dummy Dummy Dummy Dummy Dummy CN2O(n-4) CN1O(n-3) CN0O(n-2) CN0O(n-3) CN2O(n-3) 7 CKSH ADCLK Fig.18 3CH () Analog Input CKCL CN (Dummy) 11 12 4 7 CN (Dummy) 15 6 10 2 CN (n) 13 14 CN (n+1) 5 CKSH Dummy 9 3 n 8 n+1 ADCLK 1 17 Dummy CN (n) 18 CN (n+1) BD0~8 (CKSH) 16 Dummy VD0~9 Dummy Dummy CN (n-9) CN (n-8) 7 CKSH ADCLK Fig.19 1CH () 2000/11 ASAHI KASEI [AK8430] CDS Cs: 0.01uF AVDD DVDD 0.1uF DM0_O Cs Sensor Cs Sensor Cs Sensor 0.1uF Cs Sensor Sensor Cs CN0_O AVSS DM0_E CN0_E AVSS DM1_O CN1_O AVDD AVSS DM1_E CN1_E AVSS DM2_O CN2_O AVSS VREF1 VREF2 VRNGP VRNGN AVDD AVSS TDI BD8 BD7 BD6 BD5 BD4 BD3 BD2 BD1 BD0 0.1uF Sensor 0.1uF 0.1uF 10uF Cs Fig.20 CDS 0.1uF DVSS DVDD VD9 VD8 VD7 VD6 VD5 PVSS PVDD VD4 VD3 VD2 VD1 VD0 SDOUT SDENB 0.1uF 0.1uF 47k SDCLK RESETB ADCLK CKSH CKCL PDB TEST AVDD AVSS ATOUT_N ATOUT_P ATIN_N ATIN_P CN2_E DM2_E AVDD 0.1uF +5V AVDD 0.1uF SDIN DVDD 10uF 2 10uF 0.1uF 2000/11 ASAHI KASEI [AK8430] Cs: 0.22uF Cd: 0.22uF AVDD DVDD 0.1uF DM0_O Cd Sensor Sensor Sensor Cs Cd Cs Cd Cs 0.1uF Cd Sensor Sensor Cs Cd Cs CN0_O AVSS DM0_E CN0_E AVSS DM1_O CN1_O AVDD AVSS DM1_E CN1_E AVSS DM2_O CN2_O AVSS Cd Cs VREF1 VREF2 VRNGP VRNGN AVDD AVSS TDI BD8 BD7 BD6 BD5 BD4 BD3 BD2 BD1 BD0 0.1uF Sensor 0.1uF 0.1uF 10uF Fig.21 0.1uF DVSS DVDD VD9 VD8 VD7 VD6 VD5 PVSS PVDD VD4 VD3 VD2 VD1 VD0 SDOUT SDENB 0.1uF 0.1uF 47k SDCLK RESETB ADCLK CKSH CKCL PDB TEST AVDD AVSS ATOUT_N ATOUT_P ATIN_N ATIN_P CN2_E DM2_E AVDD 0.1uF +5V AVDD 0.1uF SDIN DVDD 10uF 2 10uF 0.1uF 2000/11 ASAHI KASEI [AK8430] 12.00.3 10 48 49 33 32 1.70 Max 1.40 0.100.10 12.00.3 64 1 16 17 0.5 0.210.05 0.170.05 0.10 M 1.0 0~10 0.10 0.450.2 (1) 1 ( 1 ) (2) (3) : AK8430 (4) : XXXXXXX (7 ) 4 : 3 : (5) : JAPAN AKM AK8430 XXXXXXX JAPAN 2000/11 ASAHI KASEI [AK8430] 2000/11 |
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