|
|
 |
MITSUBISHI[Mitsubishi Electric Semiconductor]
|
Part No. |
MH16S64APHB-8 MH16S64APHB-6 MH16S64APHB-7
|
OCR Text |
...-6 -7,-8 -6 -7,-8
N/A 22.5ns 20ns 15ns 20ns 22.5ns 20ns 45ns 50ns
MIT-DS-0377-0.1
MITSUBISHI ELECTRIC 4 / 55 ) (
17.Mar.2000
Preliminary Spec.
Some contents are subject to change without notice.
MITSUBISHI LSIs
MH16S64... |
Description |
1,073,741,824-BIT (16,777,216 - WORD BY 64-BIT)Synchronous DRAM
|
File Size |
685.07K /
55 Page |
View
it Online |
Download Datasheet
|
|
|
 |
MITSUBISHI[Mitsubishi Electric Semiconductor]
|
Part No. |
MH16S64PHB-8 MH16S64PHB-10 MH16S64PHB-7
|
OCR Text |
...s 13ns 15ns 6ns 7ns 8ns N/A N/A 20ns 30ns 20ns 20ns 30ns 50ns 60ns
24
SDRAM Access form Clock(2nd highest CAS latency)
-7 -8 -10
tAC for CL=2 25 26 27 28 29 30 SDRAM Cycle time(3rd highest CAS latency)
SDRAM Access form Clock(3... |
Description |
1073741824-BIT (16777216 - WORD BY 64-BIT)SynchronousDRAM
|
File Size |
586.33K /
55 Page |
View
it Online |
Download Datasheet
|
|
|
 |
MITSUBISHI[Mitsubishi Electric Semiconductor]
|
Part No. |
MH16S64PHC-8 MH16S64PHC-10 MH16S64PHC-7
|
OCR Text |
...s 13ns 15ns 6ns 7ns 8ns N/A N/A 20ns 30ns 20ns 20ns 30ns 50ns 60ns
24
SDRAM Access form Clock(2nd highest CAS latency)
-7 -8 -10
tAC for CL=2 25 26 27 28 29 30 SDRAM Cycle time(3rd highest CAS latency)
SDRAM Access form Clock(3... |
Description |
1073741824-BIT (16777216 - WORD BY 64-BIT)SynchronousDRAM
|
File Size |
587.13K /
55 Page |
View
it Online |
Download Datasheet
|
|
|
 |
MOSEL-VITELIC
|
Part No. |
V827316K04SATG-B1
|
OCR Text |
...mum row precharge time (=t rp ) 20ns 20ns 20ns 50h 50h 50h 28 minimum row activate to row active delay(=t rrd ) 15ns 15ns 15ns 3ch 3ch 3ch
mosel vitelic v827316k04satg 5 v827316k04satg rev. 1.4 january 2002 29 minimum ras to cas delay(=t ... |
Description |
16M X 72 DDR DRAM MODULE, 0.8 ns, DMA184
|
File Size |
100.16K /
13 Page |
View
it Online |
Download Datasheet
|
|
|
 |
MOSEL-VITELIC
|
Part No. |
V827332K04SATG-A0
|
OCR Text |
...ow precharge time (=t rp ) 20ns 20ns 20ns 50h 50h 50h 28 minimum row activate to row active delay(=t rrd ) 15ns 15ns 15ns 3ch 3ch 3ch
6 mosel vitelic v827332k04satg v827332k04satg rev. 1.1 july 2001 29 minimum r... |
Description |
32M X 72 DDR DRAM MODULE, 0.75 ns, DMA184
|
File Size |
370.21K /
14 Page |
View
it Online |
Download Datasheet
|
|

Price and Availability
|